From a66a0b3de010fdd2101e8bc908c62890c14221dc Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Mon, 17 Jul 2023 14:55:56 +0100 Subject: [PATCH 01/64] Checkin initial bios files --- src/flashcart/ed64/ed64_internal.c | 630 +++++++++++++++++++++++++++++ src/flashcart/ed64/ed64_internal.h | 147 +++++++ src/menu/rom_database.h | 2 + 3 files changed, 779 insertions(+) create mode 100644 src/flashcart/ed64/ed64_internal.c create mode 100644 src/flashcart/ed64/ed64_internal.h diff --git a/src/flashcart/ed64/ed64_internal.c b/src/flashcart/ed64/ed64_internal.c new file mode 100644 index 00000000..c17db294 --- /dev/null +++ b/src/flashcart/ed64/ed64_internal.c @@ -0,0 +1,630 @@ +#include + +#include "ed64_internal.h" + + + +#define REG_CFG 0 +#define REG_STATUS 1 +#define REG_DMA_LEN 2 +#define REG_DMA_RAM_ADDR 3 +#define REG_MSG 4 +#define REG_DMA_CFG 5 +#define REG_SPI 6 +#define REG_SPI_CFG 7 +#define REG_KEY 8 +#define REG_SAV_CFG 9 +#define REG_SEC 10 +#define REG_VER 11 +#define REG_GPIO 12 + +#define REG_CFG_CNT 16 +#define REG_CFG_DAT 17 +#define REG_MAX_MSG 18 +#define REG_MAX_VER 19 +#define REG_FL_ADDR 20 +#define REG_FL_DATA 21 + +#define STATE_DMA_BUSY 1 +#define STATE_DMA_TOUT 2 +#define STATE_USB_TXE 4 +#define STATE_USB_RXF 8 +#define STATE_SPI 16 + +#define DCFG_SD_TO_RAM 1 +#define DCFG_RAM_TO_SD 2 +#define DCFG_USB_TO_RAM 3 +#define DCFG_RAM_TO_USB 4 + + +#define SAV_EEP_ON 1 +#define SAV_SRM_ON 2 +#define SAV_EEP_SIZE 4 +#define SAV_SRM_SIZE 8 +#define SAV_RAM_BANK 128 +#define SAV_RAM_BANK_APPLY 32768 + +#define ED_CFG_SDRAM_ON 1 +#define ED_CFG_SWAP 2 +#define ED_CFG_WR_MOD 4 +#define ED_CFG_WR_ADDR_MASK 8 +#define ED_CFG_RTC_ON 32 +#define ED_CFG_GPIO_ON 96 +#define ED_CFG_DD_ON 256 +#define ED_CFG_DD_WE 512 + +#define REGS_BASE 0xA8040000 + +#define MAX_MSG_SKIP_FW_INIT (1 << 8) +#define MAX_MSG_SKIP_TV_INIT (1 << 9) +#define MAX_MSG_TV_TYPE1 (1 << 10) +#define MAX_MSG_TV_TYPE2 (1 << 11) +#define MAX_MSG_SKIP_SD_INIT (1 << 12) +#define MAX_MSG_SD_TYPE (1 << 13) +#define MAX_MSG_HOT_START (1 << 14) + + +uint32_t bi_reg_rd(uint32_t reg); +void bi_reg_wr(uint32_t reg, uint32_t data); +void bi_dma_r(void * ram_address, unsigned long pi_address, unsigned long len); +void bi_dma_w(void * ram_address, unsigned long pi_address, unsigned long len); +void bi_dma_read(void *ram, uint32_t addr, uint32_t len); +void bi_dma_write(void *ram, uint32_t addr, uint32_t len); + +static uint16_t spi_cfg; +uint8_t bi_ram_bank; +uint8_t bi_save_type; + +#define REG_LAT 0x04 +#define REG_PWD 0x04 + +#define ROM_LAT 0x40 +#define ROM_PWD 0x12 + +void bi_io_reg_v2(uint32_t addr, uint32_t dat) { + + *(volatile uint32_t *) (ROM_ADDR); + *(volatile uint32_t *) (ROM_ADDR + addr) = dat; +} + +void bi_io_reg_v3(uint32_t addr, uint16_t dat) { + + bi_reg_wr(REG_FL_ADDR, addr); + bi_reg_wr(REG_FL_DATA, dat); +} + +void bi_init_v2() { + + uint8_t buff[512]; + uint16_t cfg = bi_reg_rd(REG_CFG); + + bi_reg_wr(REG_CFG, 0); + bi_io_reg_v2(0xaa / 4 * 4, 0x00980098); + bi_dma_read_rom(buff, 0, 1); + bi_io_reg_v2(0xaa / 4 * 4, 0x00f000f0); + bi_dma_read_rom(buff, 0, 1); + bi_reg_wr(REG_CFG, cfg); + +} + +void bi_init_v3() { + + uint8_t buff[1024]; + uint16_t cfg = bi_reg_rd(REG_CFG); + + bi_reg_wr(REG_CFG, 0); + bi_reg_wr(REG_CFG_CNT, 161); + bi_io_reg_v3(0x55, 0x98); + bi_dma_read_rom(buff, 0, 2); + bi_io_reg_v3(0x55, 0xF0); + bi_dma_read_rom(buff, 0, 2); + bi_dma_read_rom(buff, 1024, 2); + bi_dma_read_rom(buff, 1024 + 256 - 2, 2); + bi_reg_wr(REG_CFG_CNT, 1); + + bi_reg_wr(REG_CFG, cfg); +} + +uint8_t bi_init() { + + uint16_t max_ver; + uint16_t max_msg; + uint8_t cold_start; + + + IO_WRITE(PI_BSD_DOM2_LAT_REG, REG_LAT); + IO_WRITE(PI_BSD_DOM2_PWD_REG, REG_PWD); + + + bi_reg_wr(REG_KEY, 0x1234); + bi_reg_wr(REG_CFG, 0x0000); + + + max_msg = bi_reg_rd(REG_MAX_MSG); + cold_start = (max_msg & MAX_MSG_HOT_START) == 0 ? 1 : 0; + if (cold_start) { + max_msg |= MAX_MSG_HOT_START; + bi_reg_wr(REG_MAX_MSG, max_msg); + } + + max_ver = bi_reg_rd(REG_MAX_VER); + if ((max_ver & 0xf000) >= 0x2000) { + bi_init_v3(); + } else { + bi_init_v2(); + } + + + + spi_cfg = SPI_CFG_SS | BI_SPI_SPD_LO; + bi_reg_wr(REG_CFG, ED_CFG_SDRAM_ON); + bi_reg_wr(REG_SPI_CFG, spi_cfg); + bi_save_type = 0; + + + return cold_start; +} + +void bi_reset_spx() { + + uint16_t cfg = bi_reg_rd(REG_CFG); + + bi_reg_wr(REG_CFG, 0x8000); + bi_sleep(100); + bi_reg_wr(REG_CFG, cfg); + bi_sleep(100); +} + +uint32_t bi_reg_rd(uint32_t reg) { + + *(volatile uint32_t *) (REGS_BASE); + return *(volatile uint32_t *) (REGS_BASE + reg * 4); +} + +void bi_reg_wr(uint32_t reg, uint32_t data) { + + *(volatile uint32_t *) (REGS_BASE); + *(volatile uint32_t *) (REGS_BASE + reg * 4) = data; + *(volatile uint32_t *) (ROM_ADDR); + +} + +uint8_t bi_dma_busy() { + + while ((bi_reg_rd(REG_STATUS) & STATE_DMA_BUSY) != 0); + return bi_reg_rd(REG_STATUS) & STATE_DMA_TOUT; +} + +uint8_t bi_usb_rd_busy() { + + return bi_reg_rd(REG_STATUS) & STATE_USB_RXF; +} + +uint8_t bi_usb_wr_busy() { + + return bi_reg_rd(REG_STATUS) & STATE_USB_TXE; +} + +uint8_t bi_usb_rd(uint32_t saddr, uint32_t slen) { + + saddr /= 4; + while (bi_usb_rd_busy() != 0); + + bi_reg_wr(REG_DMA_LEN, slen - 1); + bi_reg_wr(REG_DMA_RAM_ADDR, saddr); + bi_reg_wr(REG_DMA_CFG, DCFG_USB_TO_RAM); + + if (bi_dma_busy() != 0)return EVD_ERROR_FIFO_TIMEOUT; + + return 0; +} + +uint8_t bi_usb_wr(uint32_t saddr, uint32_t slen) { + + saddr /= 4; + while (bi_usb_wr_busy() != 0); + + bi_reg_wr(REG_DMA_LEN, slen - 1); + bi_reg_wr(REG_DMA_RAM_ADDR, saddr); + bi_reg_wr(REG_DMA_CFG, DCFG_RAM_TO_USB); + + if (bi_dma_busy() != 0)return EVD_ERROR_FIFO_TIMEOUT; + + return 0; +} + +uint16_t bi_spi_busy() { + + return bi_reg_rd(REG_STATUS) & STATE_DMA_BUSY; +} + +uint8_t bi_spi(uint8_t data) { + + bi_reg_wr(REG_SPI, data); + while (bi_spi_busy()); + return bi_reg_rd(REG_SPI); +} + +void bi_spi_nr(uint8_t data) { + + bi_reg_wr(REG_SPI, data); + while (bi_spi_busy()); +} + +void bi_set_spi_spd(uint16_t speed) { + + spi_cfg &= ~3; + spi_cfg |= speed; + bi_reg_wr(REG_SPI_CFG, spi_cfg); +} + +void bi_sd_mode(uint16_t mode) { + + spi_cfg &= ~(SPI_CFG_1BIT | SPI_CFG_RD | SPI_CFG_DAT); + spi_cfg |= mode; + bi_reg_wr(REG_SPI_CFG, spi_cfg); +} + +uint8_t bi_spi_read_to_rom(uint32_t saddr, uint16_t slen) { + + saddr /= 4; + + bi_reg_wr(REG_DMA_LEN, slen - 1); + bi_reg_wr(REG_DMA_RAM_ADDR, saddr); + bi_reg_wr(REG_DMA_CFG, DCFG_SD_TO_RAM); + + if (bi_dma_busy() != 0)return EVD_ERROR_MMC_TIMEOUT; + + return 0; +} + +void bi_swap_on() { + uint16_t cfg = bi_reg_rd(REG_CFG); + cfg |= ED_CFG_SWAP; + bi_reg_wr(REG_CFG, cfg); +} + +void bi_swap_off() { + uint16_t cfg = bi_reg_rd(REG_CFG); + cfg &= ~ED_CFG_SWAP; + bi_reg_wr(REG_CFG, cfg); +} + +uint8_t bi_get_save_type() { + + return bi_save_type; +} + +void bi_set_save_type(uint8_t type) { + + uint16_t save_cfg; + uint8_t eeprom_on, sram_on, eeprom_size, sram_size, ram_bank; + bi_save_type = type; + eeprom_on = 0; + sram_on = 0; + eeprom_size = 0; + sram_size = 0; + ram_bank = bi_ram_bank; + + + switch (type) { + case SAVE_TYPE_EEP16k: + eeprom_on = 1; + eeprom_size = 1; + break; + case SAVE_TYPE_EEP4k: + eeprom_on = 1; + break; + case SAVE_TYPE_SRAM: + sram_on = 1; + break; + case SAVE_TYPE_SRAM128: + sram_on = 1; + sram_size = 1; + break; + case SAVE_TYPE_FLASH: + sram_on = 0; + sram_size = 1; + break; + default: + sram_on = 0; + sram_size = 0; + ram_bank = 1; + break; + } + + save_cfg = 0; + if (eeprom_on)save_cfg |= SAV_EEP_ON; + if (sram_on)save_cfg |= SAV_SRM_ON; + if (eeprom_size)save_cfg |= SAV_EEP_SIZE; + if (sram_size)save_cfg |= SAV_SRM_SIZE; + if (ram_bank)save_cfg |= SAV_RAM_BANK; + save_cfg |= SAV_RAM_BANK_APPLY; + + bi_reg_wr(REG_SAV_CFG, save_cfg); + +} + +void bi_read_bios(void *dst, uint16_t saddr, uint16_t slen) { + + uint16_t cfg = bi_reg_rd(REG_CFG); + + cfg &= ~ED_CFG_SDRAM_ON; + bi_reg_wr(REG_CFG, cfg); + + bi_dma_read_rom(dst, saddr, slen); + + cfg |= ED_CFG_SDRAM_ON; + bi_reg_wr(REG_CFG, cfg); +} + +void bi_dma_read_rom(void *ram, uint32_t saddr, uint32_t slen) { + + bi_dma_read(ram, ROM_ADDR + saddr * 512, slen * 512); + +} + +void bi_dma_write_rom(void *ram, uint32_t saddr, uint32_t slen) { + + bi_dma_write(ram, ROM_ADDR + saddr * 512, slen * 512); +} + +void bi_dma_read_sram(void *ram, uint32_t addr, uint32_t len) { + + volatile uint32_t piLatReg = IO_READ(PI_BSD_DOM2_LAT_REG); + volatile uint32_t piPwdReg = IO_READ(PI_BSD_DOM2_PWD_REG); + volatile uint32_t piPgsReg = IO_READ(PI_BSD_DOM2_PGS_REG); + volatile uint32_t piRlsReg = IO_READ(PI_BSD_DOM2_RLS_REG); + + IO_WRITE(PI_BSD_DOM2_PGS_REG, 0x0D); + IO_WRITE(PI_BSD_DOM2_RLS_REG, 0x02); + IO_WRITE(PI_BSD_DOM2_LAT_REG, 0x05); + IO_WRITE(PI_BSD_DOM2_PWD_REG, 0x0C); + + bi_dma_read(ram, SRAM_ADDR + addr, len); + + IO_WRITE(PI_BSD_DOM2_LAT_REG, piLatReg); + IO_WRITE(PI_BSD_DOM2_PWD_REG, piPwdReg); + IO_WRITE(PI_BSD_DOM2_PGS_REG, piPgsReg); + IO_WRITE(PI_BSD_DOM2_RLS_REG, piRlsReg); +} + +void bi_dma_write_sram(void *ram, uint32_t addr, uint32_t len) { + + volatile uint32_t piLatReg = IO_READ(PI_BSD_DOM2_LAT_REG); + volatile uint32_t piPwdReg = IO_READ(PI_BSD_DOM2_PWD_REG); + volatile uint32_t piPgsReg = IO_READ(PI_BSD_DOM2_PGS_REG); + volatile uint32_t piRlsReg = IO_READ(PI_BSD_DOM2_RLS_REG); + + IO_WRITE(PI_BSD_DOM2_PGS_REG, 0x0D); + IO_WRITE(PI_BSD_DOM2_RLS_REG, 0x02); + IO_WRITE(PI_BSD_DOM2_LAT_REG, 0x05); + IO_WRITE(PI_BSD_DOM2_PWD_REG, 0x0C); + + bi_dma_write(ram, SRAM_ADDR + addr, len); + + + IO_WRITE(PI_BSD_DOM2_LAT_REG, piLatReg); + IO_WRITE(PI_BSD_DOM2_PWD_REG, piPwdReg); + IO_WRITE(PI_BSD_DOM2_PGS_REG, piPgsReg); + IO_WRITE(PI_BSD_DOM2_RLS_REG, piRlsReg); + +} + +uint16_t bi_msg_rd() { + + return bi_reg_rd(REG_MSG); +} + +void bi_msg_wr(uint16_t val) { + + bi_reg_wr(REG_MSG, val); +} + +typedef struct PI_regs_s { + /** @brief Uncached address in RAM where data should be found */ + void * ram_address; + /** @brief Address of data on peripheral */ + unsigned long pi_address; + /** @brief How much data to read from RAM into the peripheral */ + unsigned long read_length; + /** @brief How much data to write to RAM from the peripheral */ + unsigned long write_length; + /** @brief Status of the PI, including DMA busy */ + unsigned long status; +} _PI_regs_s; + +static volatile struct PI_regs_s * const PI_regs = (struct PI_regs_s *) 0xa4600000; + +void bi_dma_r(void * ram_address, unsigned long pi_address, unsigned long len) { + + + disable_interrupts(); + + while (dma_busy()); + IO_WRITE(PI_STATUS_REG, 3); + PI_regs->ram_address = ram_address; + PI_regs->pi_address = pi_address & 0x1FFFFFFF; // (pi_address | 0x10000000) & 0x1FFFFFFF; + PI_regs->write_length = len - 1; + while (dma_busy()); + + enable_interrupts(); +} + +void bi_dma_w(void * ram_address, unsigned long pi_address, unsigned long len) { + + + disable_interrupts(); + while (dma_busy()); + IO_WRITE(PI_STATUS_REG, 3); + PI_regs->ram_address = ram_address; + PI_regs->pi_address = pi_address & 0x1FFFFFFF; // (pi_address | 0x10000000) & 0x1FFFFFFF; + PI_regs->read_length = len - 1; + while (dma_busy()); + enable_interrupts(); +} + +void bi_dma_read(void *ram, uint32_t addr, uint32_t len) { + + + if (((uint32_t) ram & 0xF0000000) == 0x80000000) { + data_cache_hit_writeback_invalidate(ram, len); + bi_dma_r(ram, addr, len); + } else { + bi_dma_r(ram, addr, len); + } + +} + +void bi_dma_write(void *ram, uint32_t addr, uint32_t len) { + + if (((uint32_t) ram & 0xF0000000) == 0x80000000)data_cache_hit_writeback(ram, len); + bi_dma_w(ram, addr, len); +} + +uint16_t bi_fpga_ver() { + + return bi_reg_rd(REG_VER); +} + +void bi_load_firmware(uint8_t *firm) { + + uint32_t i; + uint16_t f_ctr = 0; + uint16_t cfg = bi_reg_rd(REG_CFG); + + cfg &= ~ED_CFG_SDRAM_ON; + bi_reg_wr(REG_CFG, cfg); + + bi_reg_wr(REG_CFG_CNT, 0); + bi_sleep(10); + bi_reg_wr(REG_CFG_CNT, 1); + bi_sleep(10); + + i = 0; + for (;;) { + + bi_reg_wr(REG_CFG_DAT, *(uint16_t *) & firm[i]); + while ((bi_reg_rd(REG_CFG_CNT) & 8) != 0); + + f_ctr = firm[i++] == 0xff ? f_ctr + 1 : 0; + if (f_ctr >= 47)break; + f_ctr = firm[i++] == 0xff ? f_ctr + 1 : 0; + if (f_ctr >= 47)break; + } + + + while ((bi_reg_rd(REG_CFG_CNT) & 4) == 0) { + bi_reg_wr(REG_CFG_DAT, 0xffff); + while ((bi_reg_rd(REG_CFG_CNT) & 8) != 0); + } + + + bi_sleep(20); +} + +void bi_sleep(uint32_t ms) { + + uint32_t current_ms = get_ticks_ms(); + + while (get_ticks_ms() - current_ms < ms); + +} + +void bi_lock_regs() { + bi_reg_wr(REG_KEY, 0); +} + +void bi_unlock_regs() { + bi_reg_wr(REG_KEY, 0x1234); +} + + +uint16_t bi_cpld_ver() { + + uint16_t ver; + uint16_t cfg = bi_reg_rd(REG_CFG); + + bi_reg_wr(REG_CFG, 0); + ver = bi_reg_rd(REG_MAX_VER); + bi_reg_wr(REG_CFG, cfg); + + return ver; +} + +void bi_gpio_mode_rtc() { + + uint16_t cfg = bi_reg_rd(REG_CFG); + cfg &= ~ED_CFG_GPIO_ON; + cfg |= ED_CFG_RTC_ON; + bi_reg_wr(REG_CFG, cfg); +} + +void bi_gpio_mode_io() { + + uint16_t cfg = bi_reg_rd(REG_CFG); + cfg |= ED_CFG_GPIO_ON; + bi_reg_wr(REG_CFG, cfg); +} + +void bi_gpio_off() { + + uint16_t cfg = bi_reg_rd(REG_CFG); + cfg &= ~ED_CFG_GPIO_ON; + bi_reg_wr(REG_CFG, cfg); +} + +void bi_gpio_wr(uint8_t data) { + + bi_reg_wr(REG_GPIO, data); +} + +uint8_t bi_gpio_rd() { + + return bi_reg_rd(REG_GPIO); +} + +void bi_set_ram_bank(uint8_t bank) { + + bi_ram_bank = bank == 0 ? 0 : 1; + +} + + + +void bi_dd_ram_oe() { + + uint16_t cfg = bi_reg_rd(REG_CFG); + cfg &= ~ED_CFG_DD_WE; + cfg |= ED_CFG_DD_ON; + bi_reg_wr(REG_CFG, cfg); +} + +void bi_dd_ram_we() { + + uint16_t cfg = bi_reg_rd(REG_CFG); + cfg |= ED_CFG_DD_ON | ED_CFG_DD_WE; + bi_reg_wr(REG_CFG, cfg); +} + +void bi_dd_ram_off() { + + uint16_t cfg = bi_reg_rd(REG_CFG); + cfg &= ~(ED_CFG_DD_ON | ED_CFG_DD_WE); + bi_reg_wr(REG_CFG, cfg); +} + +void bi_dd_ram_clr() { + + uint16_t cfg = bi_reg_rd(REG_CFG); + cfg |= ED_CFG_DD_WE; + cfg &= ~ED_CFG_DD_ON; + bi_reg_wr(REG_CFG, cfg); + bi_sleep(100); +} + +uint8_t bi_dd_ram_supported() { + + return (bi_reg_rd(REG_STATUS) >> 15) & 1; + +} \ No newline at end of file diff --git a/src/flashcart/ed64/ed64_internal.h b/src/flashcart/ed64/ed64_internal.h new file mode 100644 index 00000000..b67d6f7d --- /dev/null +++ b/src/flashcart/ed64/ed64_internal.h @@ -0,0 +1,147 @@ +/** + * @file flashcart.h + * @brief ED64 Flashcart Internal Utilities + * @ingroup flashcart + */ + +#ifndef FLASHCART_ED64_INTERNAL_H__ +#define FLASHCART_ED64_INTERNAL_H__ + + +#include +#include + +/** + * @addtogroup ed64 + * @{ + */ + +#define SAVE_TYPE_OFF 0 +#define SAVE_TYPE_SRAM 1 +#define SAVE_TYPE_SRAM128 2 +#define SAVE_TYPE_EEP4k 3 +#define SAVE_TYPE_EEP16k 4 +#define SAVE_TYPE_FLASH 5 +#define SAVE_TYPE_MPAK 8 +#define SAVE_TYPE_DD64 16 + +#define NON_CACHE_RAM 0x20000000 + +#define ROM_LEN 0x4000000 +#define ROM_ADDR 0xB0000000 +#define ROM_BUFF (ROM_LEN / 512 - 4) +#define SRAM_ADDR 0xA8000000 + +#define EVD_ERROR_FIFO_TIMEOUT 0x90 +#define EVD_ERROR_MMC_TIMEOUT 0x91 + +#define BOOT_UPD_ERR_WRONG_SIZE 0x95 +#define BOOT_UPD_ERR_HDR 0x96 +#define BOOT_UPD_ERR_CMP 0x97 +#define BOOT_UPD_ERR_CIC_DTCT 0x98 + +#define PI_BSD_DOM1_LAT_REG (PI_BASE_REG+0x14) + +/* PI dom1 pulse width (R/W): [7:0] domain 1 device R/W strobe pulse width */ +#define PI_BSD_DOM1_PWD_REG (PI_BASE_REG+0x18) + +/* PI dom1 page size (R/W): [3:0] domain 1 device page size */ +#define PI_BSD_DOM1_PGS_REG (PI_BASE_REG+0x1C) /* page size */ + +/* PI dom1 release (R/W): [1:0] domain 1 device R/W release duration */ +#define PI_BSD_DOM1_RLS_REG (PI_BASE_REG+0x20) +/* PI dom2 latency (R/W): [7:0] domain 2 device latency */ +#define PI_BSD_DOM2_LAT_REG (PI_BASE_REG+0x24) /* Domain 2 latency */ + +/* PI dom2 pulse width (R/W): [7:0] domain 2 device R/W strobe pulse width */ +#define PI_BSD_DOM2_PWD_REG (PI_BASE_REG+0x28) /* pulse width */ + +/* PI dom2 page size (R/W): [3:0] domain 2 device page size */ +#define PI_BSD_DOM2_PGS_REG (PI_BASE_REG+0x2C) /* page size */ + +/* PI dom2 release (R/W): [1:0] domain 2 device R/W release duration */ +#define PI_BSD_DOM2_RLS_REG (PI_BASE_REG+0x30) /* release duration */ + +#define PHYS_TO_K1(x) ((uint32_t)(x)|0xA0000000) /* physical to kseg1 */ +#define IO_WRITE(addr,data) (*(volatile uint32_t *)PHYS_TO_K1(addr)=(uint32_t)(data)) +#define IO_READ(addr) (*(volatile uint32_t *)PHYS_TO_K1(addr)) + +#define PI_STATUS_REG (PI_BASE_REG+0x10) +#define PI_BASE_REG 0x04600000 + +#define BI_SPI_SPD_LO 2 +#define BI_SPI_SPD_25 1 +#define BI_SPI_SPD_50 0 + +#define SPI_CFG_SPD0 1 +#define SPI_CFG_SPD1 2 +#define SPI_CFG_SS 4 +#define SPI_CFG_RD 8 +#define SPI_CFG_DAT 16 +#define SPI_CFG_1BIT 32 + +#define SPI_MODE_DAT_R1 (SPI_CFG_DAT | SPI_CFG_RD | SPI_CFG_1BIT) +#define SPI_MODE_DAT_R4 (SPI_CFG_DAT | SPI_CFG_RD) +#define SPI_MODE_DAT_W1 (SPI_CFG_DAT | SPI_CFG_1BIT) +#define SPI_MODE_DAT_W4 (SPI_CFG_DAT) + +#define SPI_MODE_CMD_R1 (SPI_CFG_RD | SPI_CFG_1BIT) +#define SPI_MODE_CMD_R4 (SPI_CFG_RD) +#define SPI_MODE_CMD_W1 (SPI_CFG_1BIT) +#define SPI_MODE_CMD_W4 (0) + +#define DD64_SAV_TBL_LEN 2048 +#define DD64_SAV_BLK_SIZ 64 + +void bi_init_boot(uint8_t *firmware); +uint8_t bi_init(); +uint8_t bi_usb_rd_busy(); +uint8_t bi_usb_rd(uint32_t saddr, uint32_t slen); +uint8_t bi_usb_wr(uint32_t saddr, uint32_t slen); + +uint8_t bi_spi(uint8_t data); +void bi_spi_nr(uint8_t data); +void bi_set_spi_spd(uint16_t speed); +void bi_ss_off(); +void bi_ss_on(); +void bi_sd_mode(uint16_t mode); +uint8_t bi_spi_read_to_rom(uint32_t saddr, uint16_t slen); +void bi_swap_on(); +void bi_swap_off(); +uint8_t bi_get_save_type(); +void bi_set_save_type(uint8_t type); +uint16_t bi_fpga_ver(); +void bi_read_bios(void *dst, uint16_t saddr, uint16_t slen); +uint16_t bi_msg_rd(); +void bi_msg_wr(uint16_t val); + + +void bi_dma_read_rom(void *ram, uint32_t saddr, uint32_t slen); +void bi_dma_write_rom(void *ram, uint32_t saddr, uint32_t slen); +void bi_dma_read_sram(void *ram, uint32_t addr, uint32_t len); +void bi_dma_write_sram(void *ram, uint32_t addr, uint32_t len); +void bi_load_firmware(uint8_t *firm); +void bi_sleep(uint32_t ms); +void bi_lock_regs(); +void bi_unlock_regs(); +void bi_init_v2(); +void bi_init_v3(); +uint16_t bi_cpld_ver(); +void bi_gpio_mode_rtc(); +void bi_gpio_mode_io(); +void bi_gpio_off(); +uint8_t bi_gpio_rd(); +uint32_t bi_reg_rd(uint32_t reg); +void bi_reg_wr(uint32_t reg, uint32_t data); +void bi_reset_spx(); + +void bi_dd_ram_oe(); +void bi_dd_ram_we(); +void bi_dd_ram_off(); +void bi_dd_ram_clr(); +uint8_t bi_dd_ram_supported(); + + +#endif + + diff --git a/src/menu/rom_database.h b/src/menu/rom_database.h index 8d3d3d54..20744c6e 100644 --- a/src/menu/rom_database.h +++ b/src/menu/rom_database.h @@ -31,7 +31,9 @@ typedef enum { DB_MEMORY_EXPANSION_NONE = 0x00, /** @brief The ROM requires 8MB of memory */ DB_MEMORY_EXPANSION_REQUIRED = 0x01, + /** @brief The ROM recommends 8MB of memory */ DB_MEMORY_EXPANSION_RECOMMENDED = 0x02, + /** @brief The ROM suggests it uses 8MB of memory */ DB_MEMORY_EXPANSION_SUGGESTED = 0x03, /** @brief The ROM is faulty when using 8MB of memory */ DB_MEMORY_EXPANSION_FAULTY = 0x04, From 1b375e0ad2405662e7d0d5f9709cc2cf4efa1faa Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Mon, 17 Jul 2023 16:41:58 +0100 Subject: [PATCH 02/64] Rename functions to use `ed64_bios` add some comments --- Makefile | 1 + src/flashcart/ed64/README.md | 8 + src/flashcart/ed64/ed64_internal.c | 375 +++++++++++++++-------------- src/flashcart/ed64/ed64_internal.h | 173 +++++++------ 4 files changed, 300 insertions(+), 257 deletions(-) create mode 100644 src/flashcart/ed64/README.md diff --git a/Makefile b/Makefile index f69a2e6b..3929e6e5 100644 --- a/Makefile +++ b/Makefile @@ -19,6 +19,7 @@ SRCS = \ boot/ipl2.S \ flashcart/flashcart.c \ flashcart/sc64/sc64_internal.c \ + flashcart/ed64/ed64_internal.c \ flashcart/sc64/sc64.c \ libs/mini.c/src/mini.c \ menu/actions.c \ diff --git a/src/flashcart/ed64/README.md b/src/flashcart/ed64/README.md new file mode 100644 index 00000000..77514735 --- /dev/null +++ b/src/flashcart/ed64/README.md @@ -0,0 +1,8 @@ +This folder allows support for the ED64 "Official" flashcart when using V series hardware. +For the moment it is unlikely to support clones. + +It is based on OS 2.12.x as used in the "Unofficial Menu". + +It requires a lot of cleansing and updating to use the latest libdragon before it will probably work based on the fact that using the latest libdragon with `libcart` seems to have a detremental effect on the ability to load ROM's. + + diff --git a/src/flashcart/ed64/ed64_internal.c b/src/flashcart/ed64/ed64_internal.c index c17db294..97b92505 100644 --- a/src/flashcart/ed64/ed64_internal.c +++ b/src/flashcart/ed64/ed64_internal.c @@ -25,6 +25,7 @@ #define REG_FL_ADDR 20 #define REG_FL_DATA 21 + #define STATE_DMA_BUSY 1 #define STATE_DMA_TOUT 2 #define STATE_USB_TXE 4 @@ -55,25 +56,25 @@ #define REGS_BASE 0xA8040000 -#define MAX_MSG_SKIP_FW_INIT (1 << 8) -#define MAX_MSG_SKIP_TV_INIT (1 << 9) -#define MAX_MSG_TV_TYPE1 (1 << 10) -#define MAX_MSG_TV_TYPE2 (1 << 11) -#define MAX_MSG_SKIP_SD_INIT (1 << 12) -#define MAX_MSG_SD_TYPE (1 << 13) +// #define MAX_MSG_SKIP_FW_INIT (1 << 8) +// #define MAX_MSG_SKIP_TV_INIT (1 << 9) +// #define MAX_MSG_TV_TYPE1 (1 << 10) +// #define MAX_MSG_TV_TYPE2 (1 << 11) +// #define MAX_MSG_SKIP_SD_INIT (1 << 12) +// #define MAX_MSG_SD_TYPE (1 << 13) #define MAX_MSG_HOT_START (1 << 14) -uint32_t bi_reg_rd(uint32_t reg); -void bi_reg_wr(uint32_t reg, uint32_t data); -void bi_dma_r(void * ram_address, unsigned long pi_address, unsigned long len); -void bi_dma_w(void * ram_address, unsigned long pi_address, unsigned long len); -void bi_dma_read(void *ram, uint32_t addr, uint32_t len); -void bi_dma_write(void *ram, uint32_t addr, uint32_t len); +uint32_t ed64_bios_reg_rd(uint32_t reg); +void ed64_bios_reg_wr(uint32_t reg, uint32_t data); +void ed64_bios_dma_r(void * ram_address, unsigned long pi_address, unsigned long len); +void ed64_bios_dma_w(void * ram_address, unsigned long pi_address, unsigned long len); +void ed64_bios_dma_read(void *ram, uint32_t addr, uint32_t len); +void ed64_bios_dma_write(void *ram, uint32_t addr, uint32_t len); static uint16_t spi_cfg; -uint8_t bi_ram_bank; -uint8_t bi_save_type; +uint8_t ed64_bios_ram_bank; +uint8_t ed64_bios_save_type; #define REG_LAT 0x04 #define REG_PWD 0x04 @@ -81,51 +82,56 @@ uint8_t bi_save_type; #define ROM_LAT 0x40 #define ROM_PWD 0x12 -void bi_io_reg_v2(uint32_t addr, uint32_t dat) { +/* register functions (dependent on flashcart version) */ + +void ed64_bios_io_reg_v2(uint32_t addr, uint32_t dat) { *(volatile uint32_t *) (ROM_ADDR); *(volatile uint32_t *) (ROM_ADDR + addr) = dat; } -void bi_io_reg_v3(uint32_t addr, uint16_t dat) { +void ed64_bios_io_reg_v3(uint32_t addr, uint16_t dat) { - bi_reg_wr(REG_FL_ADDR, addr); - bi_reg_wr(REG_FL_DATA, dat); + ed64_bios_reg_wr(REG_FL_ADDR, addr); + ed64_bios_reg_wr(REG_FL_DATA, dat); } -void bi_init_v2() { +/* initialize functions (dependent on flashcart version) */ + +void ed64_bios_init_v2() { uint8_t buff[512]; - uint16_t cfg = bi_reg_rd(REG_CFG); + uint16_t cfg = ed64_bios_reg_rd(REG_CFG); - bi_reg_wr(REG_CFG, 0); - bi_io_reg_v2(0xaa / 4 * 4, 0x00980098); - bi_dma_read_rom(buff, 0, 1); - bi_io_reg_v2(0xaa / 4 * 4, 0x00f000f0); - bi_dma_read_rom(buff, 0, 1); - bi_reg_wr(REG_CFG, cfg); + ed64_bios_reg_wr(REG_CFG, 0); + ed64_bios_io_reg_v2(0xaa / 4 * 4, 0x00980098); + ed64_bios_dma_read_rom(buff, 0, 1); + ed64_bios_io_reg_v2(0xaa / 4 * 4, 0x00f000f0); + ed64_bios_dma_read_rom(buff, 0, 1); + ed64_bios_reg_wr(REG_CFG, cfg); } -void bi_init_v3() { +void ed64_bios_init_v3() { uint8_t buff[1024]; - uint16_t cfg = bi_reg_rd(REG_CFG); + uint16_t cfg = ed64_bios_reg_rd(REG_CFG); - bi_reg_wr(REG_CFG, 0); - bi_reg_wr(REG_CFG_CNT, 161); - bi_io_reg_v3(0x55, 0x98); - bi_dma_read_rom(buff, 0, 2); - bi_io_reg_v3(0x55, 0xF0); - bi_dma_read_rom(buff, 0, 2); - bi_dma_read_rom(buff, 1024, 2); - bi_dma_read_rom(buff, 1024 + 256 - 2, 2); - bi_reg_wr(REG_CFG_CNT, 1); + ed64_bios_reg_wr(REG_CFG, 0); + ed64_bios_reg_wr(REG_CFG_CNT, 161); + ed64_bios_io_reg_v3(0x55, 0x98); + ed64_bios_dma_read_rom(buff, 0, 2); + ed64_bios_io_reg_v3(0x55, 0xF0); + ed64_bios_dma_read_rom(buff, 0, 2); + ed64_bios_dma_read_rom(buff, 1024, 2); + ed64_bios_dma_read_rom(buff, 1024 + 256 - 2, 2); + ed64_bios_reg_wr(REG_CFG_CNT, 1); - bi_reg_wr(REG_CFG, cfg); + ed64_bios_reg_wr(REG_CFG, cfg); } -uint8_t bi_init() { +/* Initialize cart */ +uint8_t ed64_bios_init() { uint16_t max_ver; uint16_t max_msg; @@ -136,52 +142,52 @@ uint8_t bi_init() { IO_WRITE(PI_BSD_DOM2_PWD_REG, REG_PWD); - bi_reg_wr(REG_KEY, 0x1234); - bi_reg_wr(REG_CFG, 0x0000); + ed64_bios_reg_wr(REG_KEY, 0x1234); + ed64_bios_reg_wr(REG_CFG, 0x0000); - max_msg = bi_reg_rd(REG_MAX_MSG); + max_msg = ed64_bios_reg_rd(REG_MAX_MSG); cold_start = (max_msg & MAX_MSG_HOT_START) == 0 ? 1 : 0; if (cold_start) { max_msg |= MAX_MSG_HOT_START; - bi_reg_wr(REG_MAX_MSG, max_msg); + ed64_bios_reg_wr(REG_MAX_MSG, max_msg); } - max_ver = bi_reg_rd(REG_MAX_VER); + max_ver = ed64_bios_reg_rd(REG_MAX_VER); if ((max_ver & 0xf000) >= 0x2000) { - bi_init_v3(); + ed64_bios_init_v3(); } else { - bi_init_v2(); + ed64_bios_init_v2(); } spi_cfg = SPI_CFG_SS | BI_SPI_SPD_LO; - bi_reg_wr(REG_CFG, ED_CFG_SDRAM_ON); - bi_reg_wr(REG_SPI_CFG, spi_cfg); - bi_save_type = 0; + ed64_bios_reg_wr(REG_CFG, ED_CFG_SDRAM_ON); + ed64_bios_reg_wr(REG_SPI_CFG, spi_cfg); + ed64_bios_save_type = 0; return cold_start; } -void bi_reset_spx() { +void ed64_bios_reset_spx() { - uint16_t cfg = bi_reg_rd(REG_CFG); + uint16_t cfg = ed64_bios_reg_rd(REG_CFG); - bi_reg_wr(REG_CFG, 0x8000); - bi_sleep(100); - bi_reg_wr(REG_CFG, cfg); - bi_sleep(100); + ed64_bios_reg_wr(REG_CFG, 0x8000); + ed64_bios_sleep(100); + ed64_bios_reg_wr(REG_CFG, cfg); + ed64_bios_sleep(100); } -uint32_t bi_reg_rd(uint32_t reg) { +uint32_t ed64_bios_reg_rd(uint32_t reg) { *(volatile uint32_t *) (REGS_BASE); return *(volatile uint32_t *) (REGS_BASE + reg * 4); } -void bi_reg_wr(uint32_t reg, uint32_t data) { +void ed64_bios_reg_wr(uint32_t reg, uint32_t data) { *(volatile uint32_t *) (REGS_BASE); *(volatile uint32_t *) (REGS_BASE + reg * 4) = data; @@ -189,122 +195,128 @@ void bi_reg_wr(uint32_t reg, uint32_t data) { } -uint8_t bi_dma_busy() { +uint8_t ed64_bios_dma_busy() { - while ((bi_reg_rd(REG_STATUS) & STATE_DMA_BUSY) != 0); - return bi_reg_rd(REG_STATUS) & STATE_DMA_TOUT; + while ((ed64_bios_reg_rd(REG_STATUS) & STATE_DMA_BUSY) != 0); + return ed64_bios_reg_rd(REG_STATUS) & STATE_DMA_TOUT; } -uint8_t bi_usb_rd_busy() { - return bi_reg_rd(REG_STATUS) & STATE_USB_RXF; +/* USB functions */ + +uint8_t ed64_bios_usb_rd_busy() { + + return ed64_bios_reg_rd(REG_STATUS) & STATE_USB_RXF; } -uint8_t bi_usb_wr_busy() { +uint8_t ed64_bios_usb_wr_busy() { - return bi_reg_rd(REG_STATUS) & STATE_USB_TXE; + return ed64_bios_reg_rd(REG_STATUS) & STATE_USB_TXE; } -uint8_t bi_usb_rd(uint32_t saddr, uint32_t slen) { +uint8_t ed64_bios_usb_rd(uint32_t saddr, uint32_t slen) { saddr /= 4; while (bi_usb_rd_busy() != 0); - bi_reg_wr(REG_DMA_LEN, slen - 1); - bi_reg_wr(REG_DMA_RAM_ADDR, saddr); - bi_reg_wr(REG_DMA_CFG, DCFG_USB_TO_RAM); + ed64_bios_reg_wr(REG_DMA_LEN, slen - 1); + ed64_bios_reg_wr(REG_DMA_RAM_ADDR, saddr); + ed64_bios_reg_wr(REG_DMA_CFG, DCFG_USB_TO_RAM); if (bi_dma_busy() != 0)return EVD_ERROR_FIFO_TIMEOUT; return 0; } -uint8_t bi_usb_wr(uint32_t saddr, uint32_t slen) { +uint8_t ed64_bios_usb_wr(uint32_t saddr, uint32_t slen) { saddr /= 4; while (bi_usb_wr_busy() != 0); - bi_reg_wr(REG_DMA_LEN, slen - 1); - bi_reg_wr(REG_DMA_RAM_ADDR, saddr); - bi_reg_wr(REG_DMA_CFG, DCFG_RAM_TO_USB); + ed64_bios_reg_wr(REG_DMA_LEN, slen - 1); + ed64_bios_reg_wr(REG_DMA_RAM_ADDR, saddr); + ed64_bios_reg_wr(REG_DMA_CFG, DCFG_RAM_TO_USB); if (bi_dma_busy() != 0)return EVD_ERROR_FIFO_TIMEOUT; return 0; } -uint16_t bi_spi_busy() { - return bi_reg_rd(REG_STATUS) & STATE_DMA_BUSY; +/* SPI functions */ + +uint16_t ed64_bios_spi_busy() { + + return ed64_bios_reg_rd(REG_STATUS) & STATE_DMA_BUSY; } -uint8_t bi_spi(uint8_t data) { +uint8_t ed64_bios_spi(uint8_t data) { - bi_reg_wr(REG_SPI, data); + ed64_bios_reg_wr(REG_SPI, data); while (bi_spi_busy()); - return bi_reg_rd(REG_SPI); + return ed64_bios_reg_rd(REG_SPI); } -void bi_spi_nr(uint8_t data) { +void ed64_bios_spi_nr(uint8_t data) { - bi_reg_wr(REG_SPI, data); + ed64_bios_reg_wr(REG_SPI, data); while (bi_spi_busy()); } -void bi_set_spi_spd(uint16_t speed) { +void ed64_bios_set_spi_spd(uint16_t speed) { spi_cfg &= ~3; spi_cfg |= speed; - bi_reg_wr(REG_SPI_CFG, spi_cfg); + ed64_bios_reg_wr(REG_SPI_CFG, spi_cfg); } -void bi_sd_mode(uint16_t mode) { +void ed64_bios_sd_mode(uint16_t mode) { spi_cfg &= ~(SPI_CFG_1BIT | SPI_CFG_RD | SPI_CFG_DAT); spi_cfg |= mode; - bi_reg_wr(REG_SPI_CFG, spi_cfg); + ed64_bios_reg_wr(REG_SPI_CFG, spi_cfg); } -uint8_t bi_spi_read_to_rom(uint32_t saddr, uint16_t slen) { +uint8_t ed64_bios_spi_read_to_rom(uint32_t saddr, uint16_t slen) { saddr /= 4; - bi_reg_wr(REG_DMA_LEN, slen - 1); - bi_reg_wr(REG_DMA_RAM_ADDR, saddr); - bi_reg_wr(REG_DMA_CFG, DCFG_SD_TO_RAM); + ed64_bios_reg_wr(REG_DMA_LEN, slen - 1); + ed64_bios_reg_wr(REG_DMA_RAM_ADDR, saddr); + ed64_bios_reg_wr(REG_DMA_CFG, DCFG_SD_TO_RAM); if (bi_dma_busy() != 0)return EVD_ERROR_MMC_TIMEOUT; return 0; } -void bi_swap_on() { - uint16_t cfg = bi_reg_rd(REG_CFG); +void ed64_bios_swap_on() { + uint16_t cfg = ed64_bios_reg_rd(REG_CFG); cfg |= ED_CFG_SWAP; - bi_reg_wr(REG_CFG, cfg); + ed64_bios_reg_wr(REG_CFG, cfg); } -void bi_swap_off() { - uint16_t cfg = bi_reg_rd(REG_CFG); +void ed64_bios_swap_off() { + uint16_t cfg = ed64_bios_reg_rd(REG_CFG); cfg &= ~ED_CFG_SWAP; - bi_reg_wr(REG_CFG, cfg); + ed64_bios_reg_wr(REG_CFG, cfg); } -uint8_t bi_get_save_type() { +uint8_t ed64_bios_get_save_type() { - return bi_save_type; + return ed64_bios_save_type; } -void bi_set_save_type(uint8_t type) { +void ed64_bios_set_save_type(uint8_t type) { uint16_t save_cfg; uint8_t eeprom_on, sram_on, eeprom_size, sram_size, ram_bank; - bi_save_type = type; + ed64_bios_save_type = type; eeprom_on = 0; sram_on = 0; eeprom_size = 0; sram_size = 0; - ram_bank = bi_ram_bank; + ram_bank = ed64_bios_ram_bank; switch (type) { @@ -341,35 +353,35 @@ void bi_set_save_type(uint8_t type) { if (ram_bank)save_cfg |= SAV_RAM_BANK; save_cfg |= SAV_RAM_BANK_APPLY; - bi_reg_wr(REG_SAV_CFG, save_cfg); + ed64_bios_reg_wr(REG_SAV_CFG, save_cfg); } -void bi_read_bios(void *dst, uint16_t saddr, uint16_t slen) { +void ed64_bios_read_bios(void *dst, uint16_t saddr, uint16_t slen) { - uint16_t cfg = bi_reg_rd(REG_CFG); + uint16_t cfg = ed64_bios_reg_rd(REG_CFG); cfg &= ~ED_CFG_SDRAM_ON; - bi_reg_wr(REG_CFG, cfg); + ed64_bios_reg_wr(REG_CFG, cfg); - bi_dma_read_rom(dst, saddr, slen); + ed64_bios_dma_read_rom(dst, saddr, slen); cfg |= ED_CFG_SDRAM_ON; - bi_reg_wr(REG_CFG, cfg); + ed64_bios_reg_wr(REG_CFG, cfg); } -void bi_dma_read_rom(void *ram, uint32_t saddr, uint32_t slen) { +void ed64_bios_dma_read_rom(void *ram, uint32_t saddr, uint32_t slen) { - bi_dma_read(ram, ROM_ADDR + saddr * 512, slen * 512); + ed64_bios_dma_read(ram, ROM_ADDR + saddr * 512, slen * 512); } -void bi_dma_write_rom(void *ram, uint32_t saddr, uint32_t slen) { +void ed64_bios_dma_write_rom(void *ram, uint32_t saddr, uint32_t slen) { - bi_dma_write(ram, ROM_ADDR + saddr * 512, slen * 512); + ed64_bios_dma_write(ram, ROM_ADDR + saddr * 512, slen * 512); } -void bi_dma_read_sram(void *ram, uint32_t addr, uint32_t len) { +void ed64_bios_dma_read_sram(void *ram, uint32_t addr, uint32_t len) { volatile uint32_t piLatReg = IO_READ(PI_BSD_DOM2_LAT_REG); volatile uint32_t piPwdReg = IO_READ(PI_BSD_DOM2_PWD_REG); @@ -381,7 +393,7 @@ void bi_dma_read_sram(void *ram, uint32_t addr, uint32_t len) { IO_WRITE(PI_BSD_DOM2_LAT_REG, 0x05); IO_WRITE(PI_BSD_DOM2_PWD_REG, 0x0C); - bi_dma_read(ram, SRAM_ADDR + addr, len); + ed64_bios_dma_read(ram, SRAM_ADDR + addr, len); IO_WRITE(PI_BSD_DOM2_LAT_REG, piLatReg); IO_WRITE(PI_BSD_DOM2_PWD_REG, piPwdReg); @@ -389,7 +401,7 @@ void bi_dma_read_sram(void *ram, uint32_t addr, uint32_t len) { IO_WRITE(PI_BSD_DOM2_RLS_REG, piRlsReg); } -void bi_dma_write_sram(void *ram, uint32_t addr, uint32_t len) { +void ed64_bios_dma_write_sram(void *ram, uint32_t addr, uint32_t len) { volatile uint32_t piLatReg = IO_READ(PI_BSD_DOM2_LAT_REG); volatile uint32_t piPwdReg = IO_READ(PI_BSD_DOM2_PWD_REG); @@ -401,7 +413,7 @@ void bi_dma_write_sram(void *ram, uint32_t addr, uint32_t len) { IO_WRITE(PI_BSD_DOM2_LAT_REG, 0x05); IO_WRITE(PI_BSD_DOM2_PWD_REG, 0x0C); - bi_dma_write(ram, SRAM_ADDR + addr, len); + ed64_bios_dma_write(ram, SRAM_ADDR + addr, len); IO_WRITE(PI_BSD_DOM2_LAT_REG, piLatReg); @@ -411,14 +423,14 @@ void bi_dma_write_sram(void *ram, uint32_t addr, uint32_t len) { } -uint16_t bi_msg_rd() { +uint16_t ed64_bios_msg_rd() { - return bi_reg_rd(REG_MSG); + return ed64_bios_reg_rd(REG_MSG); } -void bi_msg_wr(uint16_t val) { +void ed64_bios_msg_wr(uint16_t val) { - bi_reg_wr(REG_MSG, val); + ed64_bios_reg_wr(REG_MSG, val); } typedef struct PI_regs_s { @@ -436,7 +448,7 @@ typedef struct PI_regs_s { static volatile struct PI_regs_s * const PI_regs = (struct PI_regs_s *) 0xa4600000; -void bi_dma_r(void * ram_address, unsigned long pi_address, unsigned long len) { +void ed64_bios_dma_r(void * ram_address, unsigned long pi_address, unsigned long len) { disable_interrupts(); @@ -451,7 +463,7 @@ void bi_dma_r(void * ram_address, unsigned long pi_address, unsigned long len) { enable_interrupts(); } -void bi_dma_w(void * ram_address, unsigned long pi_address, unsigned long len) { +void ed64_bios_dma_w(void * ram_address, unsigned long pi_address, unsigned long len) { disable_interrupts(); @@ -464,48 +476,48 @@ void bi_dma_w(void * ram_address, unsigned long pi_address, unsigned long len) { enable_interrupts(); } -void bi_dma_read(void *ram, uint32_t addr, uint32_t len) { +void ed64_bios_dma_read(void *ram, uint32_t addr, uint32_t len) { if (((uint32_t) ram & 0xF0000000) == 0x80000000) { data_cache_hit_writeback_invalidate(ram, len); - bi_dma_r(ram, addr, len); + ed64_bios_dma_r(ram, addr, len); } else { - bi_dma_r(ram, addr, len); + ed64_bios_dma_r(ram, addr, len); } } -void bi_dma_write(void *ram, uint32_t addr, uint32_t len) { +void ed64_bios_dma_write(void *ram, uint32_t addr, uint32_t len) { if (((uint32_t) ram & 0xF0000000) == 0x80000000)data_cache_hit_writeback(ram, len); - bi_dma_w(ram, addr, len); + ed64_bios_dma_w(ram, addr, len); } -uint16_t bi_fpga_ver() { +uint16_t ed64_bios_fpga_ver() { - return bi_reg_rd(REG_VER); + return ed64_bios_reg_rd(REG_VER); } -void bi_load_firmware(uint8_t *firm) { +void ed64_bios_load_firmware(uint8_t *firm) { uint32_t i; uint16_t f_ctr = 0; - uint16_t cfg = bi_reg_rd(REG_CFG); + uint16_t cfg = ed64_bios_reg_rd(REG_CFG); cfg &= ~ED_CFG_SDRAM_ON; - bi_reg_wr(REG_CFG, cfg); + ed64_bios_reg_wr(REG_CFG, cfg); - bi_reg_wr(REG_CFG_CNT, 0); - bi_sleep(10); - bi_reg_wr(REG_CFG_CNT, 1); - bi_sleep(10); + ed64_bios_reg_wr(REG_CFG_CNT, 0); + ed64_bios_sleep(10); + ed64_bios_reg_wr(REG_CFG_CNT, 1); + ed64_bios_sleep(10); i = 0; for (;;) { - bi_reg_wr(REG_CFG_DAT, *(uint16_t *) & firm[i]); - while ((bi_reg_rd(REG_CFG_CNT) & 8) != 0); + ed64_bios_reg_wr(REG_CFG_DAT, *(uint16_t *) & firm[i]); + while ((ed64_bios_reg_rd(REG_CFG_CNT) & 8) != 0); f_ctr = firm[i++] == 0xff ? f_ctr + 1 : 0; if (f_ctr >= 47)break; @@ -514,16 +526,16 @@ void bi_load_firmware(uint8_t *firm) { } - while ((bi_reg_rd(REG_CFG_CNT) & 4) == 0) { - bi_reg_wr(REG_CFG_DAT, 0xffff); - while ((bi_reg_rd(REG_CFG_CNT) & 8) != 0); + while ((ed64_bios_reg_rd(REG_CFG_CNT) & 4) == 0) { + ed64_bios_reg_wr(REG_CFG_DAT, 0xffff); + while ((ed64_bios_reg_rd(REG_CFG_CNT) & 8) != 0); } - bi_sleep(20); + ed64_bios_sleep(20); } -void bi_sleep(uint32_t ms) { +void ed64_bios_sleep(uint32_t ms) { uint32_t current_ms = get_ticks_ms(); @@ -531,100 +543,105 @@ void bi_sleep(uint32_t ms) { } -void bi_lock_regs() { - bi_reg_wr(REG_KEY, 0); +void ed64_bios_lock_regs() { + ed64_bios_reg_wr(REG_KEY, 0); } -void bi_unlock_regs() { - bi_reg_wr(REG_KEY, 0x1234); +void ed64_bios_unlock_regs() { + ed64_bios_reg_wr(REG_KEY, 0x1234); } -uint16_t bi_cpld_ver() { +uint16_t ed64_bios_cpld_ver() { uint16_t ver; - uint16_t cfg = bi_reg_rd(REG_CFG); + uint16_t cfg = ed64_bios_reg_rd(REG_CFG); - bi_reg_wr(REG_CFG, 0); - ver = bi_reg_rd(REG_MAX_VER); - bi_reg_wr(REG_CFG, cfg); + ed64_bios_reg_wr(REG_CFG, 0); + ver = ed64_bios_reg_rd(REG_MAX_VER); + ed64_bios_reg_wr(REG_CFG, cfg); return ver; } -void bi_gpio_mode_rtc() { +/* GPIO functions */ + +void ed64_bios_gpio_mode_rtc() { - uint16_t cfg = bi_reg_rd(REG_CFG); + uint16_t cfg = ed64_bios_reg_rd(REG_CFG); cfg &= ~ED_CFG_GPIO_ON; cfg |= ED_CFG_RTC_ON; - bi_reg_wr(REG_CFG, cfg); + ed64_bios_reg_wr(REG_CFG, cfg); } -void bi_gpio_mode_io() { +void ed64_bios_gpio_mode_io() { - uint16_t cfg = bi_reg_rd(REG_CFG); + uint16_t cfg = ed64_bios_reg_rd(REG_CFG); cfg |= ED_CFG_GPIO_ON; - bi_reg_wr(REG_CFG, cfg); + ed64_bios_reg_wr(REG_CFG, cfg); } -void bi_gpio_off() { +void ed64_bios_gpio_off() { - uint16_t cfg = bi_reg_rd(REG_CFG); + uint16_t cfg = ed64_bios_reg_rd(REG_CFG); cfg &= ~ED_CFG_GPIO_ON; - bi_reg_wr(REG_CFG, cfg); + ed64_bios_reg_wr(REG_CFG, cfg); } -void bi_gpio_wr(uint8_t data) { +void ed64_bios_gpio_wr(uint8_t data) { - bi_reg_wr(REG_GPIO, data); + ed64_bios_reg_wr(REG_GPIO, data); } -uint8_t bi_gpio_rd() { +uint8_t ed64_bios_gpio_rd() { - return bi_reg_rd(REG_GPIO); + return ed64_bios_reg_rd(REG_GPIO); } -void bi_set_ram_bank(uint8_t bank) { - bi_ram_bank = bank == 0 ? 0 : 1; + +void ed64_bios_set_ram_bank(uint8_t bank) { + + ed64_bios_ram_bank = bank == 0 ? 0 : 1; } +/* 64DD functions */ -void bi_dd_ram_oe() { +void ed64_bios_dd_ram_oe() { - uint16_t cfg = bi_reg_rd(REG_CFG); + uint16_t cfg = ed64_bios_reg_rd(REG_CFG); cfg &= ~ED_CFG_DD_WE; cfg |= ED_CFG_DD_ON; - bi_reg_wr(REG_CFG, cfg); + ed64_bios_reg_wr(REG_CFG, cfg); } -void bi_dd_ram_we() { +void ed64_bios_dd_ram_we() { - uint16_t cfg = bi_reg_rd(REG_CFG); + uint16_t cfg = ed64_bios_reg_rd(REG_CFG); cfg |= ED_CFG_DD_ON | ED_CFG_DD_WE; - bi_reg_wr(REG_CFG, cfg); + ed64_bios_reg_wr(REG_CFG, cfg); } -void bi_dd_ram_off() { +void ed64_bios_dd_ram_off() { - uint16_t cfg = bi_reg_rd(REG_CFG); + uint16_t cfg = ed64_bios_reg_rd(REG_CFG); cfg &= ~(ED_CFG_DD_ON | ED_CFG_DD_WE); - bi_reg_wr(REG_CFG, cfg); + ed64_bios_reg_wr(REG_CFG, cfg); } -void bi_dd_ram_clr() { +void ed64_bios_dd_ram_clr() { - uint16_t cfg = bi_reg_rd(REG_CFG); + uint16_t cfg = ed64_bios_reg_rd(REG_CFG); cfg |= ED_CFG_DD_WE; cfg &= ~ED_CFG_DD_ON; - bi_reg_wr(REG_CFG, cfg); - bi_sleep(100); + ed64_bios_reg_wr(REG_CFG, cfg); + ed64_bios_sleep(100); } -uint8_t bi_dd_ram_supported() { +uint8_t ed64_bios_dd_ram_supported() { - return (bi_reg_rd(REG_STATUS) >> 15) & 1; + return (ed64_bios_reg_rd(REG_STATUS) >> 15) & 1; -} \ No newline at end of file +} diff --git a/src/flashcart/ed64/ed64_internal.h b/src/flashcart/ed64/ed64_internal.h index b67d6f7d..10685342 100644 --- a/src/flashcart/ed64/ed64_internal.h +++ b/src/flashcart/ed64/ed64_internal.h @@ -16,18 +16,21 @@ * @{ */ -#define SAVE_TYPE_OFF 0 -#define SAVE_TYPE_SRAM 1 -#define SAVE_TYPE_SRAM128 2 -#define SAVE_TYPE_EEP4k 3 -#define SAVE_TYPE_EEP16k 4 -#define SAVE_TYPE_FLASH 5 -#define SAVE_TYPE_MPAK 8 -#define SAVE_TYPE_DD64 16 - -#define NON_CACHE_RAM 0x20000000 - -#define ROM_LEN 0x4000000 + +typedef enum { + SAVE_TYPE_OFF = 0, + SAVE_TYPE_SRAM = 1, + SAVE_TYPE_SRAM128 = 2, + SAVE_TYPE_EEP4k = 3, + SAVE_TYPE_EEP16k = 4, + SAVE_TYPE_FLASH = 5, + SAVE_TYPE_CPAK = 8, + SAVE_TYPE_DD64 = 16, +} ed64_save_type_t; + +// #define NON_CACHE_RAM 0x20000000 + +#define ROM_LEN 0x4000000 #define ROM_ADDR 0xB0000000 #define ROM_BUFF (ROM_LEN / 512 - 4) #define SRAM_ADDR 0xA8000000 @@ -40,6 +43,9 @@ #define BOOT_UPD_ERR_CMP 0x97 #define BOOT_UPD_ERR_CIC_DTCT 0x98 + +#define PI_BASE_REG 0x04600000 +#define PI_STATUS_REG (PI_BASE_REG+0x10) #define PI_BSD_DOM1_LAT_REG (PI_BASE_REG+0x14) /* PI dom1 pulse width (R/W): [7:0] domain 1 device R/W strobe pulse width */ @@ -50,6 +56,7 @@ /* PI dom1 release (R/W): [1:0] domain 1 device R/W release duration */ #define PI_BSD_DOM1_RLS_REG (PI_BASE_REG+0x20) + /* PI dom2 latency (R/W): [7:0] domain 2 device latency */ #define PI_BSD_DOM2_LAT_REG (PI_BASE_REG+0x24) /* Domain 2 latency */ @@ -66,12 +73,11 @@ #define IO_WRITE(addr,data) (*(volatile uint32_t *)PHYS_TO_K1(addr)=(uint32_t)(data)) #define IO_READ(addr) (*(volatile uint32_t *)PHYS_TO_K1(addr)) -#define PI_STATUS_REG (PI_BASE_REG+0x10) -#define PI_BASE_REG 0x04600000 - -#define BI_SPI_SPD_LO 2 -#define BI_SPI_SPD_25 1 -#define BI_SPI_SPD_50 0 +typedef enum { + BI_SPI_SPD_50 = 0, + BI_SPI_SPD_25 = 1, + BI_SPI_SPD_LO = 2, +} ed64_spi_speed_t; #define SPI_CFG_SPD0 1 #define SPI_CFG_SPD1 2 @@ -80,67 +86,78 @@ #define SPI_CFG_DAT 16 #define SPI_CFG_1BIT 32 -#define SPI_MODE_DAT_R1 (SPI_CFG_DAT | SPI_CFG_RD | SPI_CFG_1BIT) -#define SPI_MODE_DAT_R4 (SPI_CFG_DAT | SPI_CFG_RD) -#define SPI_MODE_DAT_W1 (SPI_CFG_DAT | SPI_CFG_1BIT) -#define SPI_MODE_DAT_W4 (SPI_CFG_DAT) - -#define SPI_MODE_CMD_R1 (SPI_CFG_RD | SPI_CFG_1BIT) -#define SPI_MODE_CMD_R4 (SPI_CFG_RD) -#define SPI_MODE_CMD_W1 (SPI_CFG_1BIT) -#define SPI_MODE_CMD_W4 (0) - -#define DD64_SAV_TBL_LEN 2048 -#define DD64_SAV_BLK_SIZ 64 - -void bi_init_boot(uint8_t *firmware); -uint8_t bi_init(); -uint8_t bi_usb_rd_busy(); -uint8_t bi_usb_rd(uint32_t saddr, uint32_t slen); -uint8_t bi_usb_wr(uint32_t saddr, uint32_t slen); - -uint8_t bi_spi(uint8_t data); -void bi_spi_nr(uint8_t data); -void bi_set_spi_spd(uint16_t speed); -void bi_ss_off(); -void bi_ss_on(); -void bi_sd_mode(uint16_t mode); -uint8_t bi_spi_read_to_rom(uint32_t saddr, uint16_t slen); -void bi_swap_on(); -void bi_swap_off(); -uint8_t bi_get_save_type(); -void bi_set_save_type(uint8_t type); -uint16_t bi_fpga_ver(); -void bi_read_bios(void *dst, uint16_t saddr, uint16_t slen); -uint16_t bi_msg_rd(); -void bi_msg_wr(uint16_t val); - - -void bi_dma_read_rom(void *ram, uint32_t saddr, uint32_t slen); -void bi_dma_write_rom(void *ram, uint32_t saddr, uint32_t slen); -void bi_dma_read_sram(void *ram, uint32_t addr, uint32_t len); -void bi_dma_write_sram(void *ram, uint32_t addr, uint32_t len); -void bi_load_firmware(uint8_t *firm); -void bi_sleep(uint32_t ms); -void bi_lock_regs(); -void bi_unlock_regs(); -void bi_init_v2(); -void bi_init_v3(); -uint16_t bi_cpld_ver(); -void bi_gpio_mode_rtc(); -void bi_gpio_mode_io(); -void bi_gpio_off(); -uint8_t bi_gpio_rd(); -uint32_t bi_reg_rd(uint32_t reg); -void bi_reg_wr(uint32_t reg, uint32_t data); -void bi_reset_spx(); - -void bi_dd_ram_oe(); -void bi_dd_ram_we(); -void bi_dd_ram_off(); -void bi_dd_ram_clr(); -uint8_t bi_dd_ram_supported(); +// #define SPI_MODE_DAT_R1 (SPI_CFG_DAT | SPI_CFG_RD | SPI_CFG_1BIT) +// #define SPI_MODE_DAT_R4 (SPI_CFG_DAT | SPI_CFG_RD) +// #define SPI_MODE_DAT_W1 (SPI_CFG_DAT | SPI_CFG_1BIT) +// #define SPI_MODE_DAT_W4 (SPI_CFG_DAT) + +// #define SPI_MODE_CMD_R1 (SPI_CFG_RD | SPI_CFG_1BIT) +// #define SPI_MODE_CMD_R4 (SPI_CFG_RD) +// #define SPI_MODE_CMD_W1 (SPI_CFG_1BIT) +// #define SPI_MODE_CMD_W4 (0) + +// #define DD64_SAV_TBL_LEN 2048 +// #define DD64_SAV_BLK_SIZ 64 + + +void ed64_bios_init_boot(uint8_t *firmware); +uint8_t ed64_bios_init(); +uint8_t ed64_bios_usb_rd_busy(); +uint8_t ed64_bios_usb_rd(uint32_t saddr, uint32_t slen); +uint8_t ed64_bios_usb_wr(uint32_t saddr, uint32_t slen); + +uint8_t ed64_bios_spi(uint8_t data); +void ed64_bios_spi_nr(uint8_t data); +void ed64_bios_set_spi_spd(uint16_t speed); + +// void ed64_bios_ss_off(); +// void ed64_bios_ss_on(); + +void ed64_bios_sd_mode(uint16_t mode); +uint8_t ed64_bios_spi_read_to_rom(uint32_t saddr, uint16_t slen); +void ed64_bios_swap_on(); +void ed64_bios_swap_off(); + +uint8_t ed64_bios_get_save_type(); +void ed64_bios_set_save_type(uint8_t type); +uint16_t ed64_bios_fpga_ver(); +void ed64_bios_read_bios(void *dst, uint16_t saddr, uint16_t slen); +uint16_t ed64_bios_msg_rd(); +void ed64_bios_msg_wr(uint16_t val); + + +void ed64_bios_dma_read_rom(void *ram, uint32_t saddr, uint32_t slen); +void ed64_bios_dma_write_rom(void *ram, uint32_t saddr, uint32_t slen); +void ed64_bios_dma_read_sram(void *ram, uint32_t addr, uint32_t len); +void ed64_bios_dma_write_sram(void *ram, uint32_t addr, uint32_t len); + + + +void ed64_bios_sleep(uint32_t ms); +void ed64_bios_lock_regs(); +void ed64_bios_unlock_regs(); + +void ed64_bios_init_v2(); +void ed64_bios_init_v3(); +uint16_t ed64_bios_cpld_ver(); +void ed64_bios_load_firmware(uint8_t *firm); + +void ed64_bios_gpio_mode_rtc(); +void ed64_bios_gpio_mode_io(); +void ed64_bios_gpio_off(); +uint8_t ed64_bios_gpio_rd(); + +uint32_t ed64_bios_reg_rd(uint32_t reg); +void ed64_bios_reg_wr(uint32_t reg, uint32_t data); +void ed64_bios_reset_spx(); + +void ed64_bios_dd_ram_oe(); +void ed64_bios_dd_ram_we(); +void ed64_bios_dd_ram_off(); +void ed64_bios_dd_ram_clr(); +uint8_t ed64_bios_dd_ram_supported(); +/** @} */ /* ed64 */ #endif From 42441fc382bd34dbb7b5e1c9e9502ffe7e39098f Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Mon, 17 Jul 2023 17:45:30 +0100 Subject: [PATCH 03/64] Improve comments Re-align header functions Comment out un-used code --- src/flashcart/ed64/README.md | 3 ++ src/flashcart/ed64/ed64_internal.c | 6 ++-- src/flashcart/ed64/ed64_internal.h | 53 +++++++++++------------------- 3 files changed, 26 insertions(+), 36 deletions(-) diff --git a/src/flashcart/ed64/README.md b/src/flashcart/ed64/README.md index 77514735..7967487b 100644 --- a/src/flashcart/ed64/README.md +++ b/src/flashcart/ed64/README.md @@ -6,3 +6,6 @@ It is based on OS 2.12.x as used in the "Unofficial Menu". It requires a lot of cleansing and updating to use the latest libdragon before it will probably work based on the fact that using the latest libdragon with `libcart` seems to have a detremental effect on the ability to load ROM's. +Initially, this aims to work when loading the ED64 menu, selecting the N64FlashcartMenu and then loading a ROM from there. This works around needing to load the correct firmware. To automate this, it is possible to set the menu to autoload (at least in the unofficial menu). + + diff --git a/src/flashcart/ed64/ed64_internal.c b/src/flashcart/ed64/ed64_internal.c index 97b92505..963034f8 100644 --- a/src/flashcart/ed64/ed64_internal.c +++ b/src/flashcart/ed64/ed64_internal.c @@ -64,7 +64,7 @@ // #define MAX_MSG_SD_TYPE (1 << 13) #define MAX_MSG_HOT_START (1 << 14) - +void ed64_bios_sleep(uint32_t ms); uint32_t ed64_bios_reg_rd(uint32_t reg); void ed64_bios_reg_wr(uint32_t reg, uint32_t data); void ed64_bios_dma_r(void * ram_address, unsigned long pi_address, unsigned long len); @@ -494,7 +494,7 @@ void ed64_bios_dma_write(void *ram, uint32_t addr, uint32_t len) { ed64_bios_dma_w(ram, addr, len); } -uint16_t ed64_bios_fpga_ver() { +uint16_t ed64_bios_get_fpga_ver() { return ed64_bios_reg_rd(REG_VER); } @@ -552,7 +552,7 @@ void ed64_bios_unlock_regs() { } -uint16_t ed64_bios_cpld_ver() { +uint16_t ed64_bios_get_cpld_ver() { uint16_t ver; uint16_t cfg = ed64_bios_reg_rd(REG_CFG); diff --git a/src/flashcart/ed64/ed64_internal.h b/src/flashcart/ed64/ed64_internal.h index 10685342..55d7cd71 100644 --- a/src/flashcart/ed64/ed64_internal.h +++ b/src/flashcart/ed64/ed64_internal.h @@ -1,6 +1,6 @@ /** * @file flashcart.h - * @brief ED64 Flashcart Internal Utilities + * @brief ED64 V-Series Flashcart Internal Utilities * @ingroup flashcart */ @@ -28,11 +28,7 @@ typedef enum { SAVE_TYPE_DD64 = 16, } ed64_save_type_t; -// #define NON_CACHE_RAM 0x20000000 - -#define ROM_LEN 0x4000000 #define ROM_ADDR 0xB0000000 -#define ROM_BUFF (ROM_LEN / 512 - 4) #define SRAM_ADDR 0xA8000000 #define EVD_ERROR_FIFO_TIMEOUT 0x90 @@ -86,41 +82,38 @@ typedef enum { #define SPI_CFG_DAT 16 #define SPI_CFG_1BIT 32 -// #define SPI_MODE_DAT_R1 (SPI_CFG_DAT | SPI_CFG_RD | SPI_CFG_1BIT) -// #define SPI_MODE_DAT_R4 (SPI_CFG_DAT | SPI_CFG_RD) -// #define SPI_MODE_DAT_W1 (SPI_CFG_DAT | SPI_CFG_1BIT) -// #define SPI_MODE_DAT_W4 (SPI_CFG_DAT) - -// #define SPI_MODE_CMD_R1 (SPI_CFG_RD | SPI_CFG_1BIT) -// #define SPI_MODE_CMD_R4 (SPI_CFG_RD) -// #define SPI_MODE_CMD_W1 (SPI_CFG_1BIT) -// #define SPI_MODE_CMD_W4 (0) +/* Initialization functions */ +uint8_t ed64_bios_init(); +void ed64_bios_init_v2(); +void ed64_bios_init_v3(); -// #define DD64_SAV_TBL_LEN 2048 -// #define DD64_SAV_BLK_SIZ 64 +/* Device information functions */ +uint16_t ed64_bios_get_fpga_ver(); +uint16_t ed64_bios_get_cpld_ver(); +/* Firmware update functions */ +void ed64_bios_load_firmware(uint8_t *firm); -void ed64_bios_init_boot(uint8_t *firmware); -uint8_t ed64_bios_init(); +/* USB functions */ uint8_t ed64_bios_usb_rd_busy(); uint8_t ed64_bios_usb_rd(uint32_t saddr, uint32_t slen); uint8_t ed64_bios_usb_wr(uint32_t saddr, uint32_t slen); +/* SPI functions */ uint8_t ed64_bios_spi(uint8_t data); void ed64_bios_spi_nr(uint8_t data); void ed64_bios_set_spi_spd(uint16_t speed); -// void ed64_bios_ss_off(); -// void ed64_bios_ss_on(); - +/* SD Card functions */ void ed64_bios_sd_mode(uint16_t mode); uint8_t ed64_bios_spi_read_to_rom(uint32_t saddr, uint16_t slen); void ed64_bios_swap_on(); void ed64_bios_swap_off(); +/* Save functions */ uint8_t ed64_bios_get_save_type(); void ed64_bios_set_save_type(uint8_t type); -uint16_t ed64_bios_fpga_ver(); + void ed64_bios_read_bios(void *dst, uint16_t saddr, uint16_t slen); uint16_t ed64_bios_msg_rd(); void ed64_bios_msg_wr(uint16_t val); @@ -131,26 +124,20 @@ void ed64_bios_dma_write_rom(void *ram, uint32_t saddr, uint32_t slen); void ed64_bios_dma_read_sram(void *ram, uint32_t addr, uint32_t len); void ed64_bios_dma_write_sram(void *ram, uint32_t addr, uint32_t len); - - -void ed64_bios_sleep(uint32_t ms); void ed64_bios_lock_regs(); void ed64_bios_unlock_regs(); -void ed64_bios_init_v2(); -void ed64_bios_init_v3(); -uint16_t ed64_bios_cpld_ver(); -void ed64_bios_load_firmware(uint8_t *firm); +uint32_t ed64_bios_reg_rd(uint32_t reg); +void ed64_bios_reg_wr(uint32_t reg, uint32_t data); +void ed64_bios_reset_spx(); +/* GPIO functions */ void ed64_bios_gpio_mode_rtc(); void ed64_bios_gpio_mode_io(); void ed64_bios_gpio_off(); uint8_t ed64_bios_gpio_rd(); -uint32_t ed64_bios_reg_rd(uint32_t reg); -void ed64_bios_reg_wr(uint32_t reg, uint32_t data); -void ed64_bios_reset_spx(); - +/* 64DD functions */ void ed64_bios_dd_ram_oe(); void ed64_bios_dd_ram_we(); void ed64_bios_dd_ram_off(); From 4f5433e0cb042601bf5833cc2765835a8a866959 Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Mon, 17 Jul 2023 17:56:04 +0100 Subject: [PATCH 04/64] Switch to libdragon `wait_ms` --- src/flashcart/ed64/ed64_internal.c | 28 ++++++++++------------------ src/flashcart/ed64/ed64_internal.h | 2 +- 2 files changed, 11 insertions(+), 19 deletions(-) diff --git a/src/flashcart/ed64/ed64_internal.c b/src/flashcart/ed64/ed64_internal.c index 963034f8..f408a919 100644 --- a/src/flashcart/ed64/ed64_internal.c +++ b/src/flashcart/ed64/ed64_internal.c @@ -64,7 +64,6 @@ // #define MAX_MSG_SD_TYPE (1 << 13) #define MAX_MSG_HOT_START (1 << 14) -void ed64_bios_sleep(uint32_t ms); uint32_t ed64_bios_reg_rd(uint32_t reg); void ed64_bios_reg_wr(uint32_t reg, uint32_t data); void ed64_bios_dma_r(void * ram_address, unsigned long pi_address, unsigned long len); @@ -176,9 +175,9 @@ void ed64_bios_reset_spx() { uint16_t cfg = ed64_bios_reg_rd(REG_CFG); ed64_bios_reg_wr(REG_CFG, 0x8000); - ed64_bios_sleep(100); + wait_ms(100); ed64_bios_reg_wr(REG_CFG, cfg); - ed64_bios_sleep(100); + wait_ms(100); } uint32_t ed64_bios_reg_rd(uint32_t reg) { @@ -499,7 +498,7 @@ uint16_t ed64_bios_get_fpga_ver() { return ed64_bios_reg_rd(REG_VER); } -void ed64_bios_load_firmware(uint8_t *firm) { +void ed64_bios_load_firmware(uint8_t *firmware) { uint32_t i; uint16_t f_ctr = 0; @@ -509,19 +508,19 @@ void ed64_bios_load_firmware(uint8_t *firm) { ed64_bios_reg_wr(REG_CFG, cfg); ed64_bios_reg_wr(REG_CFG_CNT, 0); - ed64_bios_sleep(10); + wait_ms(10); ed64_bios_reg_wr(REG_CFG_CNT, 1); - ed64_bios_sleep(10); + wait_ms(10); i = 0; for (;;) { - ed64_bios_reg_wr(REG_CFG_DAT, *(uint16_t *) & firm[i]); + ed64_bios_reg_wr(REG_CFG_DAT, *(uint16_t *) & firmware[i]); while ((ed64_bios_reg_rd(REG_CFG_CNT) & 8) != 0); - f_ctr = firm[i++] == 0xff ? f_ctr + 1 : 0; + f_ctr = firmware[i++] == 0xff ? f_ctr + 1 : 0; if (f_ctr >= 47)break; - f_ctr = firm[i++] == 0xff ? f_ctr + 1 : 0; + f_ctr = firmware[i++] == 0xff ? f_ctr + 1 : 0; if (f_ctr >= 47)break; } @@ -532,16 +531,9 @@ void ed64_bios_load_firmware(uint8_t *firm) { } - ed64_bios_sleep(20); + wait_ms(20); } -void ed64_bios_sleep(uint32_t ms) { - - uint32_t current_ms = get_ticks_ms(); - - while (get_ticks_ms() - current_ms < ms); - -} void ed64_bios_lock_regs() { ed64_bios_reg_wr(REG_KEY, 0); @@ -637,7 +629,7 @@ void ed64_bios_dd_ram_clr() { cfg |= ED_CFG_DD_WE; cfg &= ~ED_CFG_DD_ON; ed64_bios_reg_wr(REG_CFG, cfg); - ed64_bios_sleep(100); + wait_ms(100); } uint8_t ed64_bios_dd_ram_supported() { diff --git a/src/flashcart/ed64/ed64_internal.h b/src/flashcart/ed64/ed64_internal.h index 55d7cd71..199bd7bd 100644 --- a/src/flashcart/ed64/ed64_internal.h +++ b/src/flashcart/ed64/ed64_internal.h @@ -92,7 +92,7 @@ uint16_t ed64_bios_get_fpga_ver(); uint16_t ed64_bios_get_cpld_ver(); /* Firmware update functions */ -void ed64_bios_load_firmware(uint8_t *firm); +void ed64_bios_load_firmware(uint8_t *firmware); /* USB functions */ uint8_t ed64_bios_usb_rd_busy(); From cec3b0fbe85da77c56ec3d2f94ee363b3079b55e Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Mon, 17 Jul 2023 18:12:07 +0100 Subject: [PATCH 05/64] Minor comment improvements --- src/flashcart/ed64/README.md | 2 +- src/flashcart/ed64/ed64_internal.c | 4 ++-- src/flashcart/ed64/ed64_internal.h | 14 +++++++------- 3 files changed, 10 insertions(+), 10 deletions(-) diff --git a/src/flashcart/ed64/README.md b/src/flashcart/ed64/README.md index 7967487b..c3bcefce 100644 --- a/src/flashcart/ed64/README.md +++ b/src/flashcart/ed64/README.md @@ -3,7 +3,7 @@ For the moment it is unlikely to support clones. It is based on OS 2.12.x as used in the "Unofficial Menu". -It requires a lot of cleansing and updating to use the latest libdragon before it will probably work based on the fact that using the latest libdragon with `libcart` seems to have a detremental effect on the ability to load ROM's. +It may require further cleansing and updating to use the latest libdragon before it will probably work based on the fact that using the latest libdragon with `libcart` seems to have a detremental effect on the ability to load ROM's. Initially, this aims to work when loading the ED64 menu, selecting the N64FlashcartMenu and then loading a ROM from there. This works around needing to load the correct firmware. To automate this, it is possible to set the menu to autoload (at least in the unofficial menu). diff --git a/src/flashcart/ed64/ed64_internal.c b/src/flashcart/ed64/ed64_internal.c index f408a919..325ea525 100644 --- a/src/flashcart/ed64/ed64_internal.c +++ b/src/flashcart/ed64/ed64_internal.c @@ -222,7 +222,7 @@ uint8_t ed64_bios_usb_rd(uint32_t saddr, uint32_t slen) { ed64_bios_reg_wr(REG_DMA_RAM_ADDR, saddr); ed64_bios_reg_wr(REG_DMA_CFG, DCFG_USB_TO_RAM); - if (bi_dma_busy() != 0)return EVD_ERROR_FIFO_TIMEOUT; + if (bi_dma_busy() != 0)return USB_ERROR_FIFO_TIMEOUT; return 0; } @@ -236,7 +236,7 @@ uint8_t ed64_bios_usb_wr(uint32_t saddr, uint32_t slen) { ed64_bios_reg_wr(REG_DMA_RAM_ADDR, saddr); ed64_bios_reg_wr(REG_DMA_CFG, DCFG_RAM_TO_USB); - if (bi_dma_busy() != 0)return EVD_ERROR_FIFO_TIMEOUT; + if (bi_dma_busy() != 0)return USB_ERROR_FIFO_TIMEOUT; return 0; } diff --git a/src/flashcart/ed64/ed64_internal.h b/src/flashcart/ed64/ed64_internal.h index 199bd7bd..87ae3f80 100644 --- a/src/flashcart/ed64/ed64_internal.h +++ b/src/flashcart/ed64/ed64_internal.h @@ -31,13 +31,13 @@ typedef enum { #define ROM_ADDR 0xB0000000 #define SRAM_ADDR 0xA8000000 -#define EVD_ERROR_FIFO_TIMEOUT 0x90 +#define USB_ERROR_FIFO_TIMEOUT 0x90 #define EVD_ERROR_MMC_TIMEOUT 0x91 -#define BOOT_UPD_ERR_WRONG_SIZE 0x95 -#define BOOT_UPD_ERR_HDR 0x96 -#define BOOT_UPD_ERR_CMP 0x97 -#define BOOT_UPD_ERR_CIC_DTCT 0x98 +// #define BOOT_UPD_ERR_WRONG_SIZE 0x95 +// #define BOOT_UPD_ERR_HDR 0x96 +// #define BOOT_UPD_ERR_CMP 0x97 +// #define BOOT_UPD_ERR_CIC_DTCT 0x98 #define PI_BASE_REG 0x04600000 @@ -75,8 +75,8 @@ typedef enum { BI_SPI_SPD_LO = 2, } ed64_spi_speed_t; -#define SPI_CFG_SPD0 1 -#define SPI_CFG_SPD1 2 +// #define SPI_CFG_SPD0 1 +// #define SPI_CFG_SPD1 2 #define SPI_CFG_SS 4 #define SPI_CFG_RD 8 #define SPI_CFG_DAT 16 From a3720db0d74c40b77bc1b25a9c2f5c52c98611f9 Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Mon, 17 Jul 2023 18:25:59 +0100 Subject: [PATCH 06/64] Correct some function names --- src/flashcart/ed64/ed64_internal.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/src/flashcart/ed64/ed64_internal.c b/src/flashcart/ed64/ed64_internal.c index 325ea525..d21d3d0a 100644 --- a/src/flashcart/ed64/ed64_internal.c +++ b/src/flashcart/ed64/ed64_internal.c @@ -216,13 +216,13 @@ uint8_t ed64_bios_usb_wr_busy() { uint8_t ed64_bios_usb_rd(uint32_t saddr, uint32_t slen) { saddr /= 4; - while (bi_usb_rd_busy() != 0); + while (ed64_bios_usb_rd_busy() != 0); ed64_bios_reg_wr(REG_DMA_LEN, slen - 1); ed64_bios_reg_wr(REG_DMA_RAM_ADDR, saddr); ed64_bios_reg_wr(REG_DMA_CFG, DCFG_USB_TO_RAM); - if (bi_dma_busy() != 0)return USB_ERROR_FIFO_TIMEOUT; + if (ed64_bios_dma_busy() != 0)return USB_ERROR_FIFO_TIMEOUT; return 0; } @@ -230,13 +230,13 @@ uint8_t ed64_bios_usb_rd(uint32_t saddr, uint32_t slen) { uint8_t ed64_bios_usb_wr(uint32_t saddr, uint32_t slen) { saddr /= 4; - while (bi_usb_wr_busy() != 0); + while (ed64_bios_usb_wr_busy() != 0); ed64_bios_reg_wr(REG_DMA_LEN, slen - 1); ed64_bios_reg_wr(REG_DMA_RAM_ADDR, saddr); ed64_bios_reg_wr(REG_DMA_CFG, DCFG_RAM_TO_USB); - if (bi_dma_busy() != 0)return USB_ERROR_FIFO_TIMEOUT; + if (ed64_bios_dma_busy() != 0)return USB_ERROR_FIFO_TIMEOUT; return 0; } @@ -252,14 +252,14 @@ uint16_t ed64_bios_spi_busy() { uint8_t ed64_bios_spi(uint8_t data) { ed64_bios_reg_wr(REG_SPI, data); - while (bi_spi_busy()); + while (ed64_bios_spi_busy()); return ed64_bios_reg_rd(REG_SPI); } void ed64_bios_spi_nr(uint8_t data) { ed64_bios_reg_wr(REG_SPI, data); - while (bi_spi_busy()); + while (ed64_bios_spi_busy()); } void ed64_bios_set_spi_spd(uint16_t speed) { @@ -284,7 +284,7 @@ uint8_t ed64_bios_spi_read_to_rom(uint32_t saddr, uint16_t slen) { ed64_bios_reg_wr(REG_DMA_RAM_ADDR, saddr); ed64_bios_reg_wr(REG_DMA_CFG, DCFG_SD_TO_RAM); - if (bi_dma_busy() != 0)return EVD_ERROR_MMC_TIMEOUT; + if (ed64_bios_dma_busy() != 0)return EVD_ERROR_MMC_TIMEOUT; return 0; } @@ -455,7 +455,7 @@ void ed64_bios_dma_r(void * ram_address, unsigned long pi_address, unsigned long while (dma_busy()); IO_WRITE(PI_STATUS_REG, 3); PI_regs->ram_address = ram_address; - PI_regs->pi_address = pi_address & 0x1FFFFFFF; // (pi_address | 0x10000000) & 0x1FFFFFFF; + PI_regs->pi_address = pi_address & 0x1FFFFFFF; PI_regs->write_length = len - 1; while (dma_busy()); @@ -469,7 +469,7 @@ void ed64_bios_dma_w(void * ram_address, unsigned long pi_address, unsigned long while (dma_busy()); IO_WRITE(PI_STATUS_REG, 3); PI_regs->ram_address = ram_address; - PI_regs->pi_address = pi_address & 0x1FFFFFFF; // (pi_address | 0x10000000) & 0x1FFFFFFF; + PI_regs->pi_address = pi_address & 0x1FFFFFFF; PI_regs->read_length = len - 1; while (dma_busy()); enable_interrupts(); From ff1411feb6943be6c19a9623c5ccc1e3f84a5eef Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Mon, 17 Jul 2023 18:33:35 +0100 Subject: [PATCH 07/64] Switch to `dma_wait` --- src/flashcart/ed64/ed64_internal.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/flashcart/ed64/ed64_internal.c b/src/flashcart/ed64/ed64_internal.c index d21d3d0a..9f7a2ad8 100644 --- a/src/flashcart/ed64/ed64_internal.c +++ b/src/flashcart/ed64/ed64_internal.c @@ -452,12 +452,12 @@ void ed64_bios_dma_r(void * ram_address, unsigned long pi_address, unsigned long disable_interrupts(); - while (dma_busy()); + dma_wait(); IO_WRITE(PI_STATUS_REG, 3); PI_regs->ram_address = ram_address; PI_regs->pi_address = pi_address & 0x1FFFFFFF; PI_regs->write_length = len - 1; - while (dma_busy()); + dma_wait(); enable_interrupts(); } @@ -466,12 +466,12 @@ void ed64_bios_dma_w(void * ram_address, unsigned long pi_address, unsigned long disable_interrupts(); - while (dma_busy()); + dma_wait(); IO_WRITE(PI_STATUS_REG, 3); PI_regs->ram_address = ram_address; PI_regs->pi_address = pi_address & 0x1FFFFFFF; PI_regs->read_length = len - 1; - while (dma_busy()); + dma_wait(); enable_interrupts(); } From a0b9ec789e1fb8d6efbf2f3098add8a8601970c0 Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Mon, 17 Jul 2023 19:26:48 +0100 Subject: [PATCH 08/64] Improve function names Make Unlock key a constant. --- assets/FiraMono-Bold.font64 | Bin 0 -> 5644 bytes src/flashcart/ed64/ed64_internal.c | 184 ++++++++++++++--------------- src/flashcart/ed64/ed64_internal.h | 14 +-- 3 files changed, 99 insertions(+), 99 deletions(-) create mode 100644 assets/FiraMono-Bold.font64 diff --git a/assets/FiraMono-Bold.font64 b/assets/FiraMono-Bold.font64 new file mode 100644 index 0000000000000000000000000000000000000000..862bdfed98f04d7d1d034d8386e1a9c9c5962c10 GIT binary patch literal 5644 zcmbu-_ahVzz<}{0B&0Gb#TD6w%8omfO~w%+Ga*Ixyt}WFm7JM%x$N!i8E0Q8D{{$* za~zkm4>#ZU{Ttrrr_UeoJbA2r|IFDl|C<2q%ozvOOGlACJv&Wlk_`IsvZ1nJSChw? zoA8^4{nBBNx?GPgo#FY<^IbeR2%LJ^kiDG8eEUBRZ)0%qAG_Moz)7o%#j(Fu7aXnf z7Hn8Mt{1ts%i$D_auYgDbp`H$w|{qaDI4CQGw4j}W}|8T+o89f?)EvjPbWkl`xOVw zNTiBfh>x&hUR^j#-<5lw?JoDL8_q`Q;)&jJ9b&UHMTrkV6?TwUn&*B8>K zoeW1zw}&-(Kko=?49@;)UmI14=(ha++GFwgc-uqvZ{ZU)RHn{Ew@+M8P#o08%VVjv ze>@`m6pP@7Kp79)gB;McMZ2AHB52rj7&yQ=9u6}d_>H68gG3%Ip*rosYW9m;H}>tp z=i{-_!cp$MWFO`hW=au-ztKL{@cviFZK*UtXgsUhNrUgw_(by3I2i zBz5}dl%>P3j0y&+Uy`6<@9kk`Ut6!=%V>Jx0lHj`Om6y&sgA0!AIqD2?ghK*(sDYU zeUw)Vn#Y0;mVRzl7aZk=ZoUOUP_+9x(({Rywno6#i&F?4_i?c)X$RekoVn)#0=sEGdZmt*&)(2Lw#`noHx%Ue z3Bs}l4$rw!I><@~s1j1a&ORT-_t_tYo6|`<#SqDK&LV55zI5W}|0z zVzYX~J9~b@TeF7T#3ThwwaFC?fY!V1<7SWd$k&;OBS`eG$K+>8Fsg@O3bk=S7PE!f zfV{&rdIN-sSsM!yK<`wW&$c^10Xd$$({mUG+WzIsms~cFnlW4Y%BOD3ex0Cm2<;h; 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} else { @@ -162,8 +162,8 @@ uint8_t ed64_bios_init() { spi_cfg = SPI_CFG_SS | BI_SPI_SPD_LO; - ed64_bios_reg_wr(REG_CFG, ED_CFG_SDRAM_ON); - ed64_bios_reg_wr(REG_SPI_CFG, spi_cfg); + ed64_bios_reg_write(REG_CFG, ED_CFG_SDRAM_ON); + ed64_bios_reg_write(REG_SPI_CFG, spi_cfg); ed64_bios_save_type = 0; @@ -172,21 +172,21 @@ uint8_t ed64_bios_init() { void ed64_bios_reset_spx() { - uint16_t cfg = ed64_bios_reg_rd(REG_CFG); + uint16_t cfg = ed64_bios_reg_read(REG_CFG); - ed64_bios_reg_wr(REG_CFG, 0x8000); + ed64_bios_reg_write(REG_CFG, 0x8000); wait_ms(100); - ed64_bios_reg_wr(REG_CFG, cfg); + ed64_bios_reg_write(REG_CFG, cfg); wait_ms(100); } -uint32_t ed64_bios_reg_rd(uint32_t reg) { +uint32_t ed64_bios_reg_read(uint32_t reg) { *(volatile uint32_t *) (REGS_BASE); return *(volatile uint32_t *) (REGS_BASE + reg * 4); } -void ed64_bios_reg_wr(uint32_t reg, uint32_t data) { +void ed64_bios_reg_write(uint32_t reg, uint32_t data) { *(volatile uint32_t *) (REGS_BASE); *(volatile uint32_t *) (REGS_BASE + reg * 4) = data; @@ -196,8 +196,8 @@ void ed64_bios_reg_wr(uint32_t reg, uint32_t data) { uint8_t ed64_bios_dma_busy() { - while ((ed64_bios_reg_rd(REG_STATUS) & STATE_DMA_BUSY) != 0); - return ed64_bios_reg_rd(REG_STATUS) & STATE_DMA_TOUT; + while ((ed64_bios_reg_read(REG_STATUS) & STATE_DMA_BUSY) != 0); + return ed64_bios_reg_read(REG_STATUS) & STATE_DMA_TOUT; } @@ -205,12 +205,12 @@ uint8_t ed64_bios_dma_busy() { uint8_t ed64_bios_usb_rd_busy() { - return ed64_bios_reg_rd(REG_STATUS) & STATE_USB_RXF; + return ed64_bios_reg_read(REG_STATUS) & STATE_USB_RXF; } uint8_t ed64_bios_usb_wr_busy() { - return ed64_bios_reg_rd(REG_STATUS) & STATE_USB_TXE; + return ed64_bios_reg_read(REG_STATUS) & STATE_USB_TXE; } uint8_t ed64_bios_usb_rd(uint32_t saddr, uint32_t slen) { @@ -218,9 +218,9 @@ uint8_t ed64_bios_usb_rd(uint32_t saddr, uint32_t slen) { saddr /= 4; while (ed64_bios_usb_rd_busy() != 0); - ed64_bios_reg_wr(REG_DMA_LEN, slen - 1); - ed64_bios_reg_wr(REG_DMA_RAM_ADDR, saddr); - ed64_bios_reg_wr(REG_DMA_CFG, DCFG_USB_TO_RAM); + ed64_bios_reg_write(REG_DMA_LEN, slen - 1); + ed64_bios_reg_write(REG_DMA_RAM_ADDR, saddr); + ed64_bios_reg_write(REG_DMA_CFG, DCFG_USB_TO_RAM); if (ed64_bios_dma_busy() != 0)return USB_ERROR_FIFO_TIMEOUT; @@ -232,9 +232,9 @@ uint8_t ed64_bios_usb_wr(uint32_t saddr, uint32_t slen) { saddr /= 4; while (ed64_bios_usb_wr_busy() != 0); - ed64_bios_reg_wr(REG_DMA_LEN, slen - 1); - ed64_bios_reg_wr(REG_DMA_RAM_ADDR, saddr); - ed64_bios_reg_wr(REG_DMA_CFG, DCFG_RAM_TO_USB); + ed64_bios_reg_write(REG_DMA_LEN, slen - 1); + ed64_bios_reg_write(REG_DMA_RAM_ADDR, saddr); + ed64_bios_reg_write(REG_DMA_CFG, DCFG_RAM_TO_USB); if (ed64_bios_dma_busy() != 0)return USB_ERROR_FIFO_TIMEOUT; @@ -246,19 +246,19 @@ uint8_t ed64_bios_usb_wr(uint32_t saddr, uint32_t slen) { uint16_t ed64_bios_spi_busy() { - return ed64_bios_reg_rd(REG_STATUS) & STATE_DMA_BUSY; + return ed64_bios_reg_read(REG_STATUS) & STATE_DMA_BUSY; } uint8_t ed64_bios_spi(uint8_t data) { - ed64_bios_reg_wr(REG_SPI, data); + ed64_bios_reg_write(REG_SPI, data); while (ed64_bios_spi_busy()); - return ed64_bios_reg_rd(REG_SPI); + return ed64_bios_reg_read(REG_SPI); } void ed64_bios_spi_nr(uint8_t data) { - ed64_bios_reg_wr(REG_SPI, data); + ed64_bios_reg_write(REG_SPI, data); while (ed64_bios_spi_busy()); } @@ -266,23 +266,23 @@ void ed64_bios_set_spi_spd(uint16_t speed) { spi_cfg &= ~3; spi_cfg |= speed; - ed64_bios_reg_wr(REG_SPI_CFG, spi_cfg); + ed64_bios_reg_write(REG_SPI_CFG, spi_cfg); } void ed64_bios_sd_mode(uint16_t mode) { spi_cfg &= ~(SPI_CFG_1BIT | SPI_CFG_RD | SPI_CFG_DAT); spi_cfg |= mode; - ed64_bios_reg_wr(REG_SPI_CFG, spi_cfg); + ed64_bios_reg_write(REG_SPI_CFG, spi_cfg); } uint8_t ed64_bios_spi_read_to_rom(uint32_t saddr, uint16_t slen) { saddr /= 4; - ed64_bios_reg_wr(REG_DMA_LEN, slen - 1); - ed64_bios_reg_wr(REG_DMA_RAM_ADDR, saddr); - ed64_bios_reg_wr(REG_DMA_CFG, DCFG_SD_TO_RAM); + ed64_bios_reg_write(REG_DMA_LEN, slen - 1); + ed64_bios_reg_write(REG_DMA_RAM_ADDR, saddr); + ed64_bios_reg_write(REG_DMA_CFG, DCFG_SD_TO_RAM); if (ed64_bios_dma_busy() != 0)return EVD_ERROR_MMC_TIMEOUT; @@ -290,15 +290,15 @@ uint8_t ed64_bios_spi_read_to_rom(uint32_t saddr, uint16_t slen) { } void ed64_bios_swap_on() { - uint16_t cfg = ed64_bios_reg_rd(REG_CFG); + uint16_t cfg = ed64_bios_reg_read(REG_CFG); cfg |= ED_CFG_SWAP; - ed64_bios_reg_wr(REG_CFG, cfg); + ed64_bios_reg_write(REG_CFG, cfg); } void ed64_bios_swap_off() { - uint16_t cfg = ed64_bios_reg_rd(REG_CFG); + uint16_t cfg = ed64_bios_reg_read(REG_CFG); cfg &= ~ED_CFG_SWAP; - ed64_bios_reg_wr(REG_CFG, cfg); + ed64_bios_reg_write(REG_CFG, cfg); } uint8_t ed64_bios_get_save_type() { @@ -352,21 +352,21 @@ void ed64_bios_set_save_type(uint8_t type) { if (ram_bank)save_cfg |= SAV_RAM_BANK; save_cfg |= SAV_RAM_BANK_APPLY; - ed64_bios_reg_wr(REG_SAV_CFG, save_cfg); + ed64_bios_reg_write(REG_SAV_CFG, save_cfg); } void ed64_bios_read_bios(void *dst, uint16_t saddr, uint16_t slen) { - uint16_t cfg = ed64_bios_reg_rd(REG_CFG); + uint16_t cfg = ed64_bios_reg_read(REG_CFG); cfg &= ~ED_CFG_SDRAM_ON; - ed64_bios_reg_wr(REG_CFG, cfg); + ed64_bios_reg_write(REG_CFG, cfg); ed64_bios_dma_read_rom(dst, saddr, slen); cfg |= ED_CFG_SDRAM_ON; - ed64_bios_reg_wr(REG_CFG, cfg); + ed64_bios_reg_write(REG_CFG, cfg); } void ed64_bios_dma_read_rom(void *ram, uint32_t saddr, uint32_t slen) { @@ -424,12 +424,12 @@ void ed64_bios_dma_write_sram(void *ram, uint32_t addr, uint32_t len) { uint16_t ed64_bios_msg_rd() { - return ed64_bios_reg_rd(REG_MSG); + return ed64_bios_reg_read(REG_MSG); } void ed64_bios_msg_wr(uint16_t val) { - ed64_bios_reg_wr(REG_MSG, val); + ed64_bios_reg_write(REG_MSG, val); } typedef struct PI_regs_s { @@ -495,28 +495,28 @@ void ed64_bios_dma_write(void *ram, uint32_t addr, uint32_t len) { uint16_t ed64_bios_get_fpga_ver() { - return ed64_bios_reg_rd(REG_VER); + return ed64_bios_reg_read(REG_VER); } void ed64_bios_load_firmware(uint8_t *firmware) { uint32_t i; uint16_t f_ctr = 0; - uint16_t cfg = ed64_bios_reg_rd(REG_CFG); + uint16_t cfg = ed64_bios_reg_read(REG_CFG); cfg &= ~ED_CFG_SDRAM_ON; - ed64_bios_reg_wr(REG_CFG, cfg); + ed64_bios_reg_write(REG_CFG, cfg); - ed64_bios_reg_wr(REG_CFG_CNT, 0); + ed64_bios_reg_write(REG_CFG_CNT, 0); wait_ms(10); - ed64_bios_reg_wr(REG_CFG_CNT, 1); + ed64_bios_reg_write(REG_CFG_CNT, 1); wait_ms(10); i = 0; for (;;) { - ed64_bios_reg_wr(REG_CFG_DAT, *(uint16_t *) & firmware[i]); - while ((ed64_bios_reg_rd(REG_CFG_CNT) & 8) != 0); + ed64_bios_reg_write(REG_CFG_DAT, *(uint16_t *) & firmware[i]); + while ((ed64_bios_reg_read(REG_CFG_CNT) & 8) != 0); f_ctr = firmware[i++] == 0xff ? f_ctr + 1 : 0; if (f_ctr >= 47)break; @@ -525,9 +525,9 @@ void ed64_bios_load_firmware(uint8_t *firmware) { } - while ((ed64_bios_reg_rd(REG_CFG_CNT) & 4) == 0) { - ed64_bios_reg_wr(REG_CFG_DAT, 0xffff); - while ((ed64_bios_reg_rd(REG_CFG_CNT) & 8) != 0); + while ((ed64_bios_reg_read(REG_CFG_CNT) & 4) == 0) { + ed64_bios_reg_write(REG_CFG_DAT, 0xffff); + while ((ed64_bios_reg_read(REG_CFG_CNT) & 8) != 0); } @@ -536,22 +536,22 @@ void ed64_bios_load_firmware(uint8_t *firmware) { void ed64_bios_lock_regs() { - ed64_bios_reg_wr(REG_KEY, 0); + ed64_bios_reg_write(REG_KEY, 0); } void ed64_bios_unlock_regs() { - ed64_bios_reg_wr(REG_KEY, 0x1234); + ed64_bios_reg_write(REG_KEY, ED64_KEY_UNLOCK); } uint16_t ed64_bios_get_cpld_ver() { uint16_t ver; - uint16_t cfg = ed64_bios_reg_rd(REG_CFG); + uint16_t cfg = ed64_bios_reg_read(REG_CFG); - ed64_bios_reg_wr(REG_CFG, 0); - ver = ed64_bios_reg_rd(REG_MAX_VER); - ed64_bios_reg_wr(REG_CFG, cfg); + ed64_bios_reg_write(REG_CFG, 0); + ver = ed64_bios_reg_read(REG_MAX_VER); + ed64_bios_reg_write(REG_CFG, cfg); return ver; } @@ -560,34 +560,34 @@ uint16_t ed64_bios_get_cpld_ver() { void ed64_bios_gpio_mode_rtc() { - uint16_t cfg = ed64_bios_reg_rd(REG_CFG); + uint16_t cfg = ed64_bios_reg_read(REG_CFG); cfg &= ~ED_CFG_GPIO_ON; cfg |= ED_CFG_RTC_ON; - ed64_bios_reg_wr(REG_CFG, cfg); + ed64_bios_reg_write(REG_CFG, cfg); } void ed64_bios_gpio_mode_io() { - uint16_t cfg = ed64_bios_reg_rd(REG_CFG); + uint16_t cfg = ed64_bios_reg_read(REG_CFG); cfg |= ED_CFG_GPIO_ON; - ed64_bios_reg_wr(REG_CFG, cfg); + ed64_bios_reg_write(REG_CFG, cfg); } void ed64_bios_gpio_off() { - uint16_t cfg = ed64_bios_reg_rd(REG_CFG); + uint16_t cfg = ed64_bios_reg_read(REG_CFG); cfg &= ~ED_CFG_GPIO_ON; - ed64_bios_reg_wr(REG_CFG, cfg); + ed64_bios_reg_write(REG_CFG, cfg); } void ed64_bios_gpio_wr(uint8_t data) { - ed64_bios_reg_wr(REG_GPIO, data); + ed64_bios_reg_write(REG_GPIO, data); } uint8_t ed64_bios_gpio_rd() { - return ed64_bios_reg_rd(REG_GPIO); + return ed64_bios_reg_read(REG_GPIO); } @@ -601,39 +601,39 @@ void ed64_bios_set_ram_bank(uint8_t bank) { /* 64DD functions */ -void ed64_bios_dd_ram_oe() { +void ed64_bios_64dd_ram_oe() { - uint16_t cfg = ed64_bios_reg_rd(REG_CFG); + uint16_t cfg = ed64_bios_reg_read(REG_CFG); cfg &= ~ED_CFG_DD_WE; cfg |= ED_CFG_DD_ON; - ed64_bios_reg_wr(REG_CFG, cfg); + ed64_bios_reg_write(REG_CFG, cfg); } -void ed64_bios_dd_ram_we() { +void ed64_bios_64dd_ram_we() { - uint16_t cfg = ed64_bios_reg_rd(REG_CFG); + uint16_t cfg = ed64_bios_reg_read(REG_CFG); cfg |= ED_CFG_DD_ON | ED_CFG_DD_WE; - ed64_bios_reg_wr(REG_CFG, cfg); + ed64_bios_reg_write(REG_CFG, cfg); } -void ed64_bios_dd_ram_off() { +void ed64_bios_64dd_ram_off() { - uint16_t cfg = ed64_bios_reg_rd(REG_CFG); + uint16_t cfg = ed64_bios_reg_read(REG_CFG); cfg &= ~(ED_CFG_DD_ON | ED_CFG_DD_WE); - ed64_bios_reg_wr(REG_CFG, cfg); + ed64_bios_reg_write(REG_CFG, cfg); } -void ed64_bios_dd_ram_clr() { +void ed64_bios_64dd_ram_clr() { - uint16_t cfg = ed64_bios_reg_rd(REG_CFG); + uint16_t cfg = ed64_bios_reg_read(REG_CFG); cfg |= ED_CFG_DD_WE; cfg &= ~ED_CFG_DD_ON; - ed64_bios_reg_wr(REG_CFG, cfg); + ed64_bios_reg_write(REG_CFG, cfg); wait_ms(100); } -uint8_t ed64_bios_dd_ram_supported() { +uint8_t ed64_bios_64dd_ram_supported() { - return (ed64_bios_reg_rd(REG_STATUS) >> 15) & 1; + return (ed64_bios_reg_read(REG_STATUS) >> 15) & 1; } diff --git a/src/flashcart/ed64/ed64_internal.h b/src/flashcart/ed64/ed64_internal.h index 87ae3f80..e61c7c6d 100644 --- a/src/flashcart/ed64/ed64_internal.h +++ b/src/flashcart/ed64/ed64_internal.h @@ -127,8 +127,8 @@ void ed64_bios_dma_write_sram(void *ram, uint32_t addr, uint32_t len); void ed64_bios_lock_regs(); void ed64_bios_unlock_regs(); -uint32_t ed64_bios_reg_rd(uint32_t reg); -void ed64_bios_reg_wr(uint32_t reg, uint32_t data); +uint32_t ed64_bios_reg_read(uint32_t reg); +void ed64_bios_reg_write(uint32_t reg, uint32_t data); void ed64_bios_reset_spx(); /* GPIO functions */ @@ -138,11 +138,11 @@ void ed64_bios_gpio_off(); uint8_t ed64_bios_gpio_rd(); /* 64DD functions */ -void ed64_bios_dd_ram_oe(); -void ed64_bios_dd_ram_we(); -void ed64_bios_dd_ram_off(); -void ed64_bios_dd_ram_clr(); -uint8_t ed64_bios_dd_ram_supported(); +void ed64_bios_64dd_ram_oe(); +void ed64_bios_64dd_ram_we(); +void ed64_bios_64dd_ram_off(); +void ed64_bios_64dd_ram_clr(); +uint8_t ed64_bios_64dd_ram_supported(); /** @} */ /* ed64 */ From ca2f74cc9d36635c4778f12c883fe5b6c4b18523 Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Mon, 17 Jul 2023 20:05:21 +0100 Subject: [PATCH 09/64] Add lock register --- src/flashcart/ed64/ed64_internal.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/flashcart/ed64/ed64_internal.c b/src/flashcart/ed64/ed64_internal.c index 1aecd1d1..bf96e791 100644 --- a/src/flashcart/ed64/ed64_internal.c +++ b/src/flashcart/ed64/ed64_internal.c @@ -2,6 +2,9 @@ #include "ed64_internal.h" +/* Locks the ED64 registers */ +#define ED64_KEY_LOCK 0x0000 +/* Unlocks the ED64 registers */ #define ED64_KEY_UNLOCK 0x1234 #define REG_CFG 0 @@ -164,7 +167,7 @@ uint8_t ed64_bios_init() { spi_cfg = SPI_CFG_SS | BI_SPI_SPD_LO; ed64_bios_reg_write(REG_CFG, ED_CFG_SDRAM_ON); ed64_bios_reg_write(REG_SPI_CFG, spi_cfg); - ed64_bios_save_type = 0; + ed64_bios_save_type = SAVE_TYPE_OFF; return cold_start; @@ -536,7 +539,7 @@ void ed64_bios_load_firmware(uint8_t *firmware) { void ed64_bios_lock_regs() { - ed64_bios_reg_write(REG_KEY, 0); + ed64_bios_reg_write(REG_KEY, ED64_KEY_LOCK); } void ed64_bios_unlock_regs() { From b99e30f1fa162a75321eaffb59c85ef80a04e6eb Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Mon, 17 Jul 2023 20:35:47 +0100 Subject: [PATCH 10/64] Improve some names --- assets/FiraMono-Bold.font64 | Bin 5644 -> 0 bytes src/flashcart/ed64/ed64_internal.c | 20 ++++++++++---------- src/flashcart/ed64/ed64_internal.h | 6 +++--- 3 files changed, 13 insertions(+), 13 deletions(-) delete mode 100644 assets/FiraMono-Bold.font64 diff --git a/assets/FiraMono-Bold.font64 b/assets/FiraMono-Bold.font64 deleted file mode 100644 index 862bdfed98f04d7d1d034d8386e1a9c9c5962c10..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 5644 zcmbu-_ahVzz<}{0B&0Gb#TD6w%8omfO~w%+Ga*Ixyt}WFm7JM%x$N!i8E0Q8D{{$* za~zkm4>#ZU{Ttrrr_UeoJbA2r|IFDl|C<2q%ozvOOGlACJv&Wlk_`IsvZ1nJSChw? zoA8^4{nBBNx?GPgo#FY<^IbeR2%LJ^kiDG8eEUBRZ)0%qAG_Moz)7o%#j(Fu7aXnf z7Hn8Mt{1ts%i$D_auYgDbp`H$w|{qaDI4CQGw4j}W}|8T+o89f?)EvjPbWkl`xOVw zNTiBfh>x&hUR^j#-<5lw?JoDL8_q`Q;)&jJ9b&UHMTrkV6?TwUn&*B8>K zoeW1zw}&-(Kko=?49@;)UmI14=(ha++GFwgc-uqvZ{ZU)RHn{Ew@+M8P#o08%VVjv ze>@`m6pP@7Kp79)gB;McMZ2AHB52rj7&yQ=9u6}d_>H68gG3%Ip*rosYW9m;H}>tp z=i{-_!cp$MWFO`hW=au-ztKL{@cviFZK*UtXgsUhNrUgw_(by3I2i zBz5}dl%>P3j0y&+Uy`6<@9kk`Ut6!=%V>Jx0lHj`Om6y&sgA0!AIqD2?ghK*(sDYU zeUw)Vn#Y0;mVRzl7aZk=ZoUOUP_+9x(({Rywno6#i&F?4_i?c)X$RekoVn)#0=sEGdZmt*&)(2Lw#`noHx%Ue z3Bs}l4$rw!I><@~s1j1a&ORT-_t_tYo6|`<#SqDK&LV55zI5W}|0z zVzYX~J9~b@TeF7T#3ThwwaFC?fY!V1<7SWd$k&;OBS`eG$K+>8Fsg@O3bk=S7PE!f zfV{&rdIN-sSsM!yK<`wW&$c^10Xd$$({mUG+WzIsms~cFnlW4Y%BOD3ex0Cm2<;h; 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#define STATE_DMA_BUSY 1 @@ -45,19 +50,21 @@ #define SAV_SRM_ON 2 #define SAV_EEP_SIZE 4 #define SAV_SRM_SIZE 8 + #define SAV_RAM_BANK 128 #define SAV_RAM_BANK_APPLY 32768 -#define ED_CFG_SDRAM_ON 1 -#define ED_CFG_SWAP 2 -#define ED_CFG_WR_MOD 4 -#define ED_CFG_WR_ADDR_MASK 8 -#define ED_CFG_RTC_ON 32 -#define ED_CFG_GPIO_ON 96 -#define ED_CFG_DD_ON 256 -#define ED_CFG_DD_WE 512 +typedef enum { + ED_CFG_SDRAM_ON = 1, + ED_CFG_SWAP = 2, + ED_CFG_WR_MOD = 4, + ED_CFG_WR_ADDR_MASK = 8, + ED_CFG_RTC_ON = 32, + ED_CFG_GPIO_ON = 96, + ED_CFG_DD_ON = 256, + ED_CFG_DD_WE = 512, +} ed64_config_t; -#define REGS_BASE 0xA8040000 // #define MAX_MSG_SKIP_FW_INIT (1 << 8) // #define MAX_MSG_SKIP_TV_INIT (1 << 9) @@ -86,12 +93,14 @@ uint8_t ed64_bios_save_type; /* register functions (dependent on flashcart version) */ +/* register functions for V2 & V2.5 */ void ed64_bios_io_reg_v2(uint32_t addr, uint32_t dat) { *(volatile uint32_t *) (ROM_ADDR); *(volatile uint32_t *) (ROM_ADDR + addr) = dat; } +/* register functions for V3 */ void ed64_bios_io_reg_v3(uint32_t addr, uint16_t dat) { ed64_bios_reg_write(REG_FL_ADDR, addr); @@ -100,6 +109,7 @@ void ed64_bios_io_reg_v3(uint32_t addr, uint16_t dat) { /* initialize functions (dependent on flashcart version) */ +/* Initilize V2 & 2.5 cart */ void ed64_bios_init_v2() { uint8_t buff[512]; @@ -114,6 +124,7 @@ void ed64_bios_init_v2() { } +/* Initilize V3 cart */ void ed64_bios_init_v3() { uint8_t buff[1024]; @@ -265,7 +276,7 @@ void ed64_bios_spi_nr(uint8_t data) { while (ed64_bios_spi_busy()); } -void ed64_bios_set_spi_spd(uint16_t speed) { +void ed64_bios_set_spi_speed(uint16_t speed) { spi_cfg &= ~3; spi_cfg |= speed; @@ -292,13 +303,13 @@ uint8_t ed64_bios_spi_read_to_rom(uint32_t saddr, uint16_t slen) { return 0; } -void ed64_bios_swap_on() { +void ed64_bios_byteswap_on() { uint16_t cfg = ed64_bios_reg_read(REG_CFG); cfg |= ED_CFG_SWAP; ed64_bios_reg_write(REG_CFG, cfg); } -void ed64_bios_swap_off() { +void ed64_bios_byteswap_off() { uint16_t cfg = ed64_bios_reg_read(REG_CFG); cfg &= ~ED_CFG_SWAP; ed64_bios_reg_write(REG_CFG, cfg); @@ -561,6 +572,7 @@ uint16_t ed64_bios_get_cpld_version() { /* GPIO functions */ +/* GPIO mode RTC */ void ed64_bios_gpio_mode_rtc() { uint16_t cfg = ed64_bios_reg_read(REG_CFG); @@ -569,6 +581,7 @@ void ed64_bios_gpio_mode_rtc() { ed64_bios_reg_write(REG_CFG, cfg); } +/* GPIO mode ON */ void ed64_bios_gpio_mode_io() { uint16_t cfg = ed64_bios_reg_read(REG_CFG); @@ -576,6 +589,7 @@ void ed64_bios_gpio_mode_io() { ed64_bios_reg_write(REG_CFG, cfg); } +/* GPIO mode OFF */ void ed64_bios_gpio_off() { uint16_t cfg = ed64_bios_reg_read(REG_CFG); @@ -583,11 +597,13 @@ void ed64_bios_gpio_off() { ed64_bios_reg_write(REG_CFG, cfg); } +/* GPIO mode write */ void ed64_bios_gpio_write(uint8_t data) { ed64_bios_reg_write(REG_GPIO, data); } +/* GPIO mode read */ uint8_t ed64_bios_gpio_read() { return ed64_bios_reg_read(REG_GPIO); @@ -595,15 +611,9 @@ uint8_t ed64_bios_gpio_read() { -void ed64_bios_set_ram_bank(uint8_t bank) { - - ed64_bios_ram_bank = bank == 0 ? 0 : 1; - -} - - /* 64DD functions */ +/* 64DD On and Dissabled?! */ void ed64_bios_64dd_ram_oe() { uint16_t cfg = ed64_bios_reg_read(REG_CFG); @@ -612,6 +622,7 @@ void ed64_bios_64dd_ram_oe() { ed64_bios_reg_write(REG_CFG, cfg); } +/* 64DD Write Enable?? */ void ed64_bios_64dd_ram_we() { uint16_t cfg = ed64_bios_reg_read(REG_CFG); @@ -619,6 +630,7 @@ void ed64_bios_64dd_ram_we() { ed64_bios_reg_write(REG_CFG, cfg); } +/* 64DD Disabled?? */ void ed64_bios_64dd_ram_off() { uint16_t cfg = ed64_bios_reg_read(REG_CFG); @@ -626,6 +638,7 @@ void ed64_bios_64dd_ram_off() { ed64_bios_reg_write(REG_CFG, cfg); } +/* 64DD Save RAM Clear */ void ed64_bios_64dd_ram_clr() { uint16_t cfg = ed64_bios_reg_read(REG_CFG); @@ -635,8 +648,15 @@ void ed64_bios_64dd_ram_clr() { wait_ms(100); } +/* 64DD Allowed on this cart?! */ uint8_t ed64_bios_64dd_ram_supported() { return (ed64_bios_reg_read(REG_STATUS) >> 15) & 1; } + +void ed64_bios_set_ram_bank(uint8_t bank) { + + ed64_bios_ram_bank = bank == 0 ? 0 : 1; + +} diff --git a/src/flashcart/ed64/ed64_internal.h b/src/flashcart/ed64/ed64_internal.h index c03112fd..dc2b70fb 100644 --- a/src/flashcart/ed64/ed64_internal.h +++ b/src/flashcart/ed64/ed64_internal.h @@ -95,20 +95,20 @@ uint16_t ed64_bios_get_cpld_version(); void ed64_bios_load_firmware(uint8_t *firmware); /* USB functions */ -uint8_t ed64_bios_usb_rd_busy(); +uint8_t ed64_bios_usb_read_busy(); uint8_t ed64_bios_usb_rd(uint32_t saddr, uint32_t slen); uint8_t ed64_bios_usb_wr(uint32_t saddr, uint32_t slen); /* SPI functions */ uint8_t ed64_bios_spi(uint8_t data); void ed64_bios_spi_nr(uint8_t data); -void ed64_bios_set_spi_spd(uint16_t speed); +void ed64_bios_set_spi_speed(uint16_t speed); /* SD Card functions */ void ed64_bios_sd_mode(uint16_t mode); uint8_t ed64_bios_spi_read_to_rom(uint32_t saddr, uint16_t slen); -void ed64_bios_swap_on(); -void ed64_bios_swap_off(); +void ed64_bios_byteswap_on(); +void ed64_bios_byteswap_off(); /* Save functions */ uint8_t ed64_bios_get_save_type(); From f8f4d0338be551a201607d2b631ad1fd4b62be62 Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Mon, 17 Jul 2023 22:59:24 +0100 Subject: [PATCH 12/64] Improve FPGA firmware variables --- src/flashcart/ed64/ed64_internal.c | 83 ++++++++++++++++-------------- src/flashcart/ed64/ed64_internal.h | 8 +-- 2 files changed, 49 insertions(+), 42 deletions(-) diff --git a/src/flashcart/ed64/ed64_internal.c b/src/flashcart/ed64/ed64_internal.c index 1a2e7eb6..b28f58ab 100644 --- a/src/flashcart/ed64/ed64_internal.c +++ b/src/flashcart/ed64/ed64_internal.c @@ -25,10 +25,11 @@ typedef enum { REG_FPGA_VER = 11, REG_GPIO = 12, +// FIXME: these are register values: REG_CFG_CNT = 16, REG_CFG_DAT = 17, - REG_MAX_MSG = 18, - REG_MAX_VER = 19, + REG_FPGA_FW_MSG = 18, + REG_FPGA_FW_VER = 19, REG_FL_ADDR = 20, REG_FL_DATA = 21, } ed64_registers_t; @@ -66,13 +67,13 @@ typedef enum { } ed64_config_t; -// #define MAX_MSG_SKIP_FW_INIT (1 << 8) -// #define MAX_MSG_SKIP_TV_INIT (1 << 9) -// #define MAX_MSG_TV_TYPE1 (1 << 10) -// #define MAX_MSG_TV_TYPE2 (1 << 11) -// #define MAX_MSG_SKIP_SD_INIT (1 << 12) -// #define MAX_MSG_SD_TYPE (1 << 13) -#define MAX_MSG_HOT_START (1 << 14) +// #define FPGA_FW_MSG_SKIP_FW_INIT (1 << 8) +// #define FPGA_FW_MSG_SKIP_TV_INIT (1 << 9) +// #define FPGA_FW_MSG_TV_TYPE1 (1 << 10) +// #define FPGA_FW_MSG_TV_TYPE2 (1 << 11) +// #define FPGA_FW_MSG_SKIP_SD_INIT (1 << 12) +// #define FPGA_FW_MSG_SD_TYPE (1 << 13) +#define FPGA_FW_MSG_HOT_START (1 << 14) uint32_t ed64_bios_reg_read(uint32_t reg); void ed64_bios_reg_write(uint32_t reg, uint32_t data); @@ -146,8 +147,8 @@ void ed64_bios_init_v3() { /* Initialize cart */ uint8_t ed64_bios_init() { - uint16_t max_ver; - uint16_t max_msg; + uint16_t firmware_ver; + uint16_t firmware_msg; uint8_t cold_start; @@ -159,15 +160,15 @@ uint8_t ed64_bios_init() { ed64_bios_reg_write(REG_CFG, 0x0000); - max_msg = ed64_bios_reg_read(REG_MAX_MSG); - cold_start = (max_msg & MAX_MSG_HOT_START) == 0 ? 1 : 0; + firmware_msg = ed64_bios_reg_read(REG_FPGA_FW_MSG); + cold_start = (firmware_msg & FPGA_FW_MSG_HOT_START) == 0 ? 1 : 0; if (cold_start) { - max_msg |= MAX_MSG_HOT_START; - ed64_bios_reg_write(REG_MAX_MSG, max_msg); + firmware_msg |= FPGA_FW_MSG_HOT_START; + ed64_bios_reg_write(REG_FPGA_FW_MSG, firmware_msg); } - max_ver = ed64_bios_reg_read(REG_MAX_VER); - if ((max_ver & 0xf000) >= 0x2000) { + firmware_ver = ed64_bios_reg_read(REG_FPGA_FW_VER); + if ((firmware_ver & 0xf000) >= 0x2000) { ed64_bios_init_v3(); } else { ed64_bios_init_v2(); @@ -217,20 +218,23 @@ uint8_t ed64_bios_dma_busy() { /* USB functions */ -uint8_t ed64_bios_usb_rd_busy() { +/* USB read is busy */ +uint8_t ed64_bios_usb_read_busy() { return ed64_bios_reg_read(REG_STATUS) & STATE_USB_RXF; } -uint8_t ed64_bios_usb_wr_busy() { +/* USB write is busy */ +uint8_t ed64_bios_usb_write_busy() { return ed64_bios_reg_read(REG_STATUS) & STATE_USB_TXE; } -uint8_t ed64_bios_usb_rd(uint32_t saddr, uint32_t slen) { +/* USB read */ +uint8_t ed64_bios_usb_read(uint32_t saddr, uint32_t slen) { saddr /= 4; - while (ed64_bios_usb_rd_busy() != 0); + while (ed64_bios_usb_read_busy() != 0); ed64_bios_reg_write(REG_DMA_LEN, slen - 1); ed64_bios_reg_write(REG_DMA_RAM_ADDR, saddr); @@ -241,10 +245,11 @@ uint8_t ed64_bios_usb_rd(uint32_t saddr, uint32_t slen) { return 0; } -uint8_t ed64_bios_usb_wr(uint32_t saddr, uint32_t slen) { +/* USB write */ +uint8_t ed64_bios_usb_write(uint32_t saddr, uint32_t slen) { saddr /= 4; - while (ed64_bios_usb_wr_busy() != 0); + while (ed64_bios_usb_write_busy() != 0); ed64_bios_reg_write(REG_DMA_LEN, slen - 1); ed64_bios_reg_write(REG_DMA_RAM_ADDR, saddr); @@ -507,11 +512,25 @@ void ed64_bios_dma_write(void *ram, uint32_t addr, uint32_t len) { ed64_bios_dma_w(ram, addr, len); } +/** @brief Get the current FPGA version */ uint16_t ed64_bios_get_fpga_version() { return ed64_bios_reg_read(REG_FPGA_VER); } +/** @brief Get the current CPLD version */ +uint16_t ed64_bios_get_cpld_version() { + + uint16_t cpld_version; + uint16_t cfg = ed64_bios_reg_read(REG_CFG); + + ed64_bios_reg_write(REG_CFG, 0); + cpld_version = ed64_bios_reg_read(REG_FPGA_FW_VER); + ed64_bios_reg_write(REG_CFG, cfg); + + return cpld_version; +} + void ed64_bios_load_firmware(uint8_t *firmware) { uint32_t i; @@ -558,18 +577,6 @@ void ed64_bios_unlock_regs() { } -uint16_t ed64_bios_get_cpld_version() { - - uint16_t cpld_version; - uint16_t cfg = ed64_bios_reg_read(REG_CFG); - - ed64_bios_reg_write(REG_CFG, 0); - cpld_version = ed64_bios_reg_read(REG_MAX_VER); - ed64_bios_reg_write(REG_CFG, cfg); - - return cpld_version; -} - /* GPIO functions */ /* GPIO mode RTC */ @@ -613,7 +620,7 @@ uint8_t ed64_bios_gpio_read() { /* 64DD functions */ -/* 64DD On and Dissabled?! */ +/* 64DD ON and Enabled?! */ void ed64_bios_64dd_ram_oe() { uint16_t cfg = ed64_bios_reg_read(REG_CFG); @@ -639,7 +646,7 @@ void ed64_bios_64dd_ram_off() { } /* 64DD Save RAM Clear */ -void ed64_bios_64dd_ram_clr() { +void ed64_bios_64dd_ram_clear() { uint16_t cfg = ed64_bios_reg_read(REG_CFG); cfg |= ED_CFG_DD_WE; @@ -649,7 +656,7 @@ void ed64_bios_64dd_ram_clr() { } /* 64DD Allowed on this cart?! */ -uint8_t ed64_bios_64dd_ram_supported() { +uint8_t ed64_bios_get_64dd_ram_supported() { return (ed64_bios_reg_read(REG_STATUS) >> 15) & 1; diff --git a/src/flashcart/ed64/ed64_internal.h b/src/flashcart/ed64/ed64_internal.h index dc2b70fb..7c6a94ec 100644 --- a/src/flashcart/ed64/ed64_internal.h +++ b/src/flashcart/ed64/ed64_internal.h @@ -96,8 +96,8 @@ void ed64_bios_load_firmware(uint8_t *firmware); /* USB functions */ uint8_t ed64_bios_usb_read_busy(); -uint8_t ed64_bios_usb_rd(uint32_t saddr, uint32_t slen); -uint8_t ed64_bios_usb_wr(uint32_t saddr, uint32_t slen); +uint8_t ed64_bios_usb_read(uint32_t saddr, uint32_t slen); +uint8_t ed64_bios_usb_write(uint32_t saddr, uint32_t slen); /* SPI functions */ uint8_t ed64_bios_spi(uint8_t data); @@ -141,8 +141,8 @@ uint8_t ed64_bios_gpio_read(); void ed64_bios_64dd_ram_oe(); void ed64_bios_64dd_ram_we(); void ed64_bios_64dd_ram_off(); -void ed64_bios_64dd_ram_clr(); -uint8_t ed64_bios_64dd_ram_supported(); +void ed64_bios_64dd_ram_clear(); +uint8_t ed64_bios_get_64dd_ram_supported(); /** @} */ /* ed64 */ From e6be62dfb7377cb20c6b09c670c33b484f223ed3 Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Tue, 18 Jul 2023 00:12:03 +0100 Subject: [PATCH 13/64] Improve names --- src/flashcart/ed64/ed64_internal.c | 109 +++++++++++++++-------------- 1 file changed, 57 insertions(+), 52 deletions(-) diff --git a/src/flashcart/ed64/ed64_internal.c b/src/flashcart/ed64/ed64_internal.c index b28f58ab..d3a08440 100644 --- a/src/flashcart/ed64/ed64_internal.c +++ b/src/flashcart/ed64/ed64_internal.c @@ -13,7 +13,7 @@ typedef enum { REG_CFG = 0, REG_STATUS = 1, - REG_DMA_LEN = 2, + REG_DMA_LENGTH = 2, REG_DMA_RAM_ADDR = 3, REG_MSG = 4, REG_DMA_CFG = 5, @@ -25,22 +25,27 @@ typedef enum { REG_FPGA_VER = 11, REG_GPIO = 12, -// FIXME: these are register values: - REG_CFG_CNT = 16, - REG_CFG_DAT = 17, - REG_FPGA_FW_MSG = 18, - REG_FPGA_FW_VER = 19, - REG_FL_ADDR = 20, - REG_FL_DATA = 21, } ed64_registers_t; +typedef enum { + REG_CFG_COUNT = 16, + REG_CFG_DATA = 17, + REG_FPGA_FW_DATA = 18, + REG_FPGA_FW_VER = 19, + REG_FLASHRAM_ADDR = 20, + REG_FLASHRAM_DATA = 21, + +} ed64_register_values_t; + + #define STATE_DMA_BUSY 1 #define STATE_DMA_TOUT 2 #define STATE_USB_TXE 4 #define STATE_USB_RXF 8 #define STATE_SPI 16 +// Default config? #define DCFG_SD_TO_RAM 1 #define DCFG_RAM_TO_SD 2 #define DCFG_USB_TO_RAM 3 @@ -57,23 +62,23 @@ typedef enum { typedef enum { ED_CFG_SDRAM_ON = 1, - ED_CFG_SWAP = 2, - ED_CFG_WR_MOD = 4, - ED_CFG_WR_ADDR_MASK = 8, + ED_CFG_BYTESWAP_ON = 2, + ED_CFG_WRITE_MODE_ON = 4, + ED_CFG_WRITE_ADDR_MASK = 8, ED_CFG_RTC_ON = 32, ED_CFG_GPIO_ON = 96, - ED_CFG_DD_ON = 256, - ED_CFG_DD_WE = 512, + ED_CFG_64DD_ON = 256, + ED_CFG_64DD_WRITE_ENABLED = 512, } ed64_config_t; -// #define FPGA_FW_MSG_SKIP_FW_INIT (1 << 8) -// #define FPGA_FW_MSG_SKIP_TV_INIT (1 << 9) -// #define FPGA_FW_MSG_TV_TYPE1 (1 << 10) -// #define FPGA_FW_MSG_TV_TYPE2 (1 << 11) -// #define FPGA_FW_MSG_SKIP_SD_INIT (1 << 12) -// #define FPGA_FW_MSG_SD_TYPE (1 << 13) -#define FPGA_FW_MSG_HOT_START (1 << 14) +// #define FPGA_FW_DATA_SKIP_FW_INIT (1 << 8) +// #define FPGA_FW_DATA_SKIP_TV_INIT (1 << 9) +// #define FPGA_FW_DATA_TV_TYPE1 (1 << 10) +// #define FPGA_FW_DATA_TV_TYPE2 (1 << 11) +// #define FPGA_FW_DATA_SKIP_SD_INIT (1 << 12) +// #define FPGA_FW_DATA_SD_TYPE (1 << 13) +#define FPGA_FW_DATA_HOT_START (1 << 14) uint32_t ed64_bios_reg_read(uint32_t reg); void ed64_bios_reg_write(uint32_t reg, uint32_t data); @@ -104,8 +109,8 @@ void ed64_bios_io_reg_v2(uint32_t addr, uint32_t dat) { /* register functions for V3 */ void ed64_bios_io_reg_v3(uint32_t addr, uint16_t dat) { - ed64_bios_reg_write(REG_FL_ADDR, addr); - ed64_bios_reg_write(REG_FL_DATA, dat); + ed64_bios_reg_write(REG_FLASHRAM_ADDR, addr); + ed64_bios_reg_write(REG_FLASHRAM_DATA, dat); } /* initialize functions (dependent on flashcart version) */ @@ -132,14 +137,14 @@ void ed64_bios_init_v3() { uint16_t cfg = ed64_bios_reg_read(REG_CFG); ed64_bios_reg_write(REG_CFG, 0); - ed64_bios_reg_write(REG_CFG_CNT, 161); + ed64_bios_reg_write(REG_CFG_COUNT, 161); ed64_bios_io_reg_v3(0x55, 0x98); ed64_bios_dma_read_rom(buff, 0, 2); ed64_bios_io_reg_v3(0x55, 0xF0); ed64_bios_dma_read_rom(buff, 0, 2); ed64_bios_dma_read_rom(buff, 1024, 2); ed64_bios_dma_read_rom(buff, 1024 + 256 - 2, 2); - ed64_bios_reg_write(REG_CFG_CNT, 1); + ed64_bios_reg_write(REG_CFG_COUNT, 1); ed64_bios_reg_write(REG_CFG, cfg); } @@ -160,11 +165,11 @@ uint8_t ed64_bios_init() { ed64_bios_reg_write(REG_CFG, 0x0000); - firmware_msg = ed64_bios_reg_read(REG_FPGA_FW_MSG); - cold_start = (firmware_msg & FPGA_FW_MSG_HOT_START) == 0 ? 1 : 0; + firmware_msg = ed64_bios_reg_read(REG_FPGA_FW_DATA); + cold_start = (firmware_msg & FPGA_FW_DATA_HOT_START) == 0 ? 1 : 0; if (cold_start) { - firmware_msg |= FPGA_FW_MSG_HOT_START; - ed64_bios_reg_write(REG_FPGA_FW_MSG, firmware_msg); + firmware_msg |= FPGA_FW_DATA_HOT_START; + ed64_bios_reg_write(REG_FPGA_FW_DATA, firmware_msg); } firmware_ver = ed64_bios_reg_read(REG_FPGA_FW_VER); @@ -236,7 +241,7 @@ uint8_t ed64_bios_usb_read(uint32_t saddr, uint32_t slen) { saddr /= 4; while (ed64_bios_usb_read_busy() != 0); - ed64_bios_reg_write(REG_DMA_LEN, slen - 1); + ed64_bios_reg_write(REG_DMA_LENGTH, slen - 1); ed64_bios_reg_write(REG_DMA_RAM_ADDR, saddr); ed64_bios_reg_write(REG_DMA_CFG, DCFG_USB_TO_RAM); @@ -251,7 +256,7 @@ uint8_t ed64_bios_usb_write(uint32_t saddr, uint32_t slen) { saddr /= 4; while (ed64_bios_usb_write_busy() != 0); - ed64_bios_reg_write(REG_DMA_LEN, slen - 1); + ed64_bios_reg_write(REG_DMA_LENGTH, slen - 1); ed64_bios_reg_write(REG_DMA_RAM_ADDR, saddr); ed64_bios_reg_write(REG_DMA_CFG, DCFG_RAM_TO_USB); @@ -299,7 +304,7 @@ uint8_t ed64_bios_spi_read_to_rom(uint32_t saddr, uint16_t slen) { saddr /= 4; - ed64_bios_reg_write(REG_DMA_LEN, slen - 1); + ed64_bios_reg_write(REG_DMA_LENGTH, slen - 1); ed64_bios_reg_write(REG_DMA_RAM_ADDR, saddr); ed64_bios_reg_write(REG_DMA_CFG, DCFG_SD_TO_RAM); @@ -310,13 +315,13 @@ uint8_t ed64_bios_spi_read_to_rom(uint32_t saddr, uint16_t slen) { void ed64_bios_byteswap_on() { uint16_t cfg = ed64_bios_reg_read(REG_CFG); - cfg |= ED_CFG_SWAP; + cfg |= ED_CFG_BYTESWAP_ON; ed64_bios_reg_write(REG_CFG, cfg); } void ed64_bios_byteswap_off() { uint16_t cfg = ed64_bios_reg_read(REG_CFG); - cfg &= ~ED_CFG_SWAP; + cfg &= ~ED_CFG_BYTESWAP_ON; ed64_bios_reg_write(REG_CFG, cfg); } @@ -375,6 +380,12 @@ void ed64_bios_set_save_type(uint8_t type) { } +void ed64_bios_set_ram_bank(uint8_t bank) { + + ed64_bios_ram_bank = bank == 0 ? 0 : 1; + +} + void ed64_bios_read_bios(void *dst, uint16_t saddr, uint16_t slen) { uint16_t cfg = ed64_bios_reg_read(REG_CFG); @@ -540,16 +551,16 @@ void ed64_bios_load_firmware(uint8_t *firmware) { cfg &= ~ED_CFG_SDRAM_ON; ed64_bios_reg_write(REG_CFG, cfg); - ed64_bios_reg_write(REG_CFG_CNT, 0); + ed64_bios_reg_write(REG_CFG_COUNT, 0); wait_ms(10); - ed64_bios_reg_write(REG_CFG_CNT, 1); + ed64_bios_reg_write(REG_CFG_COUNT, 1); wait_ms(10); i = 0; for (;;) { - ed64_bios_reg_write(REG_CFG_DAT, *(uint16_t *) & firmware[i]); - while ((ed64_bios_reg_read(REG_CFG_CNT) & 8) != 0); + ed64_bios_reg_write(REG_CFG_DATA, *(uint16_t *) & firmware[i]); + while ((ed64_bios_reg_read(REG_CFG_COUNT) & 8) != 0); f_ctr = firmware[i++] == 0xff ? f_ctr + 1 : 0; if (f_ctr >= 47)break; @@ -558,9 +569,9 @@ void ed64_bios_load_firmware(uint8_t *firmware) { } - while ((ed64_bios_reg_read(REG_CFG_CNT) & 4) == 0) { - ed64_bios_reg_write(REG_CFG_DAT, 0xffff); - while ((ed64_bios_reg_read(REG_CFG_CNT) & 8) != 0); + while ((ed64_bios_reg_read(REG_CFG_COUNT) & 4) == 0) { + ed64_bios_reg_write(REG_CFG_DATA, 0xffff); + while ((ed64_bios_reg_read(REG_CFG_COUNT) & 8) != 0); } @@ -624,8 +635,8 @@ uint8_t ed64_bios_gpio_read() { void ed64_bios_64dd_ram_oe() { uint16_t cfg = ed64_bios_reg_read(REG_CFG); - cfg &= ~ED_CFG_DD_WE; - cfg |= ED_CFG_DD_ON; + cfg &= ~ED_CFG_64DD_WRITE_ENABLED; + cfg |= ED_CFG_64DD_ON; ed64_bios_reg_write(REG_CFG, cfg); } @@ -633,7 +644,7 @@ void ed64_bios_64dd_ram_oe() { void ed64_bios_64dd_ram_we() { uint16_t cfg = ed64_bios_reg_read(REG_CFG); - cfg |= ED_CFG_DD_ON | ED_CFG_DD_WE; + cfg |= ED_CFG_64DD_ON | ED_CFG_64DD_WRITE_ENABLED; ed64_bios_reg_write(REG_CFG, cfg); } @@ -641,7 +652,7 @@ void ed64_bios_64dd_ram_we() { void ed64_bios_64dd_ram_off() { uint16_t cfg = ed64_bios_reg_read(REG_CFG); - cfg &= ~(ED_CFG_DD_ON | ED_CFG_DD_WE); + cfg &= ~(ED_CFG_64DD_ON | ED_CFG_64DD_WRITE_ENABLED); ed64_bios_reg_write(REG_CFG, cfg); } @@ -649,8 +660,8 @@ void ed64_bios_64dd_ram_off() { void ed64_bios_64dd_ram_clear() { uint16_t cfg = ed64_bios_reg_read(REG_CFG); - cfg |= ED_CFG_DD_WE; - cfg &= ~ED_CFG_DD_ON; + cfg |= ED_CFG_64DD_WRITE_ENABLED; + cfg &= ~ED_CFG_64DD_ON; ed64_bios_reg_write(REG_CFG, cfg); wait_ms(100); } @@ -661,9 +672,3 @@ uint8_t ed64_bios_get_64dd_ram_supported() { return (ed64_bios_reg_read(REG_STATUS) >> 15) & 1; } - -void ed64_bios_set_ram_bank(uint8_t bank) { - - ed64_bios_ram_bank = bank == 0 ? 0 : 1; - -} From aa0c80ae5719082dc0b9d9eaff54eae4282396fd Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Tue, 18 Jul 2023 00:27:52 +0100 Subject: [PATCH 14/64] Further renames --- src/flashcart/ed64/ed64_internal.c | 30 +++++++++++++++--------------- src/flashcart/ed64/ed64_internal.h | 12 ++++++------ 2 files changed, 21 insertions(+), 21 deletions(-) diff --git a/src/flashcart/ed64/ed64_internal.c b/src/flashcart/ed64/ed64_internal.c index d3a08440..d9c58b61 100644 --- a/src/flashcart/ed64/ed64_internal.c +++ b/src/flashcart/ed64/ed64_internal.c @@ -236,13 +236,13 @@ uint8_t ed64_bios_usb_write_busy() { } /* USB read */ -uint8_t ed64_bios_usb_read(uint32_t saddr, uint32_t slen) { +uint8_t ed64_bios_usb_read(uint32_t start_address, uint32_t slen) { - saddr /= 4; + start_address /= 4; while (ed64_bios_usb_read_busy() != 0); ed64_bios_reg_write(REG_DMA_LENGTH, slen - 1); - ed64_bios_reg_write(REG_DMA_RAM_ADDR, saddr); + ed64_bios_reg_write(REG_DMA_RAM_ADDR, start_address); ed64_bios_reg_write(REG_DMA_CFG, DCFG_USB_TO_RAM); if (ed64_bios_dma_busy() != 0)return USB_ERROR_FIFO_TIMEOUT; @@ -251,13 +251,13 @@ uint8_t ed64_bios_usb_read(uint32_t saddr, uint32_t slen) { } /* USB write */ -uint8_t ed64_bios_usb_write(uint32_t saddr, uint32_t slen) { +uint8_t ed64_bios_usb_write(uint32_t start_address, uint32_t slen) { - saddr /= 4; + start_address /= 4; while (ed64_bios_usb_write_busy() != 0); ed64_bios_reg_write(REG_DMA_LENGTH, slen - 1); - ed64_bios_reg_write(REG_DMA_RAM_ADDR, saddr); + ed64_bios_reg_write(REG_DMA_RAM_ADDR, start_address); ed64_bios_reg_write(REG_DMA_CFG, DCFG_RAM_TO_USB); if (ed64_bios_dma_busy() != 0)return USB_ERROR_FIFO_TIMEOUT; @@ -300,12 +300,12 @@ void ed64_bios_sd_mode(uint16_t mode) { ed64_bios_reg_write(REG_SPI_CFG, spi_cfg); } -uint8_t ed64_bios_spi_read_to_rom(uint32_t saddr, uint16_t slen) { +uint8_t ed64_bios_spi_read_to_rom(uint32_t start_address, uint16_t slen) { - saddr /= 4; + start_address /= 4; ed64_bios_reg_write(REG_DMA_LENGTH, slen - 1); - ed64_bios_reg_write(REG_DMA_RAM_ADDR, saddr); + ed64_bios_reg_write(REG_DMA_RAM_ADDR, start_address); ed64_bios_reg_write(REG_DMA_CFG, DCFG_SD_TO_RAM); if (ed64_bios_dma_busy() != 0)return EVD_ERROR_MMC_TIMEOUT; @@ -386,28 +386,28 @@ void ed64_bios_set_ram_bank(uint8_t bank) { } -void ed64_bios_read_bios(void *dst, uint16_t saddr, uint16_t slen) { +void ed64_bios_read_bios(void *dst, uint16_t start_address, uint16_t slen) { uint16_t cfg = ed64_bios_reg_read(REG_CFG); cfg &= ~ED_CFG_SDRAM_ON; ed64_bios_reg_write(REG_CFG, cfg); - ed64_bios_dma_read_rom(dst, saddr, slen); + ed64_bios_dma_read_rom(dst, start_address, slen); cfg |= ED_CFG_SDRAM_ON; ed64_bios_reg_write(REG_CFG, cfg); } -void ed64_bios_dma_read_rom(void *ram, uint32_t saddr, uint32_t slen) { +void ed64_bios_dma_read_rom(void *ram, uint32_t start_address, uint32_t slen) { - ed64_bios_dma_read(ram, ROM_ADDR + saddr * 512, slen * 512); + ed64_bios_dma_read(ram, ROM_ADDR + start_address * 512, slen * 512); } -void ed64_bios_dma_write_rom(void *ram, uint32_t saddr, uint32_t slen) { +void ed64_bios_dma_write_rom(void *ram, uint32_t start_address, uint32_t slen) { - ed64_bios_dma_write(ram, ROM_ADDR + saddr * 512, slen * 512); + ed64_bios_dma_write(ram, ROM_ADDR + start_address * 512, slen * 512); } void ed64_bios_dma_read_sram(void *ram, uint32_t addr, uint32_t len) { diff --git a/src/flashcart/ed64/ed64_internal.h b/src/flashcart/ed64/ed64_internal.h index 7c6a94ec..c943dc31 100644 --- a/src/flashcart/ed64/ed64_internal.h +++ b/src/flashcart/ed64/ed64_internal.h @@ -96,8 +96,8 @@ void ed64_bios_load_firmware(uint8_t *firmware); /* USB functions */ uint8_t ed64_bios_usb_read_busy(); -uint8_t ed64_bios_usb_read(uint32_t saddr, uint32_t slen); -uint8_t ed64_bios_usb_write(uint32_t saddr, uint32_t slen); +uint8_t ed64_bios_usb_read(uint32_t start_address, uint32_t slen); +uint8_t ed64_bios_usb_write(uint32_t start_address, uint32_t slen); /* SPI functions */ uint8_t ed64_bios_spi(uint8_t data); @@ -106,7 +106,7 @@ void ed64_bios_set_spi_speed(uint16_t speed); /* SD Card functions */ void ed64_bios_sd_mode(uint16_t mode); -uint8_t ed64_bios_spi_read_to_rom(uint32_t saddr, uint16_t slen); +uint8_t ed64_bios_spi_read_to_rom(uint32_t start_address, uint16_t slen); void ed64_bios_byteswap_on(); void ed64_bios_byteswap_off(); @@ -114,13 +114,13 @@ void ed64_bios_byteswap_off(); uint8_t ed64_bios_get_save_type(); void ed64_bios_set_save_type(uint8_t type); -void ed64_bios_read_bios(void *dst, uint16_t saddr, uint16_t slen); +void ed64_bios_read_bios(void *dst, uint16_t start_address, uint16_t slen); uint16_t ed64_bios_msg_rd(); void ed64_bios_msg_wr(uint16_t val); -void ed64_bios_dma_read_rom(void *ram, uint32_t saddr, uint32_t slen); -void ed64_bios_dma_write_rom(void *ram, uint32_t saddr, uint32_t slen); +void ed64_bios_dma_read_rom(void *ram, uint32_t start_address, uint32_t slen); +void ed64_bios_dma_write_rom(void *ram, uint32_t start_address, uint32_t slen); void ed64_bios_dma_read_sram(void *ram, uint32_t addr, uint32_t len); void ed64_bios_dma_write_sram(void *ram, uint32_t addr, uint32_t len); From 9689e92095248f5e7e2b51bd1282f5b9a1a61648 Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Wed, 19 Jul 2023 13:26:20 +0100 Subject: [PATCH 15/64] Name and comment improvements --- src/flashcart/ed64/ed64.h | 23 +++++++ src/flashcart/ed64/ed64_internal.c | 102 ++++++++++++++++------------- src/flashcart/ed64/ed64_internal.h | 7 +- 3 files changed, 83 insertions(+), 49 deletions(-) create mode 100644 src/flashcart/ed64/ed64.h diff --git a/src/flashcart/ed64/ed64.h b/src/flashcart/ed64/ed64.h new file mode 100644 index 00000000..916dd1db --- /dev/null +++ b/src/flashcart/ed64/ed64.h @@ -0,0 +1,23 @@ +/** + * @file flashcart.h + * @brief ED64 Flashcart Utilities + * @ingroup flashcart + */ + +#ifndef FLASHCART_ED64_H__ +#define FLASHCART_ED64_H__ + + +#include "../flashcart.h" + +/** + * @addtogroup ed64 + * @{ + */ + + +flashcart_t *ed64_get_flashcart (void); + +/** @} */ /* ed64 */ + +#endif diff --git a/src/flashcart/ed64/ed64_internal.c b/src/flashcart/ed64/ed64_internal.c index d9c58b61..9c923894 100644 --- a/src/flashcart/ed64/ed64_internal.c +++ b/src/flashcart/ed64/ed64_internal.c @@ -8,7 +8,7 @@ #define ED64_KEY_UNLOCK 0x1234 /* ED64 registers base address */ -#define REGS_BASE 0xA8040000 +#define ED64_REGS_BASE (0xA8040000) typedef enum { REG_CFG = 0, @@ -21,8 +21,8 @@ typedef enum { REG_SPI_CFG = 7, REG_KEY = 8, REG_SAV_CFG = 9, - REG_SEC = 10, - REG_FPGA_VER = 11, + REG_SEC = 10, /* Sectors?? */ + REG_FPGA_VERSION = 11, /* Altera (Intel) MAX */ REG_GPIO = 12, } ed64_registers_t; @@ -36,20 +36,26 @@ typedef enum { REG_FLASHRAM_ADDR = 20, REG_FLASHRAM_DATA = 21, -} ed64_register_values_t; +} ed64_register_args_t; -#define STATE_DMA_BUSY 1 -#define STATE_DMA_TOUT 2 -#define STATE_USB_TXE 4 -#define STATE_USB_RXF 8 -#define STATE_SPI 16 +typedef enum { + STATE_DMA_BUSY = 1, + STATE_DMA_TOUT = 2, + STATE_USB_TXE = 4, + STATE_USB_RXF = 8, + STATE_SPI = 16, + +} ed64_dma_state_t; + + +typedef enum { + DCFG_SD_TO_RAM = 1, + DCFG_RAM_TO_SD = 2, + DCFG_USB_TO_RAM = 3, + DCFG_RAM_TO_USB = 4, -// Default config? -#define DCFG_SD_TO_RAM 1 -#define DCFG_RAM_TO_SD 2 -#define DCFG_USB_TO_RAM 3 -#define DCFG_RAM_TO_USB 4 +} ed64_disk_mode_t; #define SAV_EEP_ON 1 @@ -72,20 +78,20 @@ typedef enum { } ed64_config_t; -// #define FPGA_FW_DATA_SKIP_FW_INIT (1 << 8) -// #define FPGA_FW_DATA_SKIP_TV_INIT (1 << 9) -// #define FPGA_FW_DATA_TV_TYPE1 (1 << 10) -// #define FPGA_FW_DATA_TV_TYPE2 (1 << 11) -// #define FPGA_FW_DATA_SKIP_SD_INIT (1 << 12) -// #define FPGA_FW_DATA_SD_TYPE (1 << 13) +#define FPGA_FW_DATA_SKIP_FW_INIT (1 << 8) +#define FPGA_FW_DATA_SKIP_TV_INIT (1 << 9) +#define FPGA_FW_DATA_TV_TYPE1 (1 << 10) +#define FPGA_FW_DATA_TV_TYPE2 (1 << 11) +#define FPGA_FW_DATA_SKIP_SD_INIT (1 << 12) +#define FPGA_FW_DATA_SD_TYPE (1 << 13) #define FPGA_FW_DATA_HOT_START (1 << 14) uint32_t ed64_bios_reg_read(uint32_t reg); void ed64_bios_reg_write(uint32_t reg, uint32_t data); void ed64_bios_dma_r(void * ram_address, unsigned long pi_address, unsigned long len); void ed64_bios_dma_w(void * ram_address, unsigned long pi_address, unsigned long len); -void ed64_bios_dma_read(void *ram, uint32_t addr, uint32_t len); -void ed64_bios_dma_write(void *ram, uint32_t addr, uint32_t len); +void ed64_bios_dma_read(void *ram, uint32_t address, uint32_t length); +void ed64_bios_dma_write(void *ram, uint32_t address, uint32_t length); static uint16_t spi_cfg; uint8_t ed64_bios_ram_bank; @@ -100,17 +106,17 @@ uint8_t ed64_bios_save_type; /* register functions (dependent on flashcart version) */ /* register functions for V2 & V2.5 */ -void ed64_bios_io_reg_v2(uint32_t addr, uint32_t dat) { +void ed64_bios_io_reg_v2(uint32_t address, uint32_t data) { - *(volatile uint32_t *) (ROM_ADDR); - *(volatile uint32_t *) (ROM_ADDR + addr) = dat; + *(volatile uint32_t *) (ROM_ADDRESS); + *(volatile uint32_t *) (ROM_ADDRESS + address) = data; } /* register functions for V3 */ -void ed64_bios_io_reg_v3(uint32_t addr, uint16_t dat) { +void ed64_bios_io_reg_v3(uint32_t address, uint16_t data) { - ed64_bios_reg_write(REG_FLASHRAM_ADDR, addr); - ed64_bios_reg_write(REG_FLASHRAM_DATA, dat); + ed64_bios_reg_write(REG_FLASHRAM_ADDR, address); + ed64_bios_reg_write(REG_FLASHRAM_DATA, data); } /* initialize functions (dependent on flashcart version) */ @@ -202,18 +208,19 @@ void ed64_bios_reset_spx() { uint32_t ed64_bios_reg_read(uint32_t reg) { - *(volatile uint32_t *) (REGS_BASE); - return *(volatile uint32_t *) (REGS_BASE + reg * 4); + *(volatile uint32_t *) (ED64_REGS_BASE); + return *(volatile uint32_t *) (ED64_REGS_BASE + reg * 4); } void ed64_bios_reg_write(uint32_t reg, uint32_t data) { - *(volatile uint32_t *) (REGS_BASE); - *(volatile uint32_t *) (REGS_BASE + reg * 4) = data; - *(volatile uint32_t *) (ROM_ADDR); + *(volatile uint32_t *) (ED64_REGS_BASE); + *(volatile uint32_t *) (ED64_REGS_BASE + reg * 4) = data; + *(volatile uint32_t *) (ROM_ADDRESS); } +/* Used for USB and SPI functions */ uint8_t ed64_bios_dma_busy() { while ((ed64_bios_reg_read(REG_STATUS) & STATE_DMA_BUSY) != 0); @@ -401,15 +408,16 @@ void ed64_bios_read_bios(void *dst, uint16_t start_address, uint16_t slen) { void ed64_bios_dma_read_rom(void *ram, uint32_t start_address, uint32_t slen) { - ed64_bios_dma_read(ram, ROM_ADDR + start_address * 512, slen * 512); + ed64_bios_dma_read(ram, ROM_ADDRESS + start_address * 512, slen * 512); } void ed64_bios_dma_write_rom(void *ram, uint32_t start_address, uint32_t slen) { - ed64_bios_dma_write(ram, ROM_ADDR + start_address * 512, slen * 512); + ed64_bios_dma_write(ram, ROM_ADDRESS + start_address * 512, slen * 512); } +/* Read from SRAM over DMA */ void ed64_bios_dma_read_sram(void *ram, uint32_t addr, uint32_t len) { volatile uint32_t piLatReg = IO_READ(PI_BSD_DOM2_LAT_REG); @@ -422,7 +430,7 @@ void ed64_bios_dma_read_sram(void *ram, uint32_t addr, uint32_t len) { IO_WRITE(PI_BSD_DOM2_LAT_REG, 0x05); IO_WRITE(PI_BSD_DOM2_PWD_REG, 0x0C); - ed64_bios_dma_read(ram, SRAM_ADDR + addr, len); + ed64_bios_dma_read(ram, SRAM_FLASHRAM_ADDRESS + addr, len); IO_WRITE(PI_BSD_DOM2_LAT_REG, piLatReg); IO_WRITE(PI_BSD_DOM2_PWD_REG, piPwdReg); @@ -430,6 +438,7 @@ void ed64_bios_dma_read_sram(void *ram, uint32_t addr, uint32_t len) { IO_WRITE(PI_BSD_DOM2_RLS_REG, piRlsReg); } +/* Write to SRAM over DMA */ void ed64_bios_dma_write_sram(void *ram, uint32_t addr, uint32_t len) { volatile uint32_t piLatReg = IO_READ(PI_BSD_DOM2_LAT_REG); @@ -442,7 +451,7 @@ void ed64_bios_dma_write_sram(void *ram, uint32_t addr, uint32_t len) { IO_WRITE(PI_BSD_DOM2_LAT_REG, 0x05); IO_WRITE(PI_BSD_DOM2_PWD_REG, 0x0C); - ed64_bios_dma_write(ram, SRAM_ADDR + addr, len); + ed64_bios_dma_write(ram, SRAM_FLASHRAM_ADDRESS + addr, len); IO_WRITE(PI_BSD_DOM2_LAT_REG, piLatReg); @@ -505,7 +514,7 @@ void ed64_bios_dma_w(void * ram_address, unsigned long pi_address, unsigned long enable_interrupts(); } -void ed64_bios_dma_read(void *ram, uint32_t addr, uint32_t len) { +void ed64_bios_dma_read(void *ram, uint32_t address, uint32_t length) { if (((uint32_t) ram & 0xF0000000) == 0x80000000) { @@ -517,7 +526,7 @@ void ed64_bios_dma_read(void *ram, uint32_t addr, uint32_t len) { } -void ed64_bios_dma_write(void *ram, uint32_t addr, uint32_t len) { +void ed64_bios_dma_write(void *ram, uint32_t address, uint32_t length) { if (((uint32_t) ram & 0xF0000000) == 0x80000000)data_cache_hit_writeback(ram, len); ed64_bios_dma_w(ram, addr, len); @@ -526,7 +535,7 @@ void ed64_bios_dma_write(void *ram, uint32_t addr, uint32_t len) { /** @brief Get the current FPGA version */ uint16_t ed64_bios_get_fpga_version() { - return ed64_bios_reg_read(REG_FPGA_VER); + return ed64_bios_reg_read(REG_FPGA_VERSION); } /** @brief Get the current CPLD version */ @@ -542,6 +551,7 @@ uint16_t ed64_bios_get_cpld_version() { return cpld_version; } +/* Load the specified FPGA firmware */ void ed64_bios_load_firmware(uint8_t *firmware) { uint32_t i; @@ -590,7 +600,7 @@ void ed64_bios_unlock_regs() { /* GPIO functions */ -/* GPIO mode RTC */ +/* Set GPIO mode RTC */ void ed64_bios_gpio_mode_rtc() { uint16_t cfg = ed64_bios_reg_read(REG_CFG); @@ -599,7 +609,7 @@ void ed64_bios_gpio_mode_rtc() { ed64_bios_reg_write(REG_CFG, cfg); } -/* GPIO mode ON */ +/* Set GPIO mode ON */ void ed64_bios_gpio_mode_io() { uint16_t cfg = ed64_bios_reg_read(REG_CFG); @@ -607,7 +617,7 @@ void ed64_bios_gpio_mode_io() { ed64_bios_reg_write(REG_CFG, cfg); } -/* GPIO mode OFF */ +/* Set GPIO mode OFF */ void ed64_bios_gpio_off() { uint16_t cfg = ed64_bios_reg_read(REG_CFG); @@ -631,7 +641,7 @@ uint8_t ed64_bios_gpio_read() { /* 64DD functions */ -/* 64DD ON and Enabled?! */ +/* Set 64DD ON and Enabled?! */ void ed64_bios_64dd_ram_oe() { uint16_t cfg = ed64_bios_reg_read(REG_CFG); @@ -640,7 +650,7 @@ void ed64_bios_64dd_ram_oe() { ed64_bios_reg_write(REG_CFG, cfg); } -/* 64DD Write Enable?? */ +/* Set 64DD Write Enable?? */ void ed64_bios_64dd_ram_we() { uint16_t cfg = ed64_bios_reg_read(REG_CFG); @@ -648,7 +658,7 @@ void ed64_bios_64dd_ram_we() { ed64_bios_reg_write(REG_CFG, cfg); } -/* 64DD Disabled?? */ +/* Set 64DD Disabled?? */ void ed64_bios_64dd_ram_off() { uint16_t cfg = ed64_bios_reg_read(REG_CFG); diff --git a/src/flashcart/ed64/ed64_internal.h b/src/flashcart/ed64/ed64_internal.h index c943dc31..51f1aea6 100644 --- a/src/flashcart/ed64/ed64_internal.h +++ b/src/flashcart/ed64/ed64_internal.h @@ -28,8 +28,9 @@ typedef enum { SAVE_TYPE_DD64 = 16, } ed64_save_type_t; -#define ROM_ADDR 0xB0000000 -#define SRAM_ADDR 0xA8000000 + +#define SRAM_FLASHRAM_ADDRESS (0xA8000000) +#define ROM_ADDRESS (0xB0000000) #define USB_ERROR_FIFO_TIMEOUT 0x90 #define EVD_ERROR_MMC_TIMEOUT 0x91 @@ -40,7 +41,7 @@ typedef enum { // #define BOOT_UPD_ERR_CIC_DTCT 0x98 -#define PI_BASE_REG 0x04600000 +#define PI_BASE_REG (0x04600000) #define PI_STATUS_REG (PI_BASE_REG+0x10) #define PI_BSD_DOM1_LAT_REG (PI_BASE_REG+0x14) From 64e761dc09667b1a01a53535656166f7b20565a9 Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Wed, 19 Jul 2023 14:36:23 +0100 Subject: [PATCH 16/64] Improvements to function names --- src/flashcart/ed64/ed64_internal.c | 37 +++++++++++++++--------------- src/flashcart/ed64/ed64_internal.h | 18 +++++++-------- src/flashcart/flashcart.c | 3 +++ 3 files changed, 30 insertions(+), 28 deletions(-) diff --git a/src/flashcart/ed64/ed64_internal.c b/src/flashcart/ed64/ed64_internal.c index 9c923894..d3f22f7e 100644 --- a/src/flashcart/ed64/ed64_internal.c +++ b/src/flashcart/ed64/ed64_internal.c @@ -88,8 +88,8 @@ typedef enum { uint32_t ed64_bios_reg_read(uint32_t reg); void ed64_bios_reg_write(uint32_t reg, uint32_t data); -void ed64_bios_dma_r(void * ram_address, unsigned long pi_address, unsigned long len); -void ed64_bios_dma_w(void * ram_address, unsigned long pi_address, unsigned long len); +void ed64_bios_dma_pi_read(void * ram_address, unsigned long pi_address, unsigned long length); +void ed64_bios_dma_pi_write(void * ram_address, unsigned long pi_address, unsigned long length); void ed64_bios_dma_read(void *ram, uint32_t address, uint32_t length); void ed64_bios_dma_write(void *ram, uint32_t address, uint32_t length); @@ -105,7 +105,8 @@ uint8_t ed64_bios_save_type; /* register functions (dependent on flashcart version) */ -/* register functions for V2 & V2.5 */ +/* register functions for V2 & V2.5 (These carts do not support FLASHRAM)*/ +/* The end of SDRAM is used for SRAM or FlashRAM save types */ void ed64_bios_io_reg_v2(uint32_t address, uint32_t data) { *(volatile uint32_t *) (ROM_ADDRESS); @@ -287,6 +288,7 @@ uint8_t ed64_bios_spi(uint8_t data) { return ed64_bios_reg_read(REG_SPI); } +/* never returns (or is it never reads???) */ void ed64_bios_spi_nr(uint8_t data) { ed64_bios_reg_write(REG_SPI, data); @@ -418,7 +420,7 @@ void ed64_bios_dma_write_rom(void *ram, uint32_t start_address, uint32_t slen) { } /* Read from SRAM over DMA */ -void ed64_bios_dma_read_sram(void *ram, uint32_t addr, uint32_t len) { +void ed64_bios_dma_read_sram(void *ram, uint32_t address, uint32_t length) { volatile uint32_t piLatReg = IO_READ(PI_BSD_DOM2_LAT_REG); volatile uint32_t piPwdReg = IO_READ(PI_BSD_DOM2_PWD_REG); @@ -430,7 +432,7 @@ void ed64_bios_dma_read_sram(void *ram, uint32_t addr, uint32_t len) { IO_WRITE(PI_BSD_DOM2_LAT_REG, 0x05); IO_WRITE(PI_BSD_DOM2_PWD_REG, 0x0C); - ed64_bios_dma_read(ram, SRAM_FLASHRAM_ADDRESS + addr, len); + ed64_bios_dma_read(ram, SRAM_FLASHRAM_ADDRESS + address, length); IO_WRITE(PI_BSD_DOM2_LAT_REG, piLatReg); IO_WRITE(PI_BSD_DOM2_PWD_REG, piPwdReg); @@ -439,7 +441,7 @@ void ed64_bios_dma_read_sram(void *ram, uint32_t addr, uint32_t len) { } /* Write to SRAM over DMA */ -void ed64_bios_dma_write_sram(void *ram, uint32_t addr, uint32_t len) { +void ed64_bios_dma_write_sram(void *ram, uint32_t address, uint32_t length) { volatile uint32_t piLatReg = IO_READ(PI_BSD_DOM2_LAT_REG); volatile uint32_t piPwdReg = IO_READ(PI_BSD_DOM2_PWD_REG); @@ -451,7 +453,7 @@ void ed64_bios_dma_write_sram(void *ram, uint32_t addr, uint32_t len) { IO_WRITE(PI_BSD_DOM2_LAT_REG, 0x05); IO_WRITE(PI_BSD_DOM2_PWD_REG, 0x0C); - ed64_bios_dma_write(ram, SRAM_FLASHRAM_ADDRESS + addr, len); + ed64_bios_dma_write(ram, SRAM_FLASHRAM_ADDRESS + address, length); IO_WRITE(PI_BSD_DOM2_LAT_REG, piLatReg); @@ -486,30 +488,27 @@ typedef struct PI_regs_s { static volatile struct PI_regs_s * const PI_regs = (struct PI_regs_s *) PI_BASE_REG; -void ed64_bios_dma_r(void * ram_address, unsigned long pi_address, unsigned long len) { - +void ed64_bios_dma_pi_read(void * ram_address, unsigned long pi_address, unsigned long length) { disable_interrupts(); - dma_wait(); IO_WRITE(PI_STATUS_REG, 3); PI_regs->ram_address = ram_address; PI_regs->pi_address = pi_address & 0x1FFFFFFF; - PI_regs->write_length = len - 1; + PI_regs->write_length = length - 1; dma_wait(); enable_interrupts(); } -void ed64_bios_dma_w(void * ram_address, unsigned long pi_address, unsigned long len) { - +void ed64_bios_dma_pi_write(void * ram_address, unsigned long pi_address, unsigned long length) { disable_interrupts(); dma_wait(); IO_WRITE(PI_STATUS_REG, 3); PI_regs->ram_address = ram_address; PI_regs->pi_address = pi_address & 0x1FFFFFFF; - PI_regs->read_length = len - 1; + PI_regs->read_length = length - 1; dma_wait(); enable_interrupts(); } @@ -518,18 +517,18 @@ void ed64_bios_dma_read(void *ram, uint32_t address, uint32_t length) { if (((uint32_t) ram & 0xF0000000) == 0x80000000) { - data_cache_hit_writeback_invalidate(ram, len); - ed64_bios_dma_r(ram, addr, len); + data_cache_hit_writeback_invalidate(ram, length); + ed64_bios_dma_pi_read(ram, address, length); } else { - ed64_bios_dma_r(ram, addr, len); + ed64_bios_dma_pi_read(ram, address, length); } } void ed64_bios_dma_write(void *ram, uint32_t address, uint32_t length) { - if (((uint32_t) ram & 0xF0000000) == 0x80000000)data_cache_hit_writeback(ram, len); - ed64_bios_dma_w(ram, addr, len); + if (((uint32_t) ram & 0xF0000000) == 0x80000000)data_cache_hit_writeback(ram, length); + ed64_bios_dma_pi_write(ram, address, length); } /** @brief Get the current FPGA version */ diff --git a/src/flashcart/ed64/ed64_internal.h b/src/flashcart/ed64/ed64_internal.h index 51f1aea6..cb8eccaa 100644 --- a/src/flashcart/ed64/ed64_internal.h +++ b/src/flashcart/ed64/ed64_internal.h @@ -35,10 +35,10 @@ typedef enum { #define USB_ERROR_FIFO_TIMEOUT 0x90 #define EVD_ERROR_MMC_TIMEOUT 0x91 -// #define BOOT_UPD_ERR_WRONG_SIZE 0x95 -// #define BOOT_UPD_ERR_HDR 0x96 -// #define BOOT_UPD_ERR_CMP 0x97 -// #define BOOT_UPD_ERR_CIC_DTCT 0x98 +#define BOOT_UPD_ERR_WRONG_SIZE 0x95 +#define BOOT_UPD_ERR_HDR 0x96 +#define BOOT_UPD_ERR_CMP 0x97 +#define BOOT_UPD_ERR_CIC_DTCT 0x98 #define PI_BASE_REG (0x04600000) @@ -76,8 +76,8 @@ typedef enum { BI_SPI_SPD_LO = 2, } ed64_spi_speed_t; -// #define SPI_CFG_SPD0 1 -// #define SPI_CFG_SPD1 2 +#define SPI_CFG_SPD0 1 +#define SPI_CFG_SPD1 2 #define SPI_CFG_SS 4 #define SPI_CFG_RD 8 #define SPI_CFG_DAT 16 @@ -119,11 +119,11 @@ void ed64_bios_read_bios(void *dst, uint16_t start_address, uint16_t slen); uint16_t ed64_bios_msg_rd(); void ed64_bios_msg_wr(uint16_t val); - +/* DMA functions */ void ed64_bios_dma_read_rom(void *ram, uint32_t start_address, uint32_t slen); void ed64_bios_dma_write_rom(void *ram, uint32_t start_address, uint32_t slen); -void ed64_bios_dma_read_sram(void *ram, uint32_t addr, uint32_t len); -void ed64_bios_dma_write_sram(void *ram, uint32_t addr, uint32_t len); +void ed64_bios_dma_read_sram(void *ram, uint32_t address, uint32_t length); +void ed64_bios_dma_write_sram(void *ram, uint32_t address, uint32_t length); void ed64_bios_lock_regs(); void ed64_bios_unlock_regs(); diff --git a/src/flashcart/flashcart.c b/src/flashcart/flashcart.c index a8635059..c163ad90 100644 --- a/src/flashcart/flashcart.c +++ b/src/flashcart/flashcart.c @@ -46,7 +46,10 @@ flashcart_error_t flashcart_init (void) { switch (usb_getcart()) { case CART_64DRIVE: + break; + case CART_EVERDRIVE: + // flashcart = ed64_get_flashcart(); break; case CART_SC64: From 45e9a3d2e031675ea925fce31d8f4660281f1da7 Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Wed, 19 Jul 2023 15:35:08 +0100 Subject: [PATCH 17/64] Add ED64.c base implementation --- Makefile | 1 + src/flashcart/ed64/README.md | 2 + src/flashcart/ed64/ed64.c | 326 +++++++++++++++++++++++++++++++++++ src/flashcart/flashcart.c | 3 +- 4 files changed, 331 insertions(+), 1 deletion(-) create mode 100644 src/flashcart/ed64/ed64.c diff --git a/Makefile b/Makefile index 3929e6e5..8a66d816 100644 --- a/Makefile +++ b/Makefile @@ -21,6 +21,7 @@ SRCS = \ flashcart/sc64/sc64_internal.c \ flashcart/ed64/ed64_internal.c \ flashcart/sc64/sc64.c \ + flashcart/ed64/ed64.c \ libs/mini.c/src/mini.c \ menu/actions.c \ menu/assets.c \ diff --git a/src/flashcart/ed64/README.md b/src/flashcart/ed64/README.md index c3bcefce..ca5bc2f5 100644 --- a/src/flashcart/ed64/README.md +++ b/src/flashcart/ed64/README.md @@ -8,4 +8,6 @@ It may require further cleansing and updating to use the latest libdragon before Initially, this aims to work when loading the ED64 menu, selecting the N64FlashcartMenu and then loading a ROM from there. This works around needing to load the correct firmware. To automate this, it is possible to set the menu to autoload (at least in the unofficial menu). +Notes: libcart seems to use a different base register address (0x08040000), but official implementation uses 0xA8040000 + diff --git a/src/flashcart/ed64/ed64.c b/src/flashcart/ed64/ed64.c new file mode 100644 index 00000000..091b861a --- /dev/null +++ b/src/flashcart/ed64/ed64.c @@ -0,0 +1,326 @@ +#include +#include +#include + +#include +#include + +#include "utils/fs.h" +#include "utils/utils.h" + +#include "ed64_internal.h" +#include "ed64.h" + + +// #define SRAM_FLASHRAM_ADDRESS (0x08000000) +// #define ROM_ADDRESS (0x10000000) +// #define EXTENDED_ADDRESS (0x14000000) +// #define SHADOW_ADDRESS (0x1FFC0000) +// #define EEPROM_ADDRESS (0x1FFE2000) + +// #define SUPPORTED_MAJOR_VERSION (2) +// #define SUPPORTED_MINOR_VERSION (12) + + +// static flashcart_error_t load_to_flash (FIL *fil, void *address, size_t size, UINT *br) { + // size_t erase_block_size; + // UINT bp; + + // *br = 0; + + // if (ed64_flash_get_erase_block_size(&erase_block_size) != ED64_OK) { + // return FLASHCART_ERROR_INT; + // } + + // while (size > 0) { + // size_t program_size = MIN(size, erase_block_size); + // if (ed64_flash_erase_block(address) != ED64_OK) { + // return FLASHCART_ERROR_INT; + // } + // if (f_read(fil, address, program_size, &bp) != FR_OK) { + // return FLASHCART_ERROR_LOAD; + // } + // if (ed64_flash_wait_busy() != ED64_OK) { + // return FLASHCART_ERROR_INT; + // } + // address += program_size; + // size -= program_size; + // *br += bp; + // } + +// return FLASHCART_OK; +// } + +// static void load_cleanup (FIL *fil) { +// // ed64_sd_set_byte_swap(false); +// f_close(fil); +// } + + +static flashcart_error_t ed64_init (void) { + // uint16_t major; + // uint16_t minor; + + // HACK: Because libcart reads PI config from address 0x10000000 when initializing + // we need to write safe value before running any libcart function. + // Data in SDRAM can be undefined at this point and result in setting incorrect PI config. + // extern uint32_t cart_dom1; + // cart_dom1 = 0x80371240; + + // ed64_bios_unlock_regs(); + + ed64_bios_init(); + + // if (!ed64_check_presence()) { + // return FLASHCART_ERROR_UNSUPPORTED; + // } + // if (ed64_get_version(&major, &minor) != ED64_OK) { + // return FLASHCART_ERROR_OUTDATED; + // } + // if (major != SUPPORTED_MAJOR_VERSION) { + // return FLASHCART_ERROR_OUTDATED; + // } + // if (minor < SUPPORTED_MINOR_VERSION) { + // return FLASHCART_ERROR_OUTDATED; + // } + + // bool writeback_pending; + // do { + // if (ed64_writeback_pending(&writeback_pending) != ED64_OK) { + // return FLASHCART_ERROR_INT; + // } + // } while (writeback_pending); + + // const struct { + // ed64_cfg_t id; + // uint32_t value; + // } default_config[] = { + // { CFG_BOOTLOADER_SWITCH, false }, + // { CFG_ROM_WRITE_ENABLE, false }, + // { CFG_ROM_SHADOW_ENABLE, false }, + // { CFG_DD_MODE, DD_MODE_DISABLED }, + // { CFG_ISV_ADDRESS, 0x00000000 }, + // { CFG_BOOT_MODE, BOOT_MODE_MENU }, + // { CFG_SAVE_TYPE, SAVE_TYPE_NONE }, + // { CFG_CIC_SEED, CIC_SEED_AUTO }, + // { CFG_TV_TYPE, TV_TYPE_PASSTHROUGH }, + // { CFG_DD_SD_ENABLE, false }, + // { CFG_DD_DRIVE_TYPE, DRIVE_TYPE_RETAIL }, + // { CFG_DD_DISK_STATE, DISK_STATE_EJECTED }, + // { CFG_BUTTON_MODE, BUTTON_MODE_NONE }, + // { CFG_ROM_EXTENDED_ENABLE, false }, + // }; + + // for (int i = 0; i < sizeof(default_config) / sizeof(default_config[0]); i++) { + // if (ed64_set_config(default_config[i].id, default_config[i].value) != ED64_OK) { + // return FLASHCART_ERROR_INT; + // } + // } + + return FLASHCART_OK; +} + +static flashcart_error_t ed64_deinit (void) { + // // NOTE: Necessary because libcart enables ROM write by default + // ed64_set_config(CFG_ROM_WRITE_ENABLE, false); + + ed64_bios_lock_regs(); + + return FLASHCART_OK; +} + +static flashcart_error_t ed64_load_rom (char *rom_path, bool byte_swap) { + FIL fil; + // UINT br; + + if (f_open(&fil, rom_path, FA_READ) != FR_OK) { + return FLASHCART_ERROR_LOAD; + } + + // HACK: Align file size to the SD sector size to prevent FatFs from doing partial sector load. + // We are relying on direct transfer from SD to SDRAM without CPU intervention. + // Sending some extra bytes isn't an issue here. + fil.obj.objsize = ALIGN(f_size(&fil), FS_SECTOR_SIZE); + + size_t rom_size = f_size(&fil); + + if (rom_size > MiB(78)) { + f_close(&fil); + return FLASHCART_ERROR_LOAD; + } + + // if (ed64_sd_set_byte_swap(byte_swap) != ED64_OK) { + // load_cleanup(&fil); + // return FLASHCART_ERROR_INT; + // } + + // bool shadow_enabled = (rom_size > (MiB(64) - KiB(128))); + // bool extended_enabled = (rom_size > MiB(64)); + + // size_t sdram_size = shadow_enabled ? (MiB(64) - KiB(128)) : rom_size; + // size_t shadow_size = shadow_enabled ? MIN(rom_size - sdram_size, KiB(128)) : 0; + // size_t extended_size = extended_enabled ? rom_size - MiB(64) : 0; + + // if (f_read(&fil, (void *) (ROM_ADDRESS), sdram_size, &br) != FR_OK) { + // load_cleanup(&fil); + // return FLASHCART_ERROR_LOAD; + // } + // if (br != sdram_size) { + // load_cleanup(&fil); + // return FLASHCART_ERROR_LOAD; + // } + + // if (ed64_set_config(CFG_ROM_SHADOW_ENABLE, shadow_enabled) != ED64_OK) { + // load_cleanup(&fil); + // return FLASHCART_ERROR_INT; + // } + + // if (shadow_enabled) { + // flashcart_error_t error = load_to_flash(&fil, (void *) (SHADOW_ADDRESS), shadow_size, &br); + // if (error != FLASHCART_OK) { + // load_cleanup(&fil); + // return error; + // } + // if (br != shadow_size) { + // load_cleanup(&fil); + // return FLASHCART_ERROR_LOAD; + // } + // } + + // if (ed64_set_config(CFG_ROM_EXTENDED_ENABLE, extended_enabled) != ED64_OK) { + // load_cleanup(&fil); + // return FLASHCART_ERROR_INT; + // } + + // if (extended_enabled) { + // flashcart_error_t error = load_to_flash(&fil, (void *) (EXTENDED_ADDRESS), extended_size, &br); + // if (error != FLASHCART_OK) { + // load_cleanup(&fil); + // return error; + // } + // if (br != extended_size) { + // load_cleanup(&fil); + // return FLASHCART_ERROR_LOAD; + // } + // } + + // if (ed64_sd_set_byte_swap(false) != ED64_OK) { + // load_cleanup(&fil); + // return FLASHCART_ERROR_INT; + // } + + if (f_close(&fil) != FR_OK) { + return FLASHCART_ERROR_LOAD; + } + + return FLASHCART_OK; +} + +static flashcart_error_t ed64_load_save (char *save_path) { +// void *address = NULL; +// ed64_save_type_t type; + +// if (ed64_get_config(CFG_SAVE_TYPE, &type) != ED64_OK) { +// return FLASHCART_ERROR_INT; +// } + +// switch (type) { +// case SAVE_TYPE_EEPROM_4K: +// case SAVE_TYPE_EEPROM_16K: +// address = (void *) (EEPROM_ADDRESS); +// break; +// case SAVE_TYPE_SRAM: +// case SAVE_TYPE_FLASHRAM: +// case SAVE_TYPE_SRAM_BANKED: +// address = (void *) (SRAM_FLASHRAM_ADDRESS); +// break; +// case SAVE_TYPE_NONE: +// default: +// return FLASHCART_ERROR_ARGS; +// } + +// FIL fil; +// UINT br; + +// if (f_open(&fil, save_path, FA_READ) != FR_OK) { +// return FLASHCART_ERROR_LOAD; +// } + +// size_t save_size = f_size(&fil); + +// if (f_read(&fil, address, save_size, &br) != FR_OK) { +// f_close(&fil); +// return FLASHCART_ERROR_LOAD; +// } + +// if (f_close(&fil) != FR_OK) { +// return FLASHCART_ERROR_LOAD; +// } + +// if (br != save_size) { +// return FLASHCART_ERROR_LOAD; +// } + + return FLASHCART_OK; +} + +static flashcart_error_t ed64_set_save_type (flashcart_save_type_t save_type) { +// ed64_save_type_t type; + +// switch (save_type) { +// case FLASHCART_SAVE_TYPE_NONE: +// type = SAVE_TYPE_NONE; +// break; +// case FLASHCART_SAVE_TYPE_EEPROM_4K: +// type = SAVE_TYPE_EEPROM_4K; +// break; +// case FLASHCART_SAVE_TYPE_EEPROM_16K: +// type = SAVE_TYPE_EEPROM_16K; +// break; +// case FLASHCART_SAVE_TYPE_SRAM: +// type = SAVE_TYPE_SRAM; +// break; +// case FLASHCART_SAVE_TYPE_SRAM_BANKED: +// type = SAVE_TYPE_SRAM_BANKED; +// break; +// case FLASHCART_SAVE_TYPE_SRAM_128K: +// type = SAVE_TYPE_SRAM_128K; +// break; +// case FLASHCART_SAVE_TYPE_FLASHRAM: +// type = SAVE_TYPE_FLASHRAM; +// break; +// default: +// return FLASHCART_ERROR_ARGS; +// } + +// if (ed64_set_config(CFG_SAVE_TYPE, type) != ED64_OK) { +// return FLASHCART_ERROR_INT; +// } + + return FLASHCART_OK; +} + +static flashcart_error_t ed64_set_save_writeback (uint32_t *sectors) { +// ed64_write_data(sectors, ED64_BUFFERS->BUFFER, 1024); + +// if (ed64_writeback_enable(ED64_BUFFERS->BUFFER) != ED64_OK) { +// return FLASHCART_ERROR_INT; +// } + + return FLASHCART_OK; +} + + +static flashcart_t flashcart_ed64 = { + .init = ed64_init, + .deinit = ed64_deinit, + .load_rom = ed64_load_rom, + .load_save = ed64_load_save, + .set_save_type = ed64_set_save_type, + .set_save_writeback = ed64_set_save_writeback, +}; + + +flashcart_t *ed64_get_flashcart (void) { + return &flashcart_ed64; +} diff --git a/src/flashcart/flashcart.c b/src/flashcart/flashcart.c index c163ad90..ba76900b 100644 --- a/src/flashcart/flashcart.c +++ b/src/flashcart/flashcart.c @@ -8,6 +8,7 @@ #include "flashcart.h" #include "sc64/sc64.h" +#include "ed64/ed64.h" #define WRITEBACK_MAX_SECTORS (256) @@ -49,7 +50,7 @@ flashcart_error_t flashcart_init (void) { break; case CART_EVERDRIVE: - // flashcart = ed64_get_flashcart(); + flashcart = ed64_get_flashcart(); break; case CART_SC64: From cba010e2f7db0a6109f3f757229a427bd4938642 Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Wed, 19 Jul 2023 15:46:01 +0100 Subject: [PATCH 18/64] Update README.md --- src/flashcart/ed64/README.md | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/src/flashcart/ed64/README.md b/src/flashcart/ed64/README.md index ca5bc2f5..f1c3a020 100644 --- a/src/flashcart/ed64/README.md +++ b/src/flashcart/ed64/README.md @@ -1,13 +1,15 @@ This folder allows support for the ED64 "Official" flashcart when using V series hardware. For the moment it is unlikely to support clones. -It is based on OS 2.12.x as used in the "Unofficial Menu". +It is based on OS 2.12.x as used in the "Unofficial Menu" (https://github.com/n64-tools/ED64-UnofficialOS-binaries/releases/tag/V2.12.9.3-Release) It may require further cleansing and updating to use the latest libdragon before it will probably work based on the fact that using the latest libdragon with `libcart` seems to have a detremental effect on the ability to load ROM's. -Initially, this aims to work when loading the ED64 menu, selecting the N64FlashcartMenu and then loading a ROM from there. This works around needing to load the correct firmware. To automate this, it is possible to set the menu to autoload (at least in the unofficial menu). +Initially, this aims to work when loading the ED64 menu, selecting the N64FlashcartMenu and then loading a ROM from there. This works around needing to load the correct firmware. To automate this, it is possible to set the menu to autoload (at least in the unofficial menu). e.g. You can set this ROM to auto load by placing a file called `autoexec.v64` in the `ED64` folder with the content of the file pointing to the path of this ROM. -Notes: libcart seems to use a different base register address (0x08040000), but official implementation uses 0xA8040000 +Notes: + +`libcart`` seems to use a different base register address (0x08040000), but official implementation uses 0xA8040000 From 72c2574d2596f6b36ec5de980b6c6028e7b26f5f Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Wed, 19 Jul 2023 16:23:07 +0100 Subject: [PATCH 19/64] Add set save type --- src/flashcart/ed64/ed64.c | 60 ++++++++++++++++++++------------------- 1 file changed, 31 insertions(+), 29 deletions(-) diff --git a/src/flashcart/ed64/ed64.c b/src/flashcart/ed64/ed64.c index 091b861a..2d4016a4 100644 --- a/src/flashcart/ed64/ed64.c +++ b/src/flashcart/ed64/ed64.c @@ -265,37 +265,39 @@ static flashcart_error_t ed64_load_save (char *save_path) { } static flashcart_error_t ed64_set_save_type (flashcart_save_type_t save_type) { -// ed64_save_type_t type; + ed64_save_type_t type; + + switch (save_type) { + case FLASHCART_SAVE_TYPE_NONE: + type = SAVE_TYPE_OFF; + break; + case FLASHCART_SAVE_TYPE_EEPROM_4K: + type = SAVE_TYPE_EEP4k; + break; + case FLASHCART_SAVE_TYPE_EEPROM_16K: + type = SAVE_TYPE_EEP16k; + break; + case FLASHCART_SAVE_TYPE_SRAM: + type = SAVE_TYPE_SRAM; + break; + case FLASHCART_SAVE_TYPE_SRAM_BANKED: + type = SAVE_TYPE_SRAM128; + break; + case FLASHCART_SAVE_TYPE_SRAM_128K: + type = SAVE_TYPE_SRAM128; + break; + case FLASHCART_SAVE_TYPE_FLASHRAM: + type = SAVE_TYPE_FLASH; + break; + default: + return FLASHCART_ERROR_ARGS; + } -// switch (save_type) { -// case FLASHCART_SAVE_TYPE_NONE: -// type = SAVE_TYPE_NONE; -// break; -// case FLASHCART_SAVE_TYPE_EEPROM_4K: -// type = SAVE_TYPE_EEPROM_4K; -// break; -// case FLASHCART_SAVE_TYPE_EEPROM_16K: -// type = SAVE_TYPE_EEPROM_16K; -// break; -// case FLASHCART_SAVE_TYPE_SRAM: -// type = SAVE_TYPE_SRAM; -// break; -// case FLASHCART_SAVE_TYPE_SRAM_BANKED: -// type = SAVE_TYPE_SRAM_BANKED; -// break; -// case FLASHCART_SAVE_TYPE_SRAM_128K: -// type = SAVE_TYPE_SRAM_128K; -// break; -// case FLASHCART_SAVE_TYPE_FLASHRAM: -// type = SAVE_TYPE_FLASHRAM; -// break; -// default: -// return FLASHCART_ERROR_ARGS; -// } + // if (ed64_set_config(CFG_SAVE_TYPE, type) != ED64_OK) { + // return FLASHCART_ERROR_INT; + // } -// if (ed64_set_config(CFG_SAVE_TYPE, type) != ED64_OK) { -// return FLASHCART_ERROR_INT; -// } + ed64_bios_set_save_type(type); return FLASHCART_OK; } From a7520261ebcf761d4f376df25f90f5429199cf8a Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Wed, 19 Jul 2023 17:16:25 +0100 Subject: [PATCH 20/64] Save type improvements --- src/flashcart/ed64/ed64.c | 99 ++++++++++-------------------- src/flashcart/ed64/ed64_internal.c | 6 +- src/flashcart/ed64/ed64_internal.h | 4 +- 3 files changed, 36 insertions(+), 73 deletions(-) diff --git a/src/flashcart/ed64/ed64.c b/src/flashcart/ed64/ed64.c index 2d4016a4..6d15bd7b 100644 --- a/src/flashcart/ed64/ed64.c +++ b/src/flashcart/ed64/ed64.c @@ -14,9 +14,6 @@ // #define SRAM_FLASHRAM_ADDRESS (0x08000000) // #define ROM_ADDRESS (0x10000000) -// #define EXTENDED_ADDRESS (0x14000000) -// #define SHADOW_ADDRESS (0x1FFC0000) -// #define EEPROM_ADDRESS (0x1FFE2000) // #define SUPPORTED_MAJOR_VERSION (2) // #define SUPPORTED_MINOR_VERSION (12) @@ -154,12 +151,8 @@ static flashcart_error_t ed64_load_rom (char *rom_path, bool byte_swap) { // return FLASHCART_ERROR_INT; // } - // bool shadow_enabled = (rom_size > (MiB(64) - KiB(128))); - // bool extended_enabled = (rom_size > MiB(64)); - // size_t sdram_size = shadow_enabled ? (MiB(64) - KiB(128)) : rom_size; - // size_t shadow_size = shadow_enabled ? MIN(rom_size - sdram_size, KiB(128)) : 0; - // size_t extended_size = extended_enabled ? rom_size - MiB(64) : 0; + // size_t sdram_size = rom_size; // if (f_read(&fil, (void *) (ROM_ADDRESS), sdram_size, &br) != FR_OK) { // load_cleanup(&fil); @@ -170,40 +163,11 @@ static flashcart_error_t ed64_load_rom (char *rom_path, bool byte_swap) { // return FLASHCART_ERROR_LOAD; // } - // if (ed64_set_config(CFG_ROM_SHADOW_ENABLE, shadow_enabled) != ED64_OK) { - // load_cleanup(&fil); - // return FLASHCART_ERROR_INT; - // } - - // if (shadow_enabled) { - // flashcart_error_t error = load_to_flash(&fil, (void *) (SHADOW_ADDRESS), shadow_size, &br); - // if (error != FLASHCART_OK) { - // load_cleanup(&fil); - // return error; - // } - // if (br != shadow_size) { - // load_cleanup(&fil); - // return FLASHCART_ERROR_LOAD; - // } - // } - // if (ed64_set_config(CFG_ROM_EXTENDED_ENABLE, extended_enabled) != ED64_OK) { // load_cleanup(&fil); // return FLASHCART_ERROR_INT; // } - // if (extended_enabled) { - // flashcart_error_t error = load_to_flash(&fil, (void *) (EXTENDED_ADDRESS), extended_size, &br); - // if (error != FLASHCART_OK) { - // load_cleanup(&fil); - // return error; - // } - // if (br != extended_size) { - // load_cleanup(&fil); - // return FLASHCART_ERROR_LOAD; - // } - // } - // if (ed64_sd_set_byte_swap(false) != ED64_OK) { // load_cleanup(&fil); // return FLASHCART_ERROR_INT; @@ -218,26 +182,26 @@ static flashcart_error_t ed64_load_rom (char *rom_path, bool byte_swap) { static flashcart_error_t ed64_load_save (char *save_path) { // void *address = NULL; -// ed64_save_type_t type; - -// if (ed64_get_config(CFG_SAVE_TYPE, &type) != ED64_OK) { -// return FLASHCART_ERROR_INT; -// } - -// switch (type) { -// case SAVE_TYPE_EEPROM_4K: -// case SAVE_TYPE_EEPROM_16K: -// address = (void *) (EEPROM_ADDRESS); -// break; -// case SAVE_TYPE_SRAM: -// case SAVE_TYPE_FLASHRAM: -// case SAVE_TYPE_SRAM_BANKED: -// address = (void *) (SRAM_FLASHRAM_ADDRESS); -// break; -// case SAVE_TYPE_NONE: -// default: -// return FLASHCART_ERROR_ARGS; -// } +// ed64_save_type_t type = ed64_bios_get_save_type(); + +// // if (ed64_get_config(CFG_SAVE_TYPE, &type) != ED64_OK) { +// // return FLASHCART_ERROR_INT; +// // } + +// // switch (type) { +// // case SAVE_TYPE_EEPROM_4K: +// // case SAVE_TYPE_EEPROM_16K: +// // address = (void *) (EEPROM_ADDRESS); +// // break; +// // case SAVE_TYPE_SRAM: +// // case SAVE_TYPE_FLASHRAM: +// // case SAVE_TYPE_SRAM_BANKED: +// // address = (void *) (SRAM_FLASHRAM_ADDRESS); +// // break; +// // case SAVE_TYPE_NONE: +// // default: +// // return FLASHCART_ERROR_ARGS; +// // } // FIL fil; // UINT br; @@ -265,7 +229,8 @@ static flashcart_error_t ed64_load_save (char *save_path) { } static flashcart_error_t ed64_set_save_type (flashcart_save_type_t save_type) { - ed64_save_type_t type; + + ed64_save_type_t type = SAVE_TYPE_OFF; switch (save_type) { case FLASHCART_SAVE_TYPE_NONE: @@ -281,8 +246,6 @@ static flashcart_error_t ed64_set_save_type (flashcart_save_type_t save_type) { type = SAVE_TYPE_SRAM; break; case FLASHCART_SAVE_TYPE_SRAM_BANKED: - type = SAVE_TYPE_SRAM128; - break; case FLASHCART_SAVE_TYPE_SRAM_128K: type = SAVE_TYPE_SRAM128; break; @@ -302,15 +265,15 @@ static flashcart_error_t ed64_set_save_type (flashcart_save_type_t save_type) { return FLASHCART_OK; } -static flashcart_error_t ed64_set_save_writeback (uint32_t *sectors) { -// ed64_write_data(sectors, ED64_BUFFERS->BUFFER, 1024); +// static flashcart_error_t ed64_set_save_writeback (uint32_t *sectors) { +// // ed64_write_data(sectors, ED64_BUFFERS->BUFFER, 1024); -// if (ed64_writeback_enable(ED64_BUFFERS->BUFFER) != ED64_OK) { -// return FLASHCART_ERROR_INT; -// } +// // if (ed64_writeback_enable(ED64_BUFFERS->BUFFER) != ED64_OK) { +// // return FLASHCART_ERROR_INT; +// // } - return FLASHCART_OK; -} +// return FLASHCART_OK; +// } static flashcart_t flashcart_ed64 = { @@ -319,7 +282,7 @@ static flashcart_t flashcart_ed64 = { .load_rom = ed64_load_rom, .load_save = ed64_load_save, .set_save_type = ed64_set_save_type, - .set_save_writeback = ed64_set_save_writeback, + //.set_save_writeback = ed64_set_save_writeback, }; diff --git a/src/flashcart/ed64/ed64_internal.c b/src/flashcart/ed64/ed64_internal.c index d3f22f7e..b66f16ec 100644 --- a/src/flashcart/ed64/ed64_internal.c +++ b/src/flashcart/ed64/ed64_internal.c @@ -95,7 +95,7 @@ void ed64_bios_dma_write(void *ram, uint32_t address, uint32_t length); static uint16_t spi_cfg; uint8_t ed64_bios_ram_bank; -uint8_t ed64_bios_save_type; +ed64_save_type_t ed64_bios_save_type; #define REG_LAT 0x04 #define REG_PWD 0x04 @@ -334,12 +334,12 @@ void ed64_bios_byteswap_off() { ed64_bios_reg_write(REG_CFG, cfg); } -uint8_t ed64_bios_get_save_type() { +ed64_save_type_t ed64_bios_get_save_type() { return ed64_bios_save_type; } -void ed64_bios_set_save_type(uint8_t type) { +void ed64_bios_set_save_type(ed64_save_type_t type) { uint16_t save_cfg; uint8_t eeprom_on, sram_on, eeprom_size, sram_size, ram_bank; diff --git a/src/flashcart/ed64/ed64_internal.h b/src/flashcart/ed64/ed64_internal.h index cb8eccaa..67c5afae 100644 --- a/src/flashcart/ed64/ed64_internal.h +++ b/src/flashcart/ed64/ed64_internal.h @@ -112,8 +112,8 @@ void ed64_bios_byteswap_on(); void ed64_bios_byteswap_off(); /* Save functions */ -uint8_t ed64_bios_get_save_type(); -void ed64_bios_set_save_type(uint8_t type); +ed64_save_type_t ed64_bios_get_save_type(); +void ed64_bios_set_save_type(ed64_save_type_t type); void ed64_bios_read_bios(void *dst, uint16_t start_address, uint16_t slen); uint16_t ed64_bios_msg_rd(); From c408198a295a9d11007277d3898c582bd38fe79a Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Wed, 19 Jul 2023 17:44:23 +0100 Subject: [PATCH 21/64] Re-enable save writeback It is required by flashcart.c --- src/flashcart/ed64/ed64.c | 16 ++++++++-------- src/flashcart/ed64/ed64_internal.c | 2 +- src/flashcart/ed64/ed64_internal.h | 2 +- 3 files changed, 10 insertions(+), 10 deletions(-) diff --git a/src/flashcart/ed64/ed64.c b/src/flashcart/ed64/ed64.c index 6d15bd7b..be7430bc 100644 --- a/src/flashcart/ed64/ed64.c +++ b/src/flashcart/ed64/ed64.c @@ -265,15 +265,15 @@ static flashcart_error_t ed64_set_save_type (flashcart_save_type_t save_type) { return FLASHCART_OK; } -// static flashcart_error_t ed64_set_save_writeback (uint32_t *sectors) { -// // ed64_write_data(sectors, ED64_BUFFERS->BUFFER, 1024); +static flashcart_error_t ed64_set_save_writeback (uint32_t *sectors) { +// ed64_write_data(sectors, ED64_BUFFERS->BUFFER, 1024); -// // if (ed64_writeback_enable(ED64_BUFFERS->BUFFER) != ED64_OK) { -// // return FLASHCART_ERROR_INT; -// // } +// if (ed64_writeback_enable(ED64_BUFFERS->BUFFER) != ED64_OK) { +// return FLASHCART_ERROR_INT; +// } -// return FLASHCART_OK; -// } + return FLASHCART_OK; +} static flashcart_t flashcart_ed64 = { @@ -282,7 +282,7 @@ static flashcart_t flashcart_ed64 = { .load_rom = ed64_load_rom, .load_save = ed64_load_save, .set_save_type = ed64_set_save_type, - //.set_save_writeback = ed64_set_save_writeback, + .set_save_writeback = ed64_set_save_writeback, }; diff --git a/src/flashcart/ed64/ed64_internal.c b/src/flashcart/ed64/ed64_internal.c index b66f16ec..1811aa26 100644 --- a/src/flashcart/ed64/ed64_internal.c +++ b/src/flashcart/ed64/ed64_internal.c @@ -638,7 +638,7 @@ uint8_t ed64_bios_gpio_read() { -/* 64DD functions */ +/* 64DD cart conversion save functions */ /* Set 64DD ON and Enabled?! */ void ed64_bios_64dd_ram_oe() { diff --git a/src/flashcart/ed64/ed64_internal.h b/src/flashcart/ed64/ed64_internal.h index 67c5afae..5cab9c75 100644 --- a/src/flashcart/ed64/ed64_internal.h +++ b/src/flashcart/ed64/ed64_internal.h @@ -138,7 +138,7 @@ void ed64_bios_gpio_mode_io(); void ed64_bios_gpio_off(); uint8_t ed64_bios_gpio_read(); -/* 64DD functions */ +/* 64DD cart conversion save functions */ void ed64_bios_64dd_ram_oe(); void ed64_bios_64dd_ram_we(); void ed64_bios_64dd_ram_off(); From 1834917f6f227619d17a5c9c235a0b0e22d3db2e Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Wed, 19 Jul 2023 19:45:53 +0100 Subject: [PATCH 22/64] Improve cart metadata --- src/flashcart/ed64/ed64.c | 5 +++++ src/flashcart/ed64/ed64_internal.c | 13 ++++++++++--- src/flashcart/ed64/ed64_internal.h | 19 +++++++++++++++++-- src/flashcart/flashcart.c | 2 ++ 4 files changed, 34 insertions(+), 5 deletions(-) diff --git a/src/flashcart/ed64/ed64.c b/src/flashcart/ed64/ed64.c index be7430bc..dd66a8a5 100644 --- a/src/flashcart/ed64/ed64.c +++ b/src/flashcart/ed64/ed64.c @@ -67,6 +67,10 @@ static flashcart_error_t ed64_init (void) { // ed64_bios_unlock_regs(); ed64_bios_init(); + // ed64_bios_reset_spx(); // only required if V2+ FW is updating! + + ed64_bios_set_ram_bank(1); // Seemingly bank 0 (for SRAM 128k) is only supported on V3 and it is not the default. + ed64_bios_gpio_mode_io(); // if (!ed64_check_presence()) { // return FLASHCART_ERROR_UNSUPPORTED; @@ -122,6 +126,7 @@ static flashcart_error_t ed64_deinit (void) { // ed64_set_config(CFG_ROM_WRITE_ENABLE, false); ed64_bios_lock_regs(); + ed64_bios_gpio_mode_off(); return FLASHCART_OK; } diff --git a/src/flashcart/ed64/ed64_internal.c b/src/flashcart/ed64/ed64_internal.c index 1811aa26..ac51d706 100644 --- a/src/flashcart/ed64/ed64_internal.c +++ b/src/flashcart/ed64/ed64_internal.c @@ -395,14 +395,21 @@ void ed64_bios_set_ram_bank(uint8_t bank) { } -void ed64_bios_read_bios(void *dst, uint16_t start_address, uint16_t slen) { +/* reads metadata related to the assembily date and cart capabilities */ +void ed64_bios_read_cart_metadata(void *dest) { uint16_t cfg = ed64_bios_reg_read(REG_CFG); cfg &= ~ED_CFG_SDRAM_ON; ed64_bios_reg_write(REG_CFG, cfg); - ed64_bios_dma_read_rom(dst, start_address, slen); + ed64_bios_dma_read_rom(dest, 0, 1); + + // assembily_date = (buff[0x38] << 8) | buff[0x39]; + // assembily_time = (buff[0x3A] << 8) | buff[0x3B]; + // serial_number = (buff[0x3C] << 8) | buff[0x3D]; + // cic_6105_compatible = buff[0x40] == 0x03 ? true : false; // CIC_6105 : CIC_6102; + cfg |= ED_CFG_SDRAM_ON; ed64_bios_reg_write(REG_CFG, cfg); @@ -617,7 +624,7 @@ void ed64_bios_gpio_mode_io() { } /* Set GPIO mode OFF */ -void ed64_bios_gpio_off() { +void ed64_bios_gpio_mode_off() { uint16_t cfg = ed64_bios_reg_read(REG_CFG); cfg &= ~ED_CFG_GPIO_ON; diff --git a/src/flashcart/ed64/ed64_internal.h b/src/flashcart/ed64/ed64_internal.h index 5cab9c75..a73d3e78 100644 --- a/src/flashcart/ed64/ed64_internal.h +++ b/src/flashcart/ed64/ed64_internal.h @@ -10,6 +10,7 @@ #include #include +#include /** * @addtogroup ed64 @@ -29,6 +30,17 @@ typedef enum { } ed64_save_type_t; +typedef struct { + uint16_t assembily_date; /* The Date that the ED64 was manufactured */ + uint16_t assembily_time; /* The Time that the ED64 was manufactured */ + uint16_t serial_number; /* The ED64 serial number (unique for each ED64) */ + bool cic_6105_compatible; /* This returns whether the the cart CIC is 6105 compatible + as many were produced before Ultra CIC existed! + Carts that are not compatible will be unable to run certain ROMs */ + +} ed64_cart_metadata_s; + + #define SRAM_FLASHRAM_ADDRESS (0xA8000000) #define ROM_ADDRESS (0xB0000000) @@ -112,10 +124,13 @@ void ed64_bios_byteswap_on(); void ed64_bios_byteswap_off(); /* Save functions */ +void ed64_bios_set_ram_bank(uint8_t bank); ed64_save_type_t ed64_bios_get_save_type(); void ed64_bios_set_save_type(ed64_save_type_t type); -void ed64_bios_read_bios(void *dst, uint16_t start_address, uint16_t slen); +/* reads metadata related to the assembily date and cart capabilities */ +void ed64_bios_read_cart_metadata(void *dest); + uint16_t ed64_bios_msg_rd(); void ed64_bios_msg_wr(uint16_t val); @@ -135,7 +150,7 @@ void ed64_bios_reset_spx(); /* GPIO functions */ void ed64_bios_gpio_mode_rtc(); void ed64_bios_gpio_mode_io(); -void ed64_bios_gpio_off(); +void ed64_bios_gpio_mode_off(); uint8_t ed64_bios_gpio_read(); /* 64DD cart conversion save functions */ diff --git a/src/flashcart/flashcart.c b/src/flashcart/flashcart.c index ba76900b..edd59002 100644 --- a/src/flashcart/flashcart.c +++ b/src/flashcart/flashcart.c @@ -46,10 +46,12 @@ flashcart_error_t flashcart_init (void) { } switch (usb_getcart()) { + case CART_64DRIVE: break; case CART_EVERDRIVE: + /* Given that the ED64 uses a software implementation, this will likely fail unless running this menu?! */ flashcart = ed64_get_flashcart(); break; From c67967e12d0dfde5c25c1a467623cb66ecc32fad Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Wed, 19 Jul 2023 19:56:32 +0100 Subject: [PATCH 23/64] Add note on flashram --- src/flashcart/ed64/README.md | 4 ++-- src/flashcart/ed64/ed64_internal.c | 4 ++-- src/flashcart/ed64/ed64_internal.h | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/flashcart/ed64/README.md b/src/flashcart/ed64/README.md index f1c3a020..75c07b96 100644 --- a/src/flashcart/ed64/README.md +++ b/src/flashcart/ed64/README.md @@ -10,6 +10,6 @@ Initially, this aims to work when loading the ED64 menu, selecting the N64Flashc Notes: -`libcart`` seems to use a different base register address (0x08040000), but official implementation uses 0xA8040000 - +* `libcart` seems to use a different base register address `0x08040000`, but official implementation uses `0xA8040000` +* The ability to load/save `FLASHRAM` may not yet supported. diff --git a/src/flashcart/ed64/ed64_internal.c b/src/flashcart/ed64/ed64_internal.c index ac51d706..2429bae4 100644 --- a/src/flashcart/ed64/ed64_internal.c +++ b/src/flashcart/ed64/ed64_internal.c @@ -439,7 +439,7 @@ void ed64_bios_dma_read_sram(void *ram, uint32_t address, uint32_t length) { IO_WRITE(PI_BSD_DOM2_LAT_REG, 0x05); IO_WRITE(PI_BSD_DOM2_PWD_REG, 0x0C); - ed64_bios_dma_read(ram, SRAM_FLASHRAM_ADDRESS + address, length); + ed64_bios_dma_read(ram, SRAM_ADDRESS + address, length); IO_WRITE(PI_BSD_DOM2_LAT_REG, piLatReg); IO_WRITE(PI_BSD_DOM2_PWD_REG, piPwdReg); @@ -460,7 +460,7 @@ void ed64_bios_dma_write_sram(void *ram, uint32_t address, uint32_t length) { IO_WRITE(PI_BSD_DOM2_LAT_REG, 0x05); IO_WRITE(PI_BSD_DOM2_PWD_REG, 0x0C); - ed64_bios_dma_write(ram, SRAM_FLASHRAM_ADDRESS + address, length); + ed64_bios_dma_write(ram, SRAM_ADDRESS + address, length); IO_WRITE(PI_BSD_DOM2_LAT_REG, piLatReg); diff --git a/src/flashcart/ed64/ed64_internal.h b/src/flashcart/ed64/ed64_internal.h index a73d3e78..a70a5ed4 100644 --- a/src/flashcart/ed64/ed64_internal.h +++ b/src/flashcart/ed64/ed64_internal.h @@ -41,8 +41,8 @@ typedef struct { } ed64_cart_metadata_s; -#define SRAM_FLASHRAM_ADDRESS (0xA8000000) -#define ROM_ADDRESS (0xB0000000) +#define SRAM_ADDRESS (0xA8000000) +#define ROM_ADDRESS (0xB0000000) #define USB_ERROR_FIFO_TIMEOUT 0x90 #define EVD_ERROR_MMC_TIMEOUT 0x91 From 96b6fa2772e3107f3b4a8d4bf5ab86a5ea6fd7d1 Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Wed, 19 Jul 2023 20:20:39 +0100 Subject: [PATCH 24/64] Add implementation of ED64 load ROM Untested. --- src/flashcart/ed64/ed64.c | 44 ++++++++++++++++----------------------- 1 file changed, 18 insertions(+), 26 deletions(-) diff --git a/src/flashcart/ed64/ed64.c b/src/flashcart/ed64/ed64.c index dd66a8a5..57c99d1a 100644 --- a/src/flashcart/ed64/ed64.c +++ b/src/flashcart/ed64/ed64.c @@ -48,10 +48,10 @@ // return FLASHCART_OK; // } -// static void load_cleanup (FIL *fil) { -// // ed64_sd_set_byte_swap(false); -// f_close(fil); -// } +static void load_cleanup (FIL *fil) { + ed64_bios_byteswap_off(); + f_close(fil); +} static flashcart_error_t ed64_init (void) { @@ -133,7 +133,7 @@ static flashcart_error_t ed64_deinit (void) { static flashcart_error_t ed64_load_rom (char *rom_path, bool byte_swap) { FIL fil; - // UINT br; + UINT br; if (f_open(&fil, rom_path, FA_READ) != FR_OK) { return FLASHCART_ERROR_LOAD; @@ -151,32 +151,24 @@ static flashcart_error_t ed64_load_rom (char *rom_path, bool byte_swap) { return FLASHCART_ERROR_LOAD; } - // if (ed64_sd_set_byte_swap(byte_swap) != ED64_OK) { - // load_cleanup(&fil); - // return FLASHCART_ERROR_INT; - // } + if (byte_swap) { + ed64_bios_byteswap_on(); + } - // size_t sdram_size = rom_size; + size_t sdram_size = rom_size; - // if (f_read(&fil, (void *) (ROM_ADDRESS), sdram_size, &br) != FR_OK) { - // load_cleanup(&fil); - // return FLASHCART_ERROR_LOAD; - // } - // if (br != sdram_size) { - // load_cleanup(&fil); - // return FLASHCART_ERROR_LOAD; - // } + if (f_read(&fil, (void *) (ROM_ADDRESS), sdram_size, &br) != FR_OK) { + load_cleanup(&fil); + return FLASHCART_ERROR_LOAD; + } + if (br != sdram_size) { + load_cleanup(&fil); + return FLASHCART_ERROR_LOAD; + } - // if (ed64_set_config(CFG_ROM_EXTENDED_ENABLE, extended_enabled) != ED64_OK) { - // load_cleanup(&fil); - // return FLASHCART_ERROR_INT; - // } - // if (ed64_sd_set_byte_swap(false) != ED64_OK) { - // load_cleanup(&fil); - // return FLASHCART_ERROR_INT; - // } + ed64_bios_byteswap_off(); if (f_close(&fil) != FR_OK) { return FLASHCART_ERROR_LOAD; From b947fe2f1c3042379244ddb58f5dc97de0f6505b Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Wed, 19 Jul 2023 20:49:23 +0100 Subject: [PATCH 25/64] Part enable loading a save. --- src/flashcart/ed64/ed64.c | 38 +++++++++++++++++++------------------- 1 file changed, 19 insertions(+), 19 deletions(-) diff --git a/src/flashcart/ed64/ed64.c b/src/flashcart/ed64/ed64.c index 57c99d1a..8b261190 100644 --- a/src/flashcart/ed64/ed64.c +++ b/src/flashcart/ed64/ed64.c @@ -61,8 +61,8 @@ static flashcart_error_t ed64_init (void) { // HACK: Because libcart reads PI config from address 0x10000000 when initializing // we need to write safe value before running any libcart function. // Data in SDRAM can be undefined at this point and result in setting incorrect PI config. - // extern uint32_t cart_dom1; - // cart_dom1 = 0x80371240; + extern uint32_t cart_dom1; + cart_dom1 = 0x80371240; // ed64_bios_unlock_regs(); @@ -178,7 +178,7 @@ static flashcart_error_t ed64_load_rom (char *rom_path, bool byte_swap) { } static flashcart_error_t ed64_load_save (char *save_path) { -// void *address = NULL; + void *address = NULL; // ed64_save_type_t type = ed64_bios_get_save_type(); // // if (ed64_get_config(CFG_SAVE_TYPE, &type) != ED64_OK) { @@ -200,27 +200,27 @@ static flashcart_error_t ed64_load_save (char *save_path) { // // return FLASHCART_ERROR_ARGS; // // } -// FIL fil; -// UINT br; + FIL fil; + UINT br; -// if (f_open(&fil, save_path, FA_READ) != FR_OK) { -// return FLASHCART_ERROR_LOAD; -// } + if (f_open(&fil, save_path, FA_READ) != FR_OK) { + return FLASHCART_ERROR_LOAD; + } -// size_t save_size = f_size(&fil); + size_t save_size = f_size(&fil); -// if (f_read(&fil, address, save_size, &br) != FR_OK) { -// f_close(&fil); -// return FLASHCART_ERROR_LOAD; -// } + if (f_read(&fil, address, save_size, &br) != FR_OK) { + f_close(&fil); + return FLASHCART_ERROR_LOAD; + } -// if (f_close(&fil) != FR_OK) { -// return FLASHCART_ERROR_LOAD; -// } + if (f_close(&fil) != FR_OK) { + return FLASHCART_ERROR_LOAD; + } -// if (br != save_size) { -// return FLASHCART_ERROR_LOAD; -// } + if (br != save_size) { + return FLASHCART_ERROR_LOAD; + } return FLASHCART_OK; } From 206ce6282765ba5eb8de70ce5ae25a564387ab6b Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Wed, 19 Jul 2023 20:54:03 +0100 Subject: [PATCH 26/64] Update README.md --- src/flashcart/ed64/README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/flashcart/ed64/README.md b/src/flashcart/ed64/README.md index 75c07b96..24700d51 100644 --- a/src/flashcart/ed64/README.md +++ b/src/flashcart/ed64/README.md @@ -6,7 +6,7 @@ It is based on OS 2.12.x as used in the "Unofficial Menu" (https://github.com/n6 It may require further cleansing and updating to use the latest libdragon before it will probably work based on the fact that using the latest libdragon with `libcart` seems to have a detremental effect on the ability to load ROM's. -Initially, this aims to work when loading the ED64 menu, selecting the N64FlashcartMenu and then loading a ROM from there. This works around needing to load the correct firmware. To automate this, it is possible to set the menu to autoload (at least in the unofficial menu). e.g. You can set this ROM to auto load by placing a file called `autoexec.v64` in the `ED64` folder with the content of the file pointing to the path of this ROM. +Initially, this aims to work when loading the official ED64 OS menu, selecting the N64FlashcartMenu and then loading a ROM from there. This works around needing to load the correct firmware. To automate this, it is possible to set this menu to autoload (at least in the unofficial menu). i.e. You can set this ROM to auto load by placing a file called `autoexec.v64` in the `ED64` folder with the content of the file pointing to the path of this ROM. Notes: From aa51f67a4502f6c46a1c5407b54b254cd90cffd9 Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Wed, 19 Jul 2023 20:54:42 +0100 Subject: [PATCH 27/64] Update README.md --- src/flashcart/ed64/README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/flashcart/ed64/README.md b/src/flashcart/ed64/README.md index 24700d51..13412c37 100644 --- a/src/flashcart/ed64/README.md +++ b/src/flashcart/ed64/README.md @@ -11,5 +11,5 @@ Initially, this aims to work when loading the official ED64 OS menu, selecting t Notes: * `libcart` seems to use a different base register address `0x08040000`, but official implementation uses `0xA8040000` -* The ability to load/save `FLASHRAM` may not yet supported. +* The ability to load/save `FLASHRAM` may not yet be supported. From cc234732353fb63c0b1b55b32f140483142763e5 Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Fri, 21 Jul 2023 14:21:06 +0100 Subject: [PATCH 28/64] PR feedback improvements --- src/flashcart/ed64/ed64.c | 22 +++------------------- 1 file changed, 3 insertions(+), 19 deletions(-) diff --git a/src/flashcart/ed64/ed64.c b/src/flashcart/ed64/ed64.c index 8b261190..7c5f7432 100644 --- a/src/flashcart/ed64/ed64.c +++ b/src/flashcart/ed64/ed64.c @@ -58,12 +58,6 @@ static flashcart_error_t ed64_init (void) { // uint16_t major; // uint16_t minor; - // HACK: Because libcart reads PI config from address 0x10000000 when initializing - // we need to write safe value before running any libcart function. - // Data in SDRAM can be undefined at this point and result in setting incorrect PI config. - extern uint32_t cart_dom1; - cart_dom1 = 0x80371240; - // ed64_bios_unlock_regs(); ed64_bios_init(); @@ -125,8 +119,8 @@ static flashcart_error_t ed64_deinit (void) { // // NOTE: Necessary because libcart enables ROM write by default // ed64_set_config(CFG_ROM_WRITE_ENABLE, false); + ed64_bios_gpio_mode_off(); // On V3, this should be ed64_bios_gpio_mode_rtc() if it is required. ed64_bios_lock_regs(); - ed64_bios_gpio_mode_off(); return FLASHCART_OK; } @@ -146,7 +140,7 @@ static flashcart_error_t ed64_load_rom (char *rom_path, bool byte_swap) { size_t rom_size = f_size(&fil); - if (rom_size > MiB(78)) { + if (rom_size > MiB(64)) { f_close(&fil); return FLASHCART_ERROR_LOAD; } @@ -262,16 +256,6 @@ static flashcart_error_t ed64_set_save_type (flashcart_save_type_t save_type) { return FLASHCART_OK; } -static flashcart_error_t ed64_set_save_writeback (uint32_t *sectors) { -// ed64_write_data(sectors, ED64_BUFFERS->BUFFER, 1024); - -// if (ed64_writeback_enable(ED64_BUFFERS->BUFFER) != ED64_OK) { -// return FLASHCART_ERROR_INT; -// } - - return FLASHCART_OK; -} - static flashcart_t flashcart_ed64 = { .init = ed64_init, @@ -279,7 +263,7 @@ static flashcart_t flashcart_ed64 = { .load_rom = ed64_load_rom, .load_save = ed64_load_save, .set_save_type = ed64_set_save_type, - .set_save_writeback = ed64_set_save_writeback, + .set_save_writeback = NULL, }; From 96eef11658ce63877be5d0176da317c5dac170e5 Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Mon, 21 Aug 2023 13:34:50 +0100 Subject: [PATCH 29/64] Re-align source. --- Makefile | 4 +- libdragon | 2 +- src/flashcart/ed64/ed64.c | 178 +++++++++++------- src/flashcart/ed64/ed64.h | 3 +- .../ed64/{ed64_internal.c => ed64_ll.c} | 12 +- .../ed64/{ed64_internal.h => ed64_ll.h} | 14 +- src/flashcart/flashcart.c | 3 +- 7 files changed, 127 insertions(+), 89 deletions(-) rename src/flashcart/ed64/{ed64_internal.c => ed64_ll.c} (98%) rename src/flashcart/ed64/{ed64_internal.h => ed64_ll.h} (95%) diff --git a/Makefile b/Makefile index 948c9c1d..4648cea0 100644 --- a/Makefile +++ b/Makefile @@ -20,8 +20,8 @@ SRCS = \ flashcart/flashcart.c \ flashcart/sc64/sc64_ll.c \ flashcart/sc64/sc64.c \ - flashcart/ed64/ed64_internal.c \ - flashcart/sc64/ed64.c \ + flashcart/ed64/ed64_ll.c \ + flashcart/ed64/ed64.c \ hdmi/hdmi.c \ libs/libspng/spng/spng.c \ libs/mini.c/src/mini.c \ diff --git a/libdragon b/libdragon index 35267992..520419b7 160000 --- a/libdragon +++ b/libdragon @@ -1 +1 @@ -Subproject commit 352679922bad5403f8ea4b9123dfe0403d030bc2 +Subproject commit 520419b7a952eb519c89539fb2cb2f097bf3c2cf diff --git a/src/flashcart/ed64/ed64.c b/src/flashcart/ed64/ed64.c index 7c5f7432..d75c4311 100644 --- a/src/flashcart/ed64/ed64.c +++ b/src/flashcart/ed64/ed64.c @@ -8,7 +8,8 @@ #include "utils/fs.h" #include "utils/utils.h" -#include "ed64_internal.h" +#include "../flashcart_utils.h" +#include "ed64_ll.h" #include "ed64.h" @@ -17,46 +18,45 @@ // #define SUPPORTED_MAJOR_VERSION (2) // #define SUPPORTED_MINOR_VERSION (12) - - -// static flashcart_error_t load_to_flash (FIL *fil, void *address, size_t size, UINT *br) { - // size_t erase_block_size; - // UINT bp; - - // *br = 0; - - // if (ed64_flash_get_erase_block_size(&erase_block_size) != ED64_OK) { - // return FLASHCART_ERROR_INT; - // } - - // while (size > 0) { - // size_t program_size = MIN(size, erase_block_size); - // if (ed64_flash_erase_block(address) != ED64_OK) { - // return FLASHCART_ERROR_INT; - // } - // if (f_read(fil, address, program_size, &bp) != FR_OK) { - // return FLASHCART_ERROR_LOAD; - // } - // if (ed64_flash_wait_busy() != ED64_OK) { - // return FLASHCART_ERROR_INT; - // } - // address += program_size; - // size -= program_size; - // *br += bp; - // } +// #define SUPPORTED_REVISION (0) + + +// static flashcart_error_t load_to_flash (FIL *fil, void *address, size_t size, UINT *br, flashcart_progress_callback_t *progress) { +// size_t erase_block_size; +// UINT bp; + +// *br = 0; + +// if (ed64_flash_get_erase_block_size(&erase_block_size) != ED64_OK) { +// return FLASHCART_ERROR_INT; +// } + +// while (size > 0) { +// size_t program_size = MIN(size, erase_block_size); +// if (ed64_flash_erase_block(address) != ED64_OK) { +// return FLASHCART_ERROR_INT; +// } +// if (f_read(fil, address, program_size, &bp) != FR_OK) { +// return FLASHCART_ERROR_LOAD; +// } +// if (ed64_flash_wait_busy() != ED64_OK) { +// return FLASHCART_ERROR_INT; +// } +// if (progress) { +// progress(f_tell(fil) / (float) (f_size(fil))); +// } +// address += program_size; +// size -= program_size; +// *br += bp; +// } // return FLASHCART_OK; // } -static void load_cleanup (FIL *fil) { - ed64_bios_byteswap_off(); - f_close(fil); -} - - static flashcart_error_t ed64_init (void) { // uint16_t major; // uint16_t minor; + //uint32_t revision; // ed64_bios_unlock_regs(); @@ -90,20 +90,20 @@ static flashcart_error_t ed64_init (void) { // ed64_cfg_t id; // uint32_t value; // } default_config[] = { - // { CFG_BOOTLOADER_SWITCH, false }, - // { CFG_ROM_WRITE_ENABLE, false }, - // { CFG_ROM_SHADOW_ENABLE, false }, - // { CFG_DD_MODE, DD_MODE_DISABLED }, - // { CFG_ISV_ADDRESS, 0x00000000 }, - // { CFG_BOOT_MODE, BOOT_MODE_MENU }, - // { CFG_SAVE_TYPE, SAVE_TYPE_NONE }, - // { CFG_CIC_SEED, CIC_SEED_AUTO }, - // { CFG_TV_TYPE, TV_TYPE_PASSTHROUGH }, - // { CFG_DD_SD_ENABLE, false }, - // { CFG_DD_DRIVE_TYPE, DRIVE_TYPE_RETAIL }, - // { CFG_DD_DISK_STATE, DISK_STATE_EJECTED }, - // { CFG_BUTTON_MODE, BUTTON_MODE_NONE }, - // { CFG_ROM_EXTENDED_ENABLE, false }, + // { CFG_ID_BOOTLOADER_SWITCH, false }, + // { CFG_ID_ROM_WRITE_ENABLE, false }, + // { CFG_ID_ROM_SHADOW_ENABLE, false }, + // { CFG_ID_DD_MODE, DD_MODE_DISABLED }, + // { CFG_ID_ISV_ADDRESS, 0x00000000 }, + // { CFG_ID_BOOT_MODE, BOOT_MODE_MENU }, + // { CFG_ID_SAVE_TYPE, SAVE_TYPE_NONE }, + // { CFG_ID_CIC_SEED, CIC_SEED_AUTO }, + // { CFG_ID_TV_TYPE, TV_TYPE_PASSTHROUGH }, + // { CFG_ID_DD_SD_ENABLE, false }, + // { CFG_ID_DD_DRIVE_TYPE, DRIVE_TYPE_RETAIL }, + // { CFG_ID_DD_DISK_STATE, DISK_STATE_EJECTED }, + // { CFG_ID_BUTTON_MODE, BUTTON_MODE_NONE }, + // { CFG_ID_ROM_EXTENDED_ENABLE, false }, // }; // for (int i = 0; i < sizeof(default_config) / sizeof(default_config[0]); i++) { @@ -125,18 +125,15 @@ static flashcart_error_t ed64_deinit (void) { return FLASHCART_OK; } -static flashcart_error_t ed64_load_rom (char *rom_path, bool byte_swap) { +static flashcart_error_t ed64_load_rom (char *rom_path, flashcart_progress_callback_t *progress) { FIL fil; UINT br; - if (f_open(&fil, rom_path, FA_READ) != FR_OK) { + if (f_open(&fil, strip_sd_prefix(rom_path), FA_READ) != FR_OK) { return FLASHCART_ERROR_LOAD; } - // HACK: Align file size to the SD sector size to prevent FatFs from doing partial sector load. - // We are relying on direct transfer from SD to SDRAM without CPU intervention. - // Sending some extra bytes isn't an issue here. - fil.obj.objsize = ALIGN(f_size(&fil), FS_SECTOR_SIZE); + fix_file_size(&fil); size_t rom_size = f_size(&fil); @@ -145,24 +142,63 @@ static flashcart_error_t ed64_load_rom (char *rom_path, bool byte_swap) { return FLASHCART_ERROR_LOAD; } - if (byte_swap) { - ed64_bios_byteswap_on(); - } - size_t sdram_size = rom_size; - if (f_read(&fil, (void *) (ROM_ADDRESS), sdram_size, &br) != FR_OK) { - load_cleanup(&fil); + size_t chunk_size = MiB(1); + for (int offset = 0; offset < sdram_size; offset += chunk_size) { + size_t block_size = MIN(sdram_size - offset, chunk_size); + if (f_read(&fil, (void *) (ROM_ADDRESS + offset), block_size, &br) != FR_OK) { + f_close(&fil); + return FLASHCART_ERROR_LOAD; + } + if (progress) { + progress(f_tell(&fil) / (float) (f_size(&fil))); + } + } + if (f_tell(&fil) != sdram_size) { + f_close(&fil); return FLASHCART_ERROR_LOAD; } - if (br != sdram_size) { - load_cleanup(&fil); + + + if (f_close(&fil) != FR_OK) { return FLASHCART_ERROR_LOAD; } + return FLASHCART_OK; +} + +static flashcart_error_t ed64_load_file (char *file_path, uint32_t rom_offset, uint32_t file_offset) { + FIL fil; + UINT br; + + if (f_open(&fil, strip_sd_prefix(file_path), FA_READ) != FR_OK) { + return FLASHCART_ERROR_LOAD; + } + + fix_file_size(&fil); + + size_t file_size = f_size(&fil) - file_offset; - ed64_bios_byteswap_off(); + if (file_size > (MiB(64) - rom_offset)) { + f_close(&fil); + return FLASHCART_ERROR_ARGS; + } + + if (f_lseek(&fil, file_offset) != FR_OK) { + f_close(&fil); + return FLASHCART_ERROR_LOAD; + } + + if (f_read(&fil, (void *) (ROM_ADDRESS + rom_offset), file_size, &br) != FR_OK) { + f_close(&fil); + return FLASHCART_ERROR_LOAD; + } + if (br != file_size) { + f_close(&fil); + return FLASHCART_ERROR_LOAD; + } if (f_close(&fil) != FR_OK) { return FLASHCART_ERROR_LOAD; @@ -197,7 +233,7 @@ static flashcart_error_t ed64_load_save (char *save_path) { FIL fil; UINT br; - if (f_open(&fil, save_path, FA_READ) != FR_OK) { + if (f_open(&fil, strip_sd_prefix(save_path), FA_READ) != FR_OK) { return FLASHCART_ERROR_LOAD; } @@ -220,28 +256,27 @@ static flashcart_error_t ed64_load_save (char *save_path) { } static flashcart_error_t ed64_set_save_type (flashcart_save_type_t save_type) { - - ed64_save_type_t type = SAVE_TYPE_OFF; + ed64_save_type_t type; switch (save_type) { case FLASHCART_SAVE_TYPE_NONE: - type = SAVE_TYPE_OFF; + type = SAVE_TYPE_NONE; break; case FLASHCART_SAVE_TYPE_EEPROM_4K: - type = SAVE_TYPE_EEP4k; + type = SAVE_TYPE_EEPROM_4K; break; case FLASHCART_SAVE_TYPE_EEPROM_16K: - type = SAVE_TYPE_EEP16k; + type = SAVE_TYPE_EEPROM_16K; break; case FLASHCART_SAVE_TYPE_SRAM: type = SAVE_TYPE_SRAM; break; case FLASHCART_SAVE_TYPE_SRAM_BANKED: case FLASHCART_SAVE_TYPE_SRAM_128K: - type = SAVE_TYPE_SRAM128; + type = SAVE_TYPE_SRAM_128K; break; case FLASHCART_SAVE_TYPE_FLASHRAM: - type = SAVE_TYPE_FLASH; + type = SAVE_TYPE_FLASHRAM; break; default: return FLASHCART_ERROR_ARGS; @@ -261,6 +296,7 @@ static flashcart_t flashcart_ed64 = { .init = ed64_init, .deinit = ed64_deinit, .load_rom = ed64_load_rom, + .load_file = ed64_load_file, .load_save = ed64_load_save, .set_save_type = ed64_set_save_type, .set_save_writeback = NULL, diff --git a/src/flashcart/ed64/ed64.h b/src/flashcart/ed64/ed64.h index 916dd1db..4738140f 100644 --- a/src/flashcart/ed64/ed64.h +++ b/src/flashcart/ed64/ed64.h @@ -10,14 +10,15 @@ #include "../flashcart.h" + /** * @addtogroup ed64 * @{ */ - flashcart_t *ed64_get_flashcart (void); /** @} */ /* ed64 */ + #endif diff --git a/src/flashcart/ed64/ed64_internal.c b/src/flashcart/ed64/ed64_ll.c similarity index 98% rename from src/flashcart/ed64/ed64_internal.c rename to src/flashcart/ed64/ed64_ll.c index 2429bae4..da9d7ada 100644 --- a/src/flashcart/ed64/ed64_internal.c +++ b/src/flashcart/ed64/ed64_ll.c @@ -1,6 +1,6 @@ #include -#include "ed64_internal.h" +#include "ed64_ll.h" /* Locks the ED64 registers */ #define ED64_KEY_LOCK 0x0000 @@ -191,7 +191,7 @@ uint8_t ed64_bios_init() { spi_cfg = SPI_CFG_SS | BI_SPI_SPD_LO; ed64_bios_reg_write(REG_CFG, ED_CFG_SDRAM_ON); ed64_bios_reg_write(REG_SPI_CFG, spi_cfg); - ed64_bios_save_type = SAVE_TYPE_OFF; + ed64_bios_save_type = SAVE_TYPE_NONE; return cold_start; @@ -352,21 +352,21 @@ void ed64_bios_set_save_type(ed64_save_type_t type) { switch (type) { - case SAVE_TYPE_EEP16k: + case SAVE_TYPE_EEPROM_16K: eeprom_on = 1; eeprom_size = 1; break; - case SAVE_TYPE_EEP4k: + case SAVE_TYPE_EEPROM_4K: eeprom_on = 1; break; case SAVE_TYPE_SRAM: sram_on = 1; break; - case SAVE_TYPE_SRAM128: + case SAVE_TYPE_SRAM_128K: sram_on = 1; sram_size = 1; break; - case SAVE_TYPE_FLASH: + case SAVE_TYPE_FLASHRAM: sram_on = 0; sram_size = 1; break; diff --git a/src/flashcart/ed64/ed64_internal.h b/src/flashcart/ed64/ed64_ll.h similarity index 95% rename from src/flashcart/ed64/ed64_internal.h rename to src/flashcart/ed64/ed64_ll.h index a70a5ed4..b140c2da 100644 --- a/src/flashcart/ed64/ed64_internal.h +++ b/src/flashcart/ed64/ed64_ll.h @@ -4,8 +4,8 @@ * @ingroup flashcart */ -#ifndef FLASHCART_ED64_INTERNAL_H__ -#define FLASHCART_ED64_INTERNAL_H__ +#ifndef FLASHCART_ED64_LL_H__ +#define FLASHCART_ED64_LL_H__ #include @@ -19,12 +19,12 @@ typedef enum { - SAVE_TYPE_OFF = 0, + SAVE_TYPE_NONE = 0, SAVE_TYPE_SRAM = 1, - SAVE_TYPE_SRAM128 = 2, - SAVE_TYPE_EEP4k = 3, - SAVE_TYPE_EEP16k = 4, - SAVE_TYPE_FLASH = 5, + SAVE_TYPE_SRAM_128K = 2, + SAVE_TYPE_EEPROM_4K = 3, + SAVE_TYPE_EEPROM_16K = 4, + SAVE_TYPE_FLASHRAM = 5, SAVE_TYPE_CPAK = 8, SAVE_TYPE_DD64 = 16, } ed64_save_type_t; diff --git a/src/flashcart/flashcart.c b/src/flashcart/flashcart.c index 81052ca6..85e60eec 100644 --- a/src/flashcart/flashcart.c +++ b/src/flashcart/flashcart.c @@ -9,6 +9,7 @@ #include "flashcart.h" #include "sc64/sc64.h" +#include "ed64/ed64.h" #define WRITEBACK_MAX_SECTORS (256) @@ -58,7 +59,7 @@ flashcart_error_t flashcart_init (void) { { CART_CI, ci_init, NULL }, // 64drive { CART_SC, sc_init, sc64_get_flashcart }, // SC64 { CART_EDX, edx_init, NULL }, // Series X EverDrive-64 - { CART_ED, ed_init, NULL }, // Original EverDrive-64 + { CART_ED, ed_init, ed64_get_flashcart }, // Original EverDrive-64 }; for (int i = 0; i < CART_MAX; i++) { From d26e082faa6758793aecd8460aebc368a443f4a6 Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Mon, 21 Aug 2023 13:35:46 +0100 Subject: [PATCH 30/64] Update libdragon --- libdragon | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libdragon b/libdragon index 520419b7..093e7eb0 160000 --- a/libdragon +++ b/libdragon @@ -1 +1 @@ -Subproject commit 520419b7a952eb519c89539fb2cb2f097bf3c2cf +Subproject commit 093e7eb03ef7a5d132858166e721aa77707d5008 From c0850f89b0fe844cafd3c961fc81f77d58b5562d Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Mon, 21 Aug 2023 14:32:52 +0100 Subject: [PATCH 31/64] ED64 can now load ROM's Cleanup source. --- src/flashcart/ed64/ed64.c | 151 ++++++++------------------------------ 1 file changed, 32 insertions(+), 119 deletions(-) diff --git a/src/flashcart/ed64/ed64.c b/src/flashcart/ed64/ed64.c index d75c4311..98945f63 100644 --- a/src/flashcart/ed64/ed64.c +++ b/src/flashcart/ed64/ed64.c @@ -13,104 +13,17 @@ #include "ed64.h" -// #define SRAM_FLASHRAM_ADDRESS (0x08000000) -// #define ROM_ADDRESS (0x10000000) - -// #define SUPPORTED_MAJOR_VERSION (2) -// #define SUPPORTED_MINOR_VERSION (12) -// #define SUPPORTED_REVISION (0) - - -// static flashcart_error_t load_to_flash (FIL *fil, void *address, size_t size, UINT *br, flashcart_progress_callback_t *progress) { -// size_t erase_block_size; -// UINT bp; - -// *br = 0; - -// if (ed64_flash_get_erase_block_size(&erase_block_size) != ED64_OK) { -// return FLASHCART_ERROR_INT; -// } - -// while (size > 0) { -// size_t program_size = MIN(size, erase_block_size); -// if (ed64_flash_erase_block(address) != ED64_OK) { -// return FLASHCART_ERROR_INT; -// } -// if (f_read(fil, address, program_size, &bp) != FR_OK) { -// return FLASHCART_ERROR_LOAD; -// } -// if (ed64_flash_wait_busy() != ED64_OK) { -// return FLASHCART_ERROR_INT; -// } -// if (progress) { -// progress(f_tell(fil) / (float) (f_size(fil))); -// } -// address += program_size; -// size -= program_size; -// *br += bp; -// } - -// return FLASHCART_OK; -// } - static flashcart_error_t ed64_init (void) { - // uint16_t major; - // uint16_t minor; - //uint32_t revision; + // ed64_bios_unlock_regs(); - ed64_bios_init(); + // ed64_bios_init(); // ed64_bios_reset_spx(); // only required if V2+ FW is updating! - ed64_bios_set_ram_bank(1); // Seemingly bank 0 (for SRAM 128k) is only supported on V3 and it is not the default. - ed64_bios_gpio_mode_io(); - - // if (!ed64_check_presence()) { - // return FLASHCART_ERROR_UNSUPPORTED; - // } - // if (ed64_get_version(&major, &minor) != ED64_OK) { - // return FLASHCART_ERROR_OUTDATED; - // } - // if (major != SUPPORTED_MAJOR_VERSION) { - // return FLASHCART_ERROR_OUTDATED; - // } - // if (minor < SUPPORTED_MINOR_VERSION) { - // return FLASHCART_ERROR_OUTDATED; - // } + // ed64_bios_set_ram_bank(1); // Seemingly bank 0 (for SRAM 128k) is only supported on V3 and it is not the default. + // ed64_bios_gpio_mode_io(); - // bool writeback_pending; - // do { - // if (ed64_writeback_pending(&writeback_pending) != ED64_OK) { - // return FLASHCART_ERROR_INT; - // } - // } while (writeback_pending); - - // const struct { - // ed64_cfg_t id; - // uint32_t value; - // } default_config[] = { - // { CFG_ID_BOOTLOADER_SWITCH, false }, - // { CFG_ID_ROM_WRITE_ENABLE, false }, - // { CFG_ID_ROM_SHADOW_ENABLE, false }, - // { CFG_ID_DD_MODE, DD_MODE_DISABLED }, - // { CFG_ID_ISV_ADDRESS, 0x00000000 }, - // { CFG_ID_BOOT_MODE, BOOT_MODE_MENU }, - // { CFG_ID_SAVE_TYPE, SAVE_TYPE_NONE }, - // { CFG_ID_CIC_SEED, CIC_SEED_AUTO }, - // { CFG_ID_TV_TYPE, TV_TYPE_PASSTHROUGH }, - // { CFG_ID_DD_SD_ENABLE, false }, - // { CFG_ID_DD_DRIVE_TYPE, DRIVE_TYPE_RETAIL }, - // { CFG_ID_DD_DISK_STATE, DISK_STATE_EJECTED }, - // { CFG_ID_BUTTON_MODE, BUTTON_MODE_NONE }, - // { CFG_ID_ROM_EXTENDED_ENABLE, false }, - // }; - - // for (int i = 0; i < sizeof(default_config) / sizeof(default_config[0]); i++) { - // if (ed64_set_config(default_config[i].id, default_config[i].value) != ED64_OK) { - // return FLASHCART_ERROR_INT; - // } - // } return FLASHCART_OK; } @@ -119,8 +32,8 @@ static flashcart_error_t ed64_deinit (void) { // // NOTE: Necessary because libcart enables ROM write by default // ed64_set_config(CFG_ROM_WRITE_ENABLE, false); - ed64_bios_gpio_mode_off(); // On V3, this should be ed64_bios_gpio_mode_rtc() if it is required. - ed64_bios_lock_regs(); + // ed64_bios_gpio_mode_off(); // On V3, this should be ed64_bios_gpio_mode_rtc() if it is required. + // ed64_bios_lock_regs(); return FLASHCART_OK; } @@ -256,37 +169,37 @@ static flashcart_error_t ed64_load_save (char *save_path) { } static flashcart_error_t ed64_set_save_type (flashcart_save_type_t save_type) { - ed64_save_type_t type; - - switch (save_type) { - case FLASHCART_SAVE_TYPE_NONE: - type = SAVE_TYPE_NONE; - break; - case FLASHCART_SAVE_TYPE_EEPROM_4K: - type = SAVE_TYPE_EEPROM_4K; - break; - case FLASHCART_SAVE_TYPE_EEPROM_16K: - type = SAVE_TYPE_EEPROM_16K; - break; - case FLASHCART_SAVE_TYPE_SRAM: - type = SAVE_TYPE_SRAM; - break; - case FLASHCART_SAVE_TYPE_SRAM_BANKED: - case FLASHCART_SAVE_TYPE_SRAM_128K: - type = SAVE_TYPE_SRAM_128K; - break; - case FLASHCART_SAVE_TYPE_FLASHRAM: - type = SAVE_TYPE_FLASHRAM; - break; - default: - return FLASHCART_ERROR_ARGS; - } + // ed64_save_type_t type; + + // switch (save_type) { + // case FLASHCART_SAVE_TYPE_NONE: + // type = SAVE_TYPE_NONE; + // break; + // case FLASHCART_SAVE_TYPE_EEPROM_4K: + // type = SAVE_TYPE_EEPROM_4K; + // break; + // case FLASHCART_SAVE_TYPE_EEPROM_16K: + // type = SAVE_TYPE_EEPROM_16K; + // break; + // case FLASHCART_SAVE_TYPE_SRAM: + // type = SAVE_TYPE_SRAM; + // break; + // case FLASHCART_SAVE_TYPE_SRAM_BANKED: + // case FLASHCART_SAVE_TYPE_SRAM_128K: + // type = SAVE_TYPE_SRAM_128K; + // break; + // case FLASHCART_SAVE_TYPE_FLASHRAM: + // type = SAVE_TYPE_FLASHRAM; + // break; + // default: + // return FLASHCART_ERROR_ARGS; + // } // if (ed64_set_config(CFG_SAVE_TYPE, type) != ED64_OK) { // return FLASHCART_ERROR_INT; // } - ed64_bios_set_save_type(type); + // ed64_bios_set_save_type(type); return FLASHCART_OK; } From b17579e6915358e7ff4611fa81dba54cedea69cf Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Mon, 21 Aug 2023 15:05:53 +0100 Subject: [PATCH 32/64] Rename ED64 bios functions remove SPI functions (handled by libCart). --- src/flashcart/ed64/ed64.c | 20 +- src/flashcart/ed64/ed64_ll.c | 360 +++++++++++++++-------------------- src/flashcart/ed64/ed64_ll.h | 82 ++++---- 3 files changed, 193 insertions(+), 269 deletions(-) diff --git a/src/flashcart/ed64/ed64.c b/src/flashcart/ed64/ed64.c index 98945f63..9f577076 100644 --- a/src/flashcart/ed64/ed64.c +++ b/src/flashcart/ed64/ed64.c @@ -16,13 +16,13 @@ static flashcart_error_t ed64_init (void) { - // ed64_bios_unlock_regs(); + // ed64_ll_unlock_regs(); - // ed64_bios_init(); - // ed64_bios_reset_spx(); // only required if V2+ FW is updating! + // ed64_ll_init(); + // ed64_ll_reset_spx(); // only required if V2+ FW is updating! - // ed64_bios_set_ram_bank(1); // Seemingly bank 0 (for SRAM 128k) is only supported on V3 and it is not the default. - // ed64_bios_gpio_mode_io(); + // ed64_ll_set_ram_bank(1); // Seemingly bank 0 (for SRAM 128k) is only supported on V3 and it is not the default. + // ed64_ll_gpio_mode_io(); return FLASHCART_OK; @@ -30,10 +30,10 @@ static flashcart_error_t ed64_init (void) { static flashcart_error_t ed64_deinit (void) { // // NOTE: Necessary because libcart enables ROM write by default - // ed64_set_config(CFG_ROM_WRITE_ENABLE, false); + // ed64_ll_set_config(CFG_ROM_WRITE_ENABLE, false); - // ed64_bios_gpio_mode_off(); // On V3, this should be ed64_bios_gpio_mode_rtc() if it is required. - // ed64_bios_lock_regs(); + // ed64_ll_gpio_mode_off(); // On V3, this should be ed64_bios_gpio_mode_rtc() if it is required. + ed64_ll_lock_regs(); return FLASHCART_OK; } @@ -122,7 +122,7 @@ static flashcart_error_t ed64_load_file (char *file_path, uint32_t rom_offset, u static flashcart_error_t ed64_load_save (char *save_path) { void *address = NULL; -// ed64_save_type_t type = ed64_bios_get_save_type(); +// ed64_save_type_t type = ed64_ll_get_save_type(); // // if (ed64_get_config(CFG_SAVE_TYPE, &type) != ED64_OK) { // // return FLASHCART_ERROR_INT; @@ -199,7 +199,7 @@ static flashcart_error_t ed64_set_save_type (flashcart_save_type_t save_type) { // return FLASHCART_ERROR_INT; // } - // ed64_bios_set_save_type(type); + // ed64_ll_set_save_type(type); return FLASHCART_OK; } diff --git a/src/flashcart/ed64/ed64_ll.c b/src/flashcart/ed64/ed64_ll.c index da9d7ada..fded888e 100644 --- a/src/flashcart/ed64/ed64_ll.c +++ b/src/flashcart/ed64/ed64_ll.c @@ -86,16 +86,16 @@ typedef enum { #define FPGA_FW_DATA_SD_TYPE (1 << 13) #define FPGA_FW_DATA_HOT_START (1 << 14) -uint32_t ed64_bios_reg_read(uint32_t reg); -void ed64_bios_reg_write(uint32_t reg, uint32_t data); -void ed64_bios_dma_pi_read(void * ram_address, unsigned long pi_address, unsigned long length); -void ed64_bios_dma_pi_write(void * ram_address, unsigned long pi_address, unsigned long length); -void ed64_bios_dma_read(void *ram, uint32_t address, uint32_t length); -void ed64_bios_dma_write(void *ram, uint32_t address, uint32_t length); +uint32_t ed64_ll_reg_read(uint32_t reg); +void ed64_ll_reg_write(uint32_t reg, uint32_t data); +void ed64_ll_dma_pi_read(void * ram_address, unsigned long pi_address, unsigned long length); +void ed64_ll_dma_pi_write(void * ram_address, unsigned long pi_address, unsigned long length); +void ed64_ll_dma_read(void *ram, uint32_t address, uint32_t length); +void ed64_ll_dma_write(void *ram, uint32_t address, uint32_t length); -static uint16_t spi_cfg; -uint8_t ed64_bios_ram_bank; -ed64_save_type_t ed64_bios_save_type; +// static uint16_t spi_cfg; +uint8_t ed64_ll_ram_bank; +ed64_save_type_t ed64_ll_save_type; #define REG_LAT 0x04 #define REG_PWD 0x04 @@ -107,57 +107,57 @@ ed64_save_type_t ed64_bios_save_type; /* register functions for V2 & V2.5 (These carts do not support FLASHRAM)*/ /* The end of SDRAM is used for SRAM or FlashRAM save types */ -void ed64_bios_io_reg_v2(uint32_t address, uint32_t data) { +void ed64_ll_io_reg_v2(uint32_t address, uint32_t data) { *(volatile uint32_t *) (ROM_ADDRESS); *(volatile uint32_t *) (ROM_ADDRESS + address) = data; } /* register functions for V3 */ -void ed64_bios_io_reg_v3(uint32_t address, uint16_t data) { +void ed64_ll_io_reg_v3(uint32_t address, uint16_t data) { - ed64_bios_reg_write(REG_FLASHRAM_ADDR, address); - ed64_bios_reg_write(REG_FLASHRAM_DATA, data); + ed64_ll_reg_write(REG_FLASHRAM_ADDR, address); + ed64_ll_reg_write(REG_FLASHRAM_DATA, data); } /* initialize functions (dependent on flashcart version) */ /* Initilize V2 & 2.5 cart */ -void ed64_bios_init_v2() { +void ed64_ll_init_v2() { uint8_t buff[512]; - uint16_t cfg = ed64_bios_reg_read(REG_CFG); + uint16_t cfg = ed64_ll_reg_read(REG_CFG); - ed64_bios_reg_write(REG_CFG, 0); - ed64_bios_io_reg_v2(0xaa / 4 * 4, 0x00980098); - ed64_bios_dma_read_rom(buff, 0, 1); - ed64_bios_io_reg_v2(0xaa / 4 * 4, 0x00f000f0); - ed64_bios_dma_read_rom(buff, 0, 1); - ed64_bios_reg_write(REG_CFG, cfg); + ed64_ll_reg_write(REG_CFG, 0); + ed64_ll_io_reg_v2(0xaa / 4 * 4, 0x00980098); + ed64_ll_dma_read_rom(buff, 0, 1); + ed64_ll_io_reg_v2(0xaa / 4 * 4, 0x00f000f0); + ed64_ll_dma_read_rom(buff, 0, 1); + ed64_ll_reg_write(REG_CFG, cfg); } /* Initilize V3 cart */ -void ed64_bios_init_v3() { +void ed64_ll_init_v3() { uint8_t buff[1024]; - uint16_t cfg = ed64_bios_reg_read(REG_CFG); + uint16_t cfg = ed64_ll_reg_read(REG_CFG); - ed64_bios_reg_write(REG_CFG, 0); - ed64_bios_reg_write(REG_CFG_COUNT, 161); - ed64_bios_io_reg_v3(0x55, 0x98); - ed64_bios_dma_read_rom(buff, 0, 2); - ed64_bios_io_reg_v3(0x55, 0xF0); - ed64_bios_dma_read_rom(buff, 0, 2); - ed64_bios_dma_read_rom(buff, 1024, 2); - ed64_bios_dma_read_rom(buff, 1024 + 256 - 2, 2); - ed64_bios_reg_write(REG_CFG_COUNT, 1); + ed64_ll_reg_write(REG_CFG, 0); + ed64_ll_reg_write(REG_CFG_COUNT, 161); + ed64_ll_io_reg_v3(0x55, 0x98); + ed64_ll_dma_read_rom(buff, 0, 2); + ed64_ll_io_reg_v3(0x55, 0xF0); + ed64_ll_dma_read_rom(buff, 0, 2); + ed64_ll_dma_read_rom(buff, 1024, 2); + ed64_ll_dma_read_rom(buff, 1024 + 256 - 2, 2); + ed64_ll_reg_write(REG_CFG_COUNT, 1); - ed64_bios_reg_write(REG_CFG, cfg); + ed64_ll_reg_write(REG_CFG, cfg); } /* Initialize cart */ -uint8_t ed64_bios_init() { +uint8_t ed64_ll_init() { uint16_t firmware_ver; uint16_t firmware_msg; @@ -168,52 +168,52 @@ uint8_t ed64_bios_init() { IO_WRITE(PI_BSD_DOM2_PWD_REG, REG_PWD); - ed64_bios_reg_write(REG_KEY, ED64_KEY_UNLOCK); - ed64_bios_reg_write(REG_CFG, 0x0000); + ed64_ll_reg_write(REG_KEY, ED64_KEY_UNLOCK); + ed64_ll_reg_write(REG_CFG, 0x0000); - firmware_msg = ed64_bios_reg_read(REG_FPGA_FW_DATA); + firmware_msg = ed64_ll_reg_read(REG_FPGA_FW_DATA); cold_start = (firmware_msg & FPGA_FW_DATA_HOT_START) == 0 ? 1 : 0; if (cold_start) { firmware_msg |= FPGA_FW_DATA_HOT_START; - ed64_bios_reg_write(REG_FPGA_FW_DATA, firmware_msg); + ed64_ll_reg_write(REG_FPGA_FW_DATA, firmware_msg); } - firmware_ver = ed64_bios_reg_read(REG_FPGA_FW_VER); + firmware_ver = ed64_ll_reg_read(REG_FPGA_FW_VER); if ((firmware_ver & 0xf000) >= 0x2000) { - ed64_bios_init_v3(); + ed64_ll_init_v3(); } else { - ed64_bios_init_v2(); + ed64_ll_init_v2(); } - spi_cfg = SPI_CFG_SS | BI_SPI_SPD_LO; - ed64_bios_reg_write(REG_CFG, ED_CFG_SDRAM_ON); - ed64_bios_reg_write(REG_SPI_CFG, spi_cfg); - ed64_bios_save_type = SAVE_TYPE_NONE; + //spi_cfg = SPI_CFG_SS | BI_SPI_SPD_LO; + ed64_ll_reg_write(REG_CFG, ED_CFG_SDRAM_ON); + //ed64_ll_reg_write(REG_SPI_CFG, spi_cfg); + ed64_ll_save_type = SAVE_TYPE_NONE; return cold_start; } -void ed64_bios_reset_spx() { +void ed64_ll_reset_spx() { - uint16_t cfg = ed64_bios_reg_read(REG_CFG); + uint16_t cfg = ed64_ll_reg_read(REG_CFG); - ed64_bios_reg_write(REG_CFG, 0x8000); + ed64_ll_reg_write(REG_CFG, 0x8000); wait_ms(100); - ed64_bios_reg_write(REG_CFG, cfg); + ed64_ll_reg_write(REG_CFG, cfg); wait_ms(100); } -uint32_t ed64_bios_reg_read(uint32_t reg) { +uint32_t ed64_ll_reg_read(uint32_t reg) { *(volatile uint32_t *) (ED64_REGS_BASE); return *(volatile uint32_t *) (ED64_REGS_BASE + reg * 4); } -void ed64_bios_reg_write(uint32_t reg, uint32_t data) { +void ed64_ll_reg_write(uint32_t reg, uint32_t data) { *(volatile uint32_t *) (ED64_REGS_BASE); *(volatile uint32_t *) (ED64_REGS_BASE + reg * 4) = data; @@ -222,133 +222,73 @@ void ed64_bios_reg_write(uint32_t reg, uint32_t data) { } /* Used for USB and SPI functions */ -uint8_t ed64_bios_dma_busy() { +uint8_t ed64_ll_dma_busy() { - while ((ed64_bios_reg_read(REG_STATUS) & STATE_DMA_BUSY) != 0); - return ed64_bios_reg_read(REG_STATUS) & STATE_DMA_TOUT; + while ((ed64_ll_reg_read(REG_STATUS) & STATE_DMA_BUSY) != 0); + return ed64_ll_reg_read(REG_STATUS) & STATE_DMA_TOUT; } /* USB functions */ /* USB read is busy */ -uint8_t ed64_bios_usb_read_busy() { +uint8_t ed64_ll_usb_read_busy() { - return ed64_bios_reg_read(REG_STATUS) & STATE_USB_RXF; + return ed64_ll_reg_read(REG_STATUS) & STATE_USB_RXF; } /* USB write is busy */ -uint8_t ed64_bios_usb_write_busy() { +uint8_t ed64_ll_usb_write_busy() { - return ed64_bios_reg_read(REG_STATUS) & STATE_USB_TXE; + return ed64_ll_reg_read(REG_STATUS) & STATE_USB_TXE; } /* USB read */ -uint8_t ed64_bios_usb_read(uint32_t start_address, uint32_t slen) { +uint8_t ed64_ll_usb_read(uint32_t start_address, uint32_t slen) { start_address /= 4; - while (ed64_bios_usb_read_busy() != 0); + while (ed64_ll_usb_read_busy() != 0); - ed64_bios_reg_write(REG_DMA_LENGTH, slen - 1); - ed64_bios_reg_write(REG_DMA_RAM_ADDR, start_address); - ed64_bios_reg_write(REG_DMA_CFG, DCFG_USB_TO_RAM); + ed64_ll_reg_write(REG_DMA_LENGTH, slen - 1); + ed64_ll_reg_write(REG_DMA_RAM_ADDR, start_address); + ed64_ll_reg_write(REG_DMA_CFG, DCFG_USB_TO_RAM); - if (ed64_bios_dma_busy() != 0)return USB_ERROR_FIFO_TIMEOUT; + if (ed64_ll_dma_busy() != 0)return USB_ERROR_FIFO_TIMEOUT; return 0; } /* USB write */ -uint8_t ed64_bios_usb_write(uint32_t start_address, uint32_t slen) { +uint8_t ed64_ll_usb_write(uint32_t start_address, uint32_t slen) { start_address /= 4; - while (ed64_bios_usb_write_busy() != 0); + while (ed64_ll_usb_write_busy() != 0); - ed64_bios_reg_write(REG_DMA_LENGTH, slen - 1); - ed64_bios_reg_write(REG_DMA_RAM_ADDR, start_address); - ed64_bios_reg_write(REG_DMA_CFG, DCFG_RAM_TO_USB); + ed64_ll_reg_write(REG_DMA_LENGTH, slen - 1); + ed64_ll_reg_write(REG_DMA_RAM_ADDR, start_address); + ed64_ll_reg_write(REG_DMA_CFG, DCFG_RAM_TO_USB); - if (ed64_bios_dma_busy() != 0)return USB_ERROR_FIFO_TIMEOUT; + if (ed64_ll_dma_busy() != 0)return USB_ERROR_FIFO_TIMEOUT; return 0; } -/* SPI functions */ +ed64_save_type_t ed64_ll_get_save_type() { -uint16_t ed64_bios_spi_busy() { - - return ed64_bios_reg_read(REG_STATUS) & STATE_DMA_BUSY; -} - -uint8_t ed64_bios_spi(uint8_t data) { - - ed64_bios_reg_write(REG_SPI, data); - while (ed64_bios_spi_busy()); - return ed64_bios_reg_read(REG_SPI); -} - -/* never returns (or is it never reads???) */ -void ed64_bios_spi_nr(uint8_t data) { - - ed64_bios_reg_write(REG_SPI, data); - while (ed64_bios_spi_busy()); -} - -void ed64_bios_set_spi_speed(uint16_t speed) { - - spi_cfg &= ~3; - spi_cfg |= speed; - ed64_bios_reg_write(REG_SPI_CFG, spi_cfg); -} - -void ed64_bios_sd_mode(uint16_t mode) { - - spi_cfg &= ~(SPI_CFG_1BIT | SPI_CFG_RD | SPI_CFG_DAT); - spi_cfg |= mode; - ed64_bios_reg_write(REG_SPI_CFG, spi_cfg); -} - -uint8_t ed64_bios_spi_read_to_rom(uint32_t start_address, uint16_t slen) { - - start_address /= 4; - - ed64_bios_reg_write(REG_DMA_LENGTH, slen - 1); - ed64_bios_reg_write(REG_DMA_RAM_ADDR, start_address); - ed64_bios_reg_write(REG_DMA_CFG, DCFG_SD_TO_RAM); - - if (ed64_bios_dma_busy() != 0)return EVD_ERROR_MMC_TIMEOUT; - - return 0; -} - -void ed64_bios_byteswap_on() { - uint16_t cfg = ed64_bios_reg_read(REG_CFG); - cfg |= ED_CFG_BYTESWAP_ON; - ed64_bios_reg_write(REG_CFG, cfg); -} - -void ed64_bios_byteswap_off() { - uint16_t cfg = ed64_bios_reg_read(REG_CFG); - cfg &= ~ED_CFG_BYTESWAP_ON; - ed64_bios_reg_write(REG_CFG, cfg); -} - -ed64_save_type_t ed64_bios_get_save_type() { - - return ed64_bios_save_type; + return ed64_ll_save_type; } -void ed64_bios_set_save_type(ed64_save_type_t type) { +void ed64_ll_set_save_type(ed64_save_type_t type) { uint16_t save_cfg; uint8_t eeprom_on, sram_on, eeprom_size, sram_size, ram_bank; - ed64_bios_save_type = type; + ed64_ll_save_type = type; eeprom_on = 0; sram_on = 0; eeprom_size = 0; sram_size = 0; - ram_bank = ed64_bios_ram_bank; + ram_bank = ed64_ll_ram_bank; switch (type) { @@ -385,25 +325,25 @@ void ed64_bios_set_save_type(ed64_save_type_t type) { if (ram_bank)save_cfg |= SAV_RAM_BANK; save_cfg |= SAV_RAM_BANK_APPLY; - ed64_bios_reg_write(REG_SAV_CFG, save_cfg); + ed64_ll_reg_write(REG_SAV_CFG, save_cfg); } -void ed64_bios_set_ram_bank(uint8_t bank) { +void ed64_ll_set_ram_bank(uint8_t bank) { - ed64_bios_ram_bank = bank == 0 ? 0 : 1; + ed64_ll_ram_bank = bank == 0 ? 0 : 1; } /* reads metadata related to the assembily date and cart capabilities */ -void ed64_bios_read_cart_metadata(void *dest) { +void ed64_ll_read_cart_metadata(void *dest) { - uint16_t cfg = ed64_bios_reg_read(REG_CFG); + uint16_t cfg = ed64_ll_reg_read(REG_CFG); cfg &= ~ED_CFG_SDRAM_ON; - ed64_bios_reg_write(REG_CFG, cfg); + ed64_ll_reg_write(REG_CFG, cfg); - ed64_bios_dma_read_rom(dest, 0, 1); + ed64_ll_dma_read_rom(dest, 0, 1); // assembily_date = (buff[0x38] << 8) | buff[0x39]; // assembily_time = (buff[0x3A] << 8) | buff[0x3B]; @@ -412,22 +352,22 @@ void ed64_bios_read_cart_metadata(void *dest) { cfg |= ED_CFG_SDRAM_ON; - ed64_bios_reg_write(REG_CFG, cfg); + ed64_ll_reg_write(REG_CFG, cfg); } -void ed64_bios_dma_read_rom(void *ram, uint32_t start_address, uint32_t slen) { +void ed64_ll_dma_read_rom(void *ram, uint32_t start_address, uint32_t slen) { - ed64_bios_dma_read(ram, ROM_ADDRESS + start_address * 512, slen * 512); + ed64_ll_dma_read(ram, ROM_ADDRESS + start_address * 512, slen * 512); } -void ed64_bios_dma_write_rom(void *ram, uint32_t start_address, uint32_t slen) { +void ed64_ll_dma_write_rom(void *ram, uint32_t start_address, uint32_t slen) { - ed64_bios_dma_write(ram, ROM_ADDRESS + start_address * 512, slen * 512); + ed64_ll_dma_write(ram, ROM_ADDRESS + start_address * 512, slen * 512); } /* Read from SRAM over DMA */ -void ed64_bios_dma_read_sram(void *ram, uint32_t address, uint32_t length) { +void ed64_ll_dma_read_sram(void *ram, uint32_t address, uint32_t length) { volatile uint32_t piLatReg = IO_READ(PI_BSD_DOM2_LAT_REG); volatile uint32_t piPwdReg = IO_READ(PI_BSD_DOM2_PWD_REG); @@ -439,7 +379,7 @@ void ed64_bios_dma_read_sram(void *ram, uint32_t address, uint32_t length) { IO_WRITE(PI_BSD_DOM2_LAT_REG, 0x05); IO_WRITE(PI_BSD_DOM2_PWD_REG, 0x0C); - ed64_bios_dma_read(ram, SRAM_ADDRESS + address, length); + ed64_ll_dma_read(ram, SRAM_ADDRESS + address, length); IO_WRITE(PI_BSD_DOM2_LAT_REG, piLatReg); IO_WRITE(PI_BSD_DOM2_PWD_REG, piPwdReg); @@ -448,7 +388,7 @@ void ed64_bios_dma_read_sram(void *ram, uint32_t address, uint32_t length) { } /* Write to SRAM over DMA */ -void ed64_bios_dma_write_sram(void *ram, uint32_t address, uint32_t length) { +void ed64_ll_dma_write_sram(void *ram, uint32_t address, uint32_t length) { volatile uint32_t piLatReg = IO_READ(PI_BSD_DOM2_LAT_REG); volatile uint32_t piPwdReg = IO_READ(PI_BSD_DOM2_PWD_REG); @@ -460,7 +400,7 @@ void ed64_bios_dma_write_sram(void *ram, uint32_t address, uint32_t length) { IO_WRITE(PI_BSD_DOM2_LAT_REG, 0x05); IO_WRITE(PI_BSD_DOM2_PWD_REG, 0x0C); - ed64_bios_dma_write(ram, SRAM_ADDRESS + address, length); + ed64_ll_dma_write(ram, SRAM_ADDRESS + address, length); IO_WRITE(PI_BSD_DOM2_LAT_REG, piLatReg); @@ -470,14 +410,14 @@ void ed64_bios_dma_write_sram(void *ram, uint32_t address, uint32_t length) { } -uint16_t ed64_bios_msg_rd() { +uint16_t ed64_ll_msg_rd() { - return ed64_bios_reg_read(REG_MSG); + return ed64_ll_reg_read(REG_MSG); } -void ed64_bios_msg_wr(uint16_t val) { +void ed64_ll_msg_wr(uint16_t val) { - ed64_bios_reg_write(REG_MSG, val); + ed64_ll_reg_write(REG_MSG, val); } typedef struct PI_regs_s { @@ -495,7 +435,7 @@ typedef struct PI_regs_s { static volatile struct PI_regs_s * const PI_regs = (struct PI_regs_s *) PI_BASE_REG; -void ed64_bios_dma_pi_read(void * ram_address, unsigned long pi_address, unsigned long length) { +void ed64_ll_dma_pi_read(void * ram_address, unsigned long pi_address, unsigned long length) { disable_interrupts(); dma_wait(); @@ -508,7 +448,7 @@ void ed64_bios_dma_pi_read(void * ram_address, unsigned long pi_address, unsigne enable_interrupts(); } -void ed64_bios_dma_pi_write(void * ram_address, unsigned long pi_address, unsigned long length) { +void ed64_ll_dma_pi_write(void * ram_address, unsigned long pi_address, unsigned long length) { disable_interrupts(); dma_wait(); @@ -520,63 +460,63 @@ void ed64_bios_dma_pi_write(void * ram_address, unsigned long pi_address, unsign enable_interrupts(); } -void ed64_bios_dma_read(void *ram, uint32_t address, uint32_t length) { +void ed64_ll_dma_read(void *ram, uint32_t address, uint32_t length) { if (((uint32_t) ram & 0xF0000000) == 0x80000000) { data_cache_hit_writeback_invalidate(ram, length); - ed64_bios_dma_pi_read(ram, address, length); + ed64_ll_dma_pi_read(ram, address, length); } else { - ed64_bios_dma_pi_read(ram, address, length); + ed64_ll_dma_pi_read(ram, address, length); } } -void ed64_bios_dma_write(void *ram, uint32_t address, uint32_t length) { +void ed64_ll_dma_write(void *ram, uint32_t address, uint32_t length) { if (((uint32_t) ram & 0xF0000000) == 0x80000000)data_cache_hit_writeback(ram, length); - ed64_bios_dma_pi_write(ram, address, length); + ed64_ll_dma_pi_write(ram, address, length); } /** @brief Get the current FPGA version */ -uint16_t ed64_bios_get_fpga_version() { +uint16_t ed64_ll_get_fpga_version() { - return ed64_bios_reg_read(REG_FPGA_VERSION); + return ed64_ll_reg_read(REG_FPGA_VERSION); } /** @brief Get the current CPLD version */ -uint16_t ed64_bios_get_cpld_version() { +uint16_t ed64_ll_get_cpld_version() { uint16_t cpld_version; - uint16_t cfg = ed64_bios_reg_read(REG_CFG); + uint16_t cfg = ed64_ll_reg_read(REG_CFG); - ed64_bios_reg_write(REG_CFG, 0); - cpld_version = ed64_bios_reg_read(REG_FPGA_FW_VER); - ed64_bios_reg_write(REG_CFG, cfg); + ed64_ll_reg_write(REG_CFG, 0); + cpld_version = ed64_ll_reg_read(REG_FPGA_FW_VER); + ed64_ll_reg_write(REG_CFG, cfg); return cpld_version; } /* Load the specified FPGA firmware */ -void ed64_bios_load_firmware(uint8_t *firmware) { +void ed64_ll_load_firmware(uint8_t *firmware) { uint32_t i; uint16_t f_ctr = 0; - uint16_t cfg = ed64_bios_reg_read(REG_CFG); + uint16_t cfg = ed64_ll_reg_read(REG_CFG); cfg &= ~ED_CFG_SDRAM_ON; - ed64_bios_reg_write(REG_CFG, cfg); + ed64_ll_reg_write(REG_CFG, cfg); - ed64_bios_reg_write(REG_CFG_COUNT, 0); + ed64_ll_reg_write(REG_CFG_COUNT, 0); wait_ms(10); - ed64_bios_reg_write(REG_CFG_COUNT, 1); + ed64_ll_reg_write(REG_CFG_COUNT, 1); wait_ms(10); i = 0; for (;;) { - ed64_bios_reg_write(REG_CFG_DATA, *(uint16_t *) & firmware[i]); - while ((ed64_bios_reg_read(REG_CFG_COUNT) & 8) != 0); + ed64_ll_reg_write(REG_CFG_DATA, *(uint16_t *) & firmware[i]); + while ((ed64_ll_reg_read(REG_CFG_COUNT) & 8) != 0); f_ctr = firmware[i++] == 0xff ? f_ctr + 1 : 0; if (f_ctr >= 47)break; @@ -585,9 +525,9 @@ void ed64_bios_load_firmware(uint8_t *firmware) { } - while ((ed64_bios_reg_read(REG_CFG_COUNT) & 4) == 0) { - ed64_bios_reg_write(REG_CFG_DATA, 0xffff); - while ((ed64_bios_reg_read(REG_CFG_COUNT) & 8) != 0); + while ((ed64_ll_reg_read(REG_CFG_COUNT) & 4) == 0) { + ed64_ll_reg_write(REG_CFG_DATA, 0xffff); + while ((ed64_ll_reg_read(REG_CFG_COUNT) & 8) != 0); } @@ -595,52 +535,52 @@ void ed64_bios_load_firmware(uint8_t *firmware) { } -void ed64_bios_lock_regs() { - ed64_bios_reg_write(REG_KEY, ED64_KEY_LOCK); +void ed64_ll_lock_regs() { + ed64_ll_reg_write(REG_KEY, ED64_KEY_LOCK); } -void ed64_bios_unlock_regs() { - ed64_bios_reg_write(REG_KEY, ED64_KEY_UNLOCK); +void ed64_ll_unlock_regs() { + ed64_ll_reg_write(REG_KEY, ED64_KEY_UNLOCK); } /* GPIO functions */ /* Set GPIO mode RTC */ -void ed64_bios_gpio_mode_rtc() { +void ed64_ll_gpio_mode_rtc() { - uint16_t cfg = ed64_bios_reg_read(REG_CFG); + uint16_t cfg = ed64_ll_reg_read(REG_CFG); cfg &= ~ED_CFG_GPIO_ON; cfg |= ED_CFG_RTC_ON; - ed64_bios_reg_write(REG_CFG, cfg); + ed64_ll_reg_write(REG_CFG, cfg); } /* Set GPIO mode ON */ -void ed64_bios_gpio_mode_io() { +void ed64_ll_gpio_mode_io() { - uint16_t cfg = ed64_bios_reg_read(REG_CFG); + uint16_t cfg = ed64_ll_reg_read(REG_CFG); cfg |= ED_CFG_GPIO_ON; - ed64_bios_reg_write(REG_CFG, cfg); + ed64_ll_reg_write(REG_CFG, cfg); } /* Set GPIO mode OFF */ -void ed64_bios_gpio_mode_off() { +void ed64_ll_gpio_mode_off() { - uint16_t cfg = ed64_bios_reg_read(REG_CFG); + uint16_t cfg = ed64_ll_reg_read(REG_CFG); cfg &= ~ED_CFG_GPIO_ON; - ed64_bios_reg_write(REG_CFG, cfg); + ed64_ll_reg_write(REG_CFG, cfg); } /* GPIO mode write */ -void ed64_bios_gpio_write(uint8_t data) { +void ed64_ll_gpio_write(uint8_t data) { - ed64_bios_reg_write(REG_GPIO, data); + ed64_ll_reg_write(REG_GPIO, data); } /* GPIO mode read */ -uint8_t ed64_bios_gpio_read() { +uint8_t ed64_ll_gpio_read() { - return ed64_bios_reg_read(REG_GPIO); + return ed64_ll_reg_read(REG_GPIO); } @@ -648,43 +588,43 @@ uint8_t ed64_bios_gpio_read() { /* 64DD cart conversion save functions */ /* Set 64DD ON and Enabled?! */ -void ed64_bios_64dd_ram_oe() { +void ed64_ll_64dd_ram_oe() { - uint16_t cfg = ed64_bios_reg_read(REG_CFG); + uint16_t cfg = ed64_ll_reg_read(REG_CFG); cfg &= ~ED_CFG_64DD_WRITE_ENABLED; cfg |= ED_CFG_64DD_ON; - ed64_bios_reg_write(REG_CFG, cfg); + ed64_ll_reg_write(REG_CFG, cfg); } /* Set 64DD Write Enable?? */ -void ed64_bios_64dd_ram_we() { +void ed64_ll_64dd_ram_we() { - uint16_t cfg = ed64_bios_reg_read(REG_CFG); + uint16_t cfg = ed64_ll_reg_read(REG_CFG); cfg |= ED_CFG_64DD_ON | ED_CFG_64DD_WRITE_ENABLED; - ed64_bios_reg_write(REG_CFG, cfg); + ed64_ll_reg_write(REG_CFG, cfg); } /* Set 64DD Disabled?? */ -void ed64_bios_64dd_ram_off() { +void ed64_ll_64dd_ram_off() { - uint16_t cfg = ed64_bios_reg_read(REG_CFG); + uint16_t cfg = ed64_ll_reg_read(REG_CFG); cfg &= ~(ED_CFG_64DD_ON | ED_CFG_64DD_WRITE_ENABLED); - ed64_bios_reg_write(REG_CFG, cfg); + ed64_ll_reg_write(REG_CFG, cfg); } /* 64DD Save RAM Clear */ -void ed64_bios_64dd_ram_clear() { +void ed64_ll_64dd_ram_clear() { - uint16_t cfg = ed64_bios_reg_read(REG_CFG); + uint16_t cfg = ed64_ll_reg_read(REG_CFG); cfg |= ED_CFG_64DD_WRITE_ENABLED; cfg &= ~ED_CFG_64DD_ON; - ed64_bios_reg_write(REG_CFG, cfg); + ed64_ll_reg_write(REG_CFG, cfg); wait_ms(100); } /* 64DD Allowed on this cart?! */ -uint8_t ed64_bios_get_64dd_ram_supported() { +uint8_t ed64_ll_get_64dd_ram_supported() { - return (ed64_bios_reg_read(REG_STATUS) >> 15) & 1; + return (ed64_ll_reg_read(REG_STATUS) >> 15) & 1; } diff --git a/src/flashcart/ed64/ed64_ll.h b/src/flashcart/ed64/ed64_ll.h index b140c2da..f5c9c01c 100644 --- a/src/flashcart/ed64/ed64_ll.h +++ b/src/flashcart/ed64/ed64_ll.h @@ -82,11 +82,6 @@ typedef struct { #define IO_WRITE(addr,data) (*(volatile uint32_t *)PHYS_TO_K1(addr)=(uint32_t)(data)) #define IO_READ(addr) (*(volatile uint32_t *)PHYS_TO_K1(addr)) -typedef enum { - BI_SPI_SPD_50 = 0, - BI_SPI_SPD_25 = 1, - BI_SPI_SPD_LO = 2, -} ed64_spi_speed_t; #define SPI_CFG_SPD0 1 #define SPI_CFG_SPD1 2 @@ -96,69 +91,58 @@ typedef enum { #define SPI_CFG_1BIT 32 /* Initialization functions */ -uint8_t ed64_bios_init(); -void ed64_bios_init_v2(); -void ed64_bios_init_v3(); +uint8_t ed64_ll_init(); +void ed64_ll_init_v2(); +void ed64_ll_init_v3(); /* Device information functions */ -uint16_t ed64_bios_get_fpga_version(); -uint16_t ed64_bios_get_cpld_version(); +uint16_t ed64_ll_get_fpga_version(); +uint16_t ed64_ll_get_cpld_version(); /* Firmware update functions */ -void ed64_bios_load_firmware(uint8_t *firmware); +void ed64_ll_load_firmware(uint8_t *firmware); /* USB functions */ -uint8_t ed64_bios_usb_read_busy(); -uint8_t ed64_bios_usb_read(uint32_t start_address, uint32_t slen); -uint8_t ed64_bios_usb_write(uint32_t start_address, uint32_t slen); - -/* SPI functions */ -uint8_t ed64_bios_spi(uint8_t data); -void ed64_bios_spi_nr(uint8_t data); -void ed64_bios_set_spi_speed(uint16_t speed); - -/* SD Card functions */ -void ed64_bios_sd_mode(uint16_t mode); -uint8_t ed64_bios_spi_read_to_rom(uint32_t start_address, uint16_t slen); -void ed64_bios_byteswap_on(); -void ed64_bios_byteswap_off(); +uint8_t ed64_ll_usb_read_busy(); +uint8_t ed64_ll_usb_read(uint32_t start_address, uint32_t slen); +uint8_t ed64_ll_usb_write(uint32_t start_address, uint32_t slen); /* Save functions */ -void ed64_bios_set_ram_bank(uint8_t bank); -ed64_save_type_t ed64_bios_get_save_type(); -void ed64_bios_set_save_type(ed64_save_type_t type); +void ed64_ll_set_ram_bank(uint8_t bank); +ed64_save_type_t ed64_ll_get_save_type(); +void ed64_ll_set_save_type(ed64_save_type_t type); /* reads metadata related to the assembily date and cart capabilities */ -void ed64_bios_read_cart_metadata(void *dest); +void ed64_ll_read_cart_metadata(void *dest); -uint16_t ed64_bios_msg_rd(); -void ed64_bios_msg_wr(uint16_t val); +uint16_t ed64_ll_msg_rd(); +void ed64_ll_msg_wr(uint16_t val); /* DMA functions */ -void ed64_bios_dma_read_rom(void *ram, uint32_t start_address, uint32_t slen); -void ed64_bios_dma_write_rom(void *ram, uint32_t start_address, uint32_t slen); -void ed64_bios_dma_read_sram(void *ram, uint32_t address, uint32_t length); -void ed64_bios_dma_write_sram(void *ram, uint32_t address, uint32_t length); +void ed64_ll_dma_read_rom(void *ram, uint32_t start_address, uint32_t slen); +void ed64_ll_dma_write_rom(void *ram, uint32_t start_address, uint32_t slen); +void ed64_ll_dma_read_sram(void *ram, uint32_t address, uint32_t length); +void ed64_ll_dma_write_sram(void *ram, uint32_t address, uint32_t length); -void ed64_bios_lock_regs(); -void ed64_bios_unlock_regs(); +void ed64_ll_lock_regs(); +void ed64_ll_unlock_regs(); -uint32_t ed64_bios_reg_read(uint32_t reg); -void ed64_bios_reg_write(uint32_t reg, uint32_t data); -void ed64_bios_reset_spx(); +uint32_t ed64_ll_reg_read(uint32_t reg); +void ed64_ll_reg_write(uint32_t reg, uint32_t data); +void ed64_ll_reset_spx(); /* GPIO functions */ -void ed64_bios_gpio_mode_rtc(); -void ed64_bios_gpio_mode_io(); -void ed64_bios_gpio_mode_off(); -uint8_t ed64_bios_gpio_read(); +void ed64_ll_gpio_mode_rtc(); +void ed64_ll_gpio_mode_io(); +void ed64_ll_gpio_mode_off(); +uint8_t ed64_ll_gpio_read(); /* 64DD cart conversion save functions */ -void ed64_bios_64dd_ram_oe(); -void ed64_bios_64dd_ram_we(); -void ed64_bios_64dd_ram_off(); -void ed64_bios_64dd_ram_clear(); -uint8_t ed64_bios_get_64dd_ram_supported(); +void ed64_ll_64dd_ram_oe(); +void ed64_ll_64dd_ram_we(); +void ed64_ll_64dd_ram_off(); +void ed64_ll_64dd_ram_clear(); +uint8_t ed64_ll_get_64dd_ram_supported(); /** @} */ /* ed64 */ From 54ae9daec5731accc37d93dae146f10262ab2b31 Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Mon, 21 Aug 2023 16:07:58 +0100 Subject: [PATCH 33/64] Enable save type set --- src/flashcart/ed64/ed64.c | 62 ++++++++-------- src/flashcart/ed64/ed64_ll.c | 132 +++++++++++++++++------------------ 2 files changed, 99 insertions(+), 95 deletions(-) diff --git a/src/flashcart/ed64/ed64.c b/src/flashcart/ed64/ed64.c index 9f577076..380c1271 100644 --- a/src/flashcart/ed64/ed64.c +++ b/src/flashcart/ed64/ed64.c @@ -16,12 +16,16 @@ static flashcart_error_t ed64_init (void) { - // ed64_ll_unlock_regs(); + ed64_ll_unlock_regs(); - // ed64_ll_init(); + // ed64_ll_init(); // FIXME: this causes a crash! // ed64_ll_reset_spx(); // only required if V2+ FW is updating! // ed64_ll_set_ram_bank(1); // Seemingly bank 0 (for SRAM 128k) is only supported on V3 and it is not the default. + + // If a V3 cart is detected (has a battery?), enable RTC, + // ed64_ll_gpio_mode_rtc(); + // otherwise: // ed64_ll_gpio_mode_io(); @@ -32,7 +36,7 @@ static flashcart_error_t ed64_deinit (void) { // // NOTE: Necessary because libcart enables ROM write by default // ed64_ll_set_config(CFG_ROM_WRITE_ENABLE, false); - // ed64_ll_gpio_mode_off(); // On V3, this should be ed64_bios_gpio_mode_rtc() if it is required. + ed64_ll_gpio_mode_off(); // On V3, this should be ed64_bios_gpio_mode_rtc() if it is required. ed64_ll_lock_regs(); return FLASHCART_OK; @@ -169,37 +173,37 @@ static flashcart_error_t ed64_load_save (char *save_path) { } static flashcart_error_t ed64_set_save_type (flashcart_save_type_t save_type) { - // ed64_save_type_t type; - - // switch (save_type) { - // case FLASHCART_SAVE_TYPE_NONE: - // type = SAVE_TYPE_NONE; - // break; - // case FLASHCART_SAVE_TYPE_EEPROM_4K: - // type = SAVE_TYPE_EEPROM_4K; - // break; - // case FLASHCART_SAVE_TYPE_EEPROM_16K: - // type = SAVE_TYPE_EEPROM_16K; - // break; - // case FLASHCART_SAVE_TYPE_SRAM: - // type = SAVE_TYPE_SRAM; - // break; - // case FLASHCART_SAVE_TYPE_SRAM_BANKED: - // case FLASHCART_SAVE_TYPE_SRAM_128K: - // type = SAVE_TYPE_SRAM_128K; - // break; - // case FLASHCART_SAVE_TYPE_FLASHRAM: - // type = SAVE_TYPE_FLASHRAM; - // break; - // default: - // return FLASHCART_ERROR_ARGS; - // } + ed64_save_type_t type; + + switch (save_type) { + case FLASHCART_SAVE_TYPE_NONE: + type = SAVE_TYPE_NONE; + break; + case FLASHCART_SAVE_TYPE_EEPROM_4K: + type = SAVE_TYPE_EEPROM_4K; + break; + case FLASHCART_SAVE_TYPE_EEPROM_16K: + type = SAVE_TYPE_EEPROM_16K; + break; + case FLASHCART_SAVE_TYPE_SRAM: + type = SAVE_TYPE_SRAM; + break; + case FLASHCART_SAVE_TYPE_SRAM_BANKED: + case FLASHCART_SAVE_TYPE_SRAM_128K: + type = SAVE_TYPE_SRAM_128K; + break; + case FLASHCART_SAVE_TYPE_FLASHRAM: + type = SAVE_TYPE_FLASHRAM; + break; + default: + return FLASHCART_ERROR_ARGS; + } // if (ed64_set_config(CFG_SAVE_TYPE, type) != ED64_OK) { // return FLASHCART_ERROR_INT; // } - // ed64_ll_set_save_type(type); + ed64_ll_set_save_type(type); return FLASHCART_OK; } diff --git a/src/flashcart/ed64/ed64_ll.c b/src/flashcart/ed64/ed64_ll.c index fded888e..25d6343d 100644 --- a/src/flashcart/ed64/ed64_ll.c +++ b/src/flashcart/ed64/ed64_ll.c @@ -221,57 +221,57 @@ void ed64_ll_reg_write(uint32_t reg, uint32_t data) { } -/* Used for USB and SPI functions */ -uint8_t ed64_ll_dma_busy() { +// /* Used for USB and SPI functions */ +// uint8_t ed64_ll_dma_busy() { - while ((ed64_ll_reg_read(REG_STATUS) & STATE_DMA_BUSY) != 0); - return ed64_ll_reg_read(REG_STATUS) & STATE_DMA_TOUT; -} +// while ((ed64_ll_reg_read(REG_STATUS) & STATE_DMA_BUSY) != 0); +// return ed64_ll_reg_read(REG_STATUS) & STATE_DMA_TOUT; +// } -/* USB functions */ +// /* USB functions */ -/* USB read is busy */ -uint8_t ed64_ll_usb_read_busy() { +// /* USB read is busy */ +// uint8_t ed64_ll_usb_read_busy() { - return ed64_ll_reg_read(REG_STATUS) & STATE_USB_RXF; -} +// return ed64_ll_reg_read(REG_STATUS) & STATE_USB_RXF; +// } -/* USB write is busy */ -uint8_t ed64_ll_usb_write_busy() { +// /* USB write is busy */ +// uint8_t ed64_ll_usb_write_busy() { - return ed64_ll_reg_read(REG_STATUS) & STATE_USB_TXE; -} +// return ed64_ll_reg_read(REG_STATUS) & STATE_USB_TXE; +// } -/* USB read */ -uint8_t ed64_ll_usb_read(uint32_t start_address, uint32_t slen) { +// /* USB read */ +// uint8_t ed64_ll_usb_read(uint32_t start_address, uint32_t slen) { - start_address /= 4; - while (ed64_ll_usb_read_busy() != 0); +// start_address /= 4; +// while (ed64_ll_usb_read_busy() != 0); - ed64_ll_reg_write(REG_DMA_LENGTH, slen - 1); - ed64_ll_reg_write(REG_DMA_RAM_ADDR, start_address); - ed64_ll_reg_write(REG_DMA_CFG, DCFG_USB_TO_RAM); +// ed64_ll_reg_write(REG_DMA_LENGTH, slen - 1); +// ed64_ll_reg_write(REG_DMA_RAM_ADDR, start_address); +// ed64_ll_reg_write(REG_DMA_CFG, DCFG_USB_TO_RAM); - if (ed64_ll_dma_busy() != 0)return USB_ERROR_FIFO_TIMEOUT; +// if (ed64_ll_dma_busy() != 0)return USB_ERROR_FIFO_TIMEOUT; - return 0; -} +// return 0; +// } -/* USB write */ -uint8_t ed64_ll_usb_write(uint32_t start_address, uint32_t slen) { +// /* USB write */ +// uint8_t ed64_ll_usb_write(uint32_t start_address, uint32_t slen) { - start_address /= 4; - while (ed64_ll_usb_write_busy() != 0); +// start_address /= 4; +// while (ed64_ll_usb_write_busy() != 0); - ed64_ll_reg_write(REG_DMA_LENGTH, slen - 1); - ed64_ll_reg_write(REG_DMA_RAM_ADDR, start_address); - ed64_ll_reg_write(REG_DMA_CFG, DCFG_RAM_TO_USB); +// ed64_ll_reg_write(REG_DMA_LENGTH, slen - 1); +// ed64_ll_reg_write(REG_DMA_RAM_ADDR, start_address); +// ed64_ll_reg_write(REG_DMA_CFG, DCFG_RAM_TO_USB); - if (ed64_ll_dma_busy() != 0)return USB_ERROR_FIFO_TIMEOUT; +// if (ed64_ll_dma_busy() != 0)return USB_ERROR_FIFO_TIMEOUT; - return 0; -} +// return 0; +// } ed64_save_type_t ed64_ll_get_save_type() { @@ -585,46 +585,46 @@ uint8_t ed64_ll_gpio_read() { -/* 64DD cart conversion save functions */ +// /* 64DD cart conversion save functions */ -/* Set 64DD ON and Enabled?! */ -void ed64_ll_64dd_ram_oe() { +// /* Set 64DD ON and Enabled?! */ +// void ed64_ll_64dd_ram_oe() { - uint16_t cfg = ed64_ll_reg_read(REG_CFG); - cfg &= ~ED_CFG_64DD_WRITE_ENABLED; - cfg |= ED_CFG_64DD_ON; - ed64_ll_reg_write(REG_CFG, cfg); -} +// uint16_t cfg = ed64_ll_reg_read(REG_CFG); +// cfg &= ~ED_CFG_64DD_WRITE_ENABLED; +// cfg |= ED_CFG_64DD_ON; +// ed64_ll_reg_write(REG_CFG, cfg); +// } -/* Set 64DD Write Enable?? */ -void ed64_ll_64dd_ram_we() { +// /* Set 64DD Write Enable?? */ +// void ed64_ll_64dd_ram_we() { - uint16_t cfg = ed64_ll_reg_read(REG_CFG); - cfg |= ED_CFG_64DD_ON | ED_CFG_64DD_WRITE_ENABLED; - ed64_ll_reg_write(REG_CFG, cfg); -} +// uint16_t cfg = ed64_ll_reg_read(REG_CFG); +// cfg |= ED_CFG_64DD_ON | ED_CFG_64DD_WRITE_ENABLED; +// ed64_ll_reg_write(REG_CFG, cfg); +// } -/* Set 64DD Disabled?? */ -void ed64_ll_64dd_ram_off() { +// /* Set 64DD Disabled?? */ +// void ed64_ll_64dd_ram_off() { - uint16_t cfg = ed64_ll_reg_read(REG_CFG); - cfg &= ~(ED_CFG_64DD_ON | ED_CFG_64DD_WRITE_ENABLED); - ed64_ll_reg_write(REG_CFG, cfg); -} +// uint16_t cfg = ed64_ll_reg_read(REG_CFG); +// cfg &= ~(ED_CFG_64DD_ON | ED_CFG_64DD_WRITE_ENABLED); +// ed64_ll_reg_write(REG_CFG, cfg); +// } -/* 64DD Save RAM Clear */ -void ed64_ll_64dd_ram_clear() { +// /* 64DD Save RAM Clear */ +// void ed64_ll_64dd_ram_clear() { - uint16_t cfg = ed64_ll_reg_read(REG_CFG); - cfg |= ED_CFG_64DD_WRITE_ENABLED; - cfg &= ~ED_CFG_64DD_ON; - ed64_ll_reg_write(REG_CFG, cfg); - wait_ms(100); -} +// uint16_t cfg = ed64_ll_reg_read(REG_CFG); +// cfg |= ED_CFG_64DD_WRITE_ENABLED; +// cfg &= ~ED_CFG_64DD_ON; +// ed64_ll_reg_write(REG_CFG, cfg); +// wait_ms(100); +// } -/* 64DD Allowed on this cart?! */ -uint8_t ed64_ll_get_64dd_ram_supported() { +// /* 64DD Allowed on this cart?! */ +// uint8_t ed64_ll_get_64dd_ram_supported() { - return (ed64_ll_reg_read(REG_STATUS) >> 15) & 1; +// return (ed64_ll_reg_read(REG_STATUS) >> 15) & 1; -} +// } From a2576e22ce217852b1a6a6b2250957607c692e30 Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Mon, 21 Aug 2023 17:36:04 +0100 Subject: [PATCH 34/64] Move ed64 ll functions Improve comments. --- src/flashcart/ed64/ed64.c | 12 ++--- src/flashcart/ed64/ed64_ll.c | 48 +++++++++++++++++--- src/flashcart/ed64/ed64_ll.h | 85 ++++++++++-------------------------- 3 files changed, 72 insertions(+), 73 deletions(-) diff --git a/src/flashcart/ed64/ed64.c b/src/flashcart/ed64/ed64.c index 380c1271..77d5df05 100644 --- a/src/flashcart/ed64/ed64.c +++ b/src/flashcart/ed64/ed64.c @@ -12,11 +12,11 @@ #include "ed64_ll.h" #include "ed64.h" - static flashcart_error_t ed64_init (void) { + // TODO: partly already done, see https://github.com/DragonMinded/libdragon/blob/4ec469d26b6dc4e308caf3d5b86c2b340b708bbd/src/libcart/cart.c#L1064 - ed64_ll_unlock_regs(); + //ed64_ll_unlock_regs(); // ed64_ll_init(); // FIXME: this causes a crash! // ed64_ll_reset_spx(); // only required if V2+ FW is updating! @@ -33,11 +33,10 @@ static flashcart_error_t ed64_init (void) { } static flashcart_error_t ed64_deinit (void) { - // // NOTE: Necessary because libcart enables ROM write by default - // ed64_ll_set_config(CFG_ROM_WRITE_ENABLE, false); - ed64_ll_gpio_mode_off(); // On V3, this should be ed64_bios_gpio_mode_rtc() if it is required. - ed64_ll_lock_regs(); + // ed64_ll_gpio_mode_off(); // On V3, this should be ed64_bios_gpio_mode_rtc() if it is required. + + ed_exit(); return FLASHCART_OK; } @@ -54,6 +53,7 @@ static flashcart_error_t ed64_load_rom (char *rom_path, flashcart_progress_callb size_t rom_size = f_size(&fil); + // FIXME: if the cart is not V3, we need to - 128KiB if (rom_size > MiB(64)) { f_close(&fil); return FLASHCART_ERROR_LOAD; diff --git a/src/flashcart/ed64/ed64_ll.c b/src/flashcart/ed64/ed64_ll.c index 25d6343d..a37183e5 100644 --- a/src/flashcart/ed64/ed64_ll.c +++ b/src/flashcart/ed64/ed64_ll.c @@ -2,6 +2,42 @@ #include "ed64_ll.h" +// NOTE: these are a replica of libcart cart.c defines! +#define PI_BASE_REG (0x04600000) +#define PI_STATUS_REG (PI_BASE_REG+0x10) + +#define PI_BSD_DOM1_LAT_REG (PI_BASE_REG+0x14) + +/* PI dom1 pulse width (R/W): [7:0] domain 1 device R/W strobe pulse width */ +#define PI_BSD_DOM1_PWD_REG (PI_BASE_REG+0x18) + +/* PI dom1 page size (R/W): [3:0] domain 1 device page size */ +#define PI_BSD_DOM1_PGS_REG (PI_BASE_REG+0x1C) /* page size */ + +/* PI dom1 release (R/W): [1:0] domain 1 device R/W release duration */ +#define PI_BSD_DOM1_RLS_REG (PI_BASE_REG+0x20) + +/* PI dom2 latency (R/W): [7:0] domain 2 device latency */ +#define PI_BSD_DOM2_LAT_REG (PI_BASE_REG+0x24) /* Domain 2 latency */ + +/* PI dom2 pulse width (R/W): [7:0] domain 2 device R/W strobe pulse width */ +#define PI_BSD_DOM2_PWD_REG (PI_BASE_REG+0x28) /* pulse width */ + +/* PI dom2 page size (R/W): [3:0] domain 2 device page size */ +#define PI_BSD_DOM2_PGS_REG (PI_BASE_REG+0x2C) /* page size */ + +/* PI dom2 release (R/W): [1:0] domain 2 device R/W release duration */ +#define PI_BSD_DOM2_RLS_REG (PI_BASE_REG+0x30) /* release duration */ + +#define IO_READ(addr) (*(volatile uint32_t *)PHYS_TO_K1(addr)) +#define IO_WRITE(addr,data) \ + (*(volatile uint32_t *)PHYS_TO_K1(addr)=(uint32_t)(data)) + +#define PHYS_TO_K1(x) ((uint32_t)(x)|0xA0000000) /* physical to kseg1 */ + +// END NOTE. + + /* Locks the ED64 registers */ #define ED64_KEY_LOCK 0x0000 /* Unlocks the ED64 registers */ @@ -49,13 +85,13 @@ typedef enum { } ed64_dma_state_t; -typedef enum { - DCFG_SD_TO_RAM = 1, - DCFG_RAM_TO_SD = 2, - DCFG_USB_TO_RAM = 3, - DCFG_RAM_TO_USB = 4, +// typedef enum { +// DCFG_SD_TO_RAM = 1, +// DCFG_RAM_TO_SD = 2, +// DCFG_USB_TO_RAM = 3, +// DCFG_RAM_TO_USB = 4, -} ed64_disk_mode_t; +// } ed64_disk_mode_t; #define SAV_EEP_ON 1 diff --git a/src/flashcart/ed64/ed64_ll.h b/src/flashcart/ed64/ed64_ll.h index f5c9c01c..ec088c00 100644 --- a/src/flashcart/ed64/ed64_ll.h +++ b/src/flashcart/ed64/ed64_ll.h @@ -30,66 +30,29 @@ typedef enum { } ed64_save_type_t; -typedef struct { - uint16_t assembily_date; /* The Date that the ED64 was manufactured */ - uint16_t assembily_time; /* The Time that the ED64 was manufactured */ - uint16_t serial_number; /* The ED64 serial number (unique for each ED64) */ - bool cic_6105_compatible; /* This returns whether the the cart CIC is 6105 compatible - as many were produced before Ultra CIC existed! - Carts that are not compatible will be unable to run certain ROMs */ +// typedef struct { +// uint16_t assembily_date; /* The Date that the ED64 was manufactured */ +// uint16_t assembily_time; /* The Time that the ED64 was manufactured */ +// uint16_t serial_number; /* The ED64 serial number (unique for each ED64) */ +// bool cic_6105_compatible; /* This returns whether the the cart CIC is 6105 compatible +// as many were produced before Ultra CIC existed! +// Carts that are not compatible will be unable to run certain ROMs */ -} ed64_cart_metadata_s; +// } ed64_cart_metadata_s; #define SRAM_ADDRESS (0xA8000000) #define ROM_ADDRESS (0xB0000000) -#define USB_ERROR_FIFO_TIMEOUT 0x90 -#define EVD_ERROR_MMC_TIMEOUT 0x91 +// #define USB_ERROR_FIFO_TIMEOUT 0x90 +// #define EVD_ERROR_MMC_TIMEOUT 0x91 -#define BOOT_UPD_ERR_WRONG_SIZE 0x95 -#define BOOT_UPD_ERR_HDR 0x96 -#define BOOT_UPD_ERR_CMP 0x97 -#define BOOT_UPD_ERR_CIC_DTCT 0x98 +// #define BOOT_UPD_ERR_WRONG_SIZE 0x95 +// #define BOOT_UPD_ERR_HDR 0x96 +// #define BOOT_UPD_ERR_CMP 0x97 +// #define BOOT_UPD_ERR_CIC_DTCT 0x98 -#define PI_BASE_REG (0x04600000) -#define PI_STATUS_REG (PI_BASE_REG+0x10) -#define PI_BSD_DOM1_LAT_REG (PI_BASE_REG+0x14) - -/* PI dom1 pulse width (R/W): [7:0] domain 1 device R/W strobe pulse width */ -#define PI_BSD_DOM1_PWD_REG (PI_BASE_REG+0x18) - -/* PI dom1 page size (R/W): [3:0] domain 1 device page size */ -#define PI_BSD_DOM1_PGS_REG (PI_BASE_REG+0x1C) /* page size */ - -/* PI dom1 release (R/W): [1:0] domain 1 device R/W release duration */ -#define PI_BSD_DOM1_RLS_REG (PI_BASE_REG+0x20) - -/* PI dom2 latency (R/W): [7:0] domain 2 device latency */ -#define PI_BSD_DOM2_LAT_REG (PI_BASE_REG+0x24) /* Domain 2 latency */ - -/* PI dom2 pulse width (R/W): [7:0] domain 2 device R/W strobe pulse width */ -#define PI_BSD_DOM2_PWD_REG (PI_BASE_REG+0x28) /* pulse width */ - -/* PI dom2 page size (R/W): [3:0] domain 2 device page size */ -#define PI_BSD_DOM2_PGS_REG (PI_BASE_REG+0x2C) /* page size */ - -/* PI dom2 release (R/W): [1:0] domain 2 device R/W release duration */ -#define PI_BSD_DOM2_RLS_REG (PI_BASE_REG+0x30) /* release duration */ - -#define PHYS_TO_K1(x) ((uint32_t)(x)|0xA0000000) /* physical to kseg1 */ -#define IO_WRITE(addr,data) (*(volatile uint32_t *)PHYS_TO_K1(addr)=(uint32_t)(data)) -#define IO_READ(addr) (*(volatile uint32_t *)PHYS_TO_K1(addr)) - - -#define SPI_CFG_SPD0 1 -#define SPI_CFG_SPD1 2 -#define SPI_CFG_SS 4 -#define SPI_CFG_RD 8 -#define SPI_CFG_DAT 16 -#define SPI_CFG_1BIT 32 - /* Initialization functions */ uint8_t ed64_ll_init(); void ed64_ll_init_v2(); @@ -102,10 +65,10 @@ uint16_t ed64_ll_get_cpld_version(); /* Firmware update functions */ void ed64_ll_load_firmware(uint8_t *firmware); -/* USB functions */ -uint8_t ed64_ll_usb_read_busy(); -uint8_t ed64_ll_usb_read(uint32_t start_address, uint32_t slen); -uint8_t ed64_ll_usb_write(uint32_t start_address, uint32_t slen); +// /* USB functions */ +// uint8_t ed64_ll_usb_read_busy(); +// uint8_t ed64_ll_usb_read(uint32_t start_address, uint32_t slen); +// uint8_t ed64_ll_usb_write(uint32_t start_address, uint32_t slen); /* Save functions */ void ed64_ll_set_ram_bank(uint8_t bank); @@ -137,12 +100,12 @@ void ed64_ll_gpio_mode_io(); void ed64_ll_gpio_mode_off(); uint8_t ed64_ll_gpio_read(); -/* 64DD cart conversion save functions */ -void ed64_ll_64dd_ram_oe(); -void ed64_ll_64dd_ram_we(); -void ed64_ll_64dd_ram_off(); -void ed64_ll_64dd_ram_clear(); -uint8_t ed64_ll_get_64dd_ram_supported(); +// /* 64DD cart conversion save functions */ +// void ed64_ll_64dd_ram_oe(); +// void ed64_ll_64dd_ram_we(); +// void ed64_ll_64dd_ram_off(); +// void ed64_ll_64dd_ram_clear(); +// uint8_t ed64_ll_get_64dd_ram_supported(); /** @} */ /* ed64 */ From ef682dd2f4afaf7a0c57e145fa36dab1ae121136 Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Mon, 21 Aug 2023 18:40:15 +0100 Subject: [PATCH 35/64] Further fixups --- src/flashcart/ed64/ed64.c | 10 +++++----- src/flashcart/ed64/ed64_ll.c | 10 ++++++++-- src/flashcart/ed64/ed64_ll.h | 10 +--------- 3 files changed, 14 insertions(+), 16 deletions(-) diff --git a/src/flashcart/ed64/ed64.c b/src/flashcart/ed64/ed64.c index 77d5df05..21d5d032 100644 --- a/src/flashcart/ed64/ed64.c +++ b/src/flashcart/ed64/ed64.c @@ -12,6 +12,8 @@ #include "ed64_ll.h" #include "ed64.h" +extern int ed_exit(void); + static flashcart_error_t ed64_init (void) { // TODO: partly already done, see https://github.com/DragonMinded/libdragon/blob/4ec469d26b6dc4e308caf3d5b86c2b340b708bbd/src/libcart/cart.c#L1064 @@ -36,6 +38,7 @@ static flashcart_error_t ed64_deinit (void) { // ed64_ll_gpio_mode_off(); // On V3, this should be ed64_bios_gpio_mode_rtc() if it is required. + // For the moment, just use libCart exit. ed_exit(); return FLASHCART_OK; @@ -53,7 +56,7 @@ static flashcart_error_t ed64_load_rom (char *rom_path, flashcart_progress_callb size_t rom_size = f_size(&fil); - // FIXME: if the cart is not V3, we need to - 128KiB + // FIXME: if the cart is not V3 or X5 or X7, we need to - 128KiB if (rom_size > MiB(64)) { f_close(&fil); return FLASHCART_ERROR_LOAD; @@ -98,6 +101,7 @@ static flashcart_error_t ed64_load_file (char *file_path, uint32_t rom_offset, u size_t file_size = f_size(&fil) - file_offset; + // FIXME: if the cart is not V3 or X5 or X7, we need to - 128KiB if (file_size > (MiB(64) - rom_offset)) { f_close(&fil); return FLASHCART_ERROR_ARGS; @@ -199,10 +203,6 @@ static flashcart_error_t ed64_set_save_type (flashcart_save_type_t save_type) { return FLASHCART_ERROR_ARGS; } - // if (ed64_set_config(CFG_SAVE_TYPE, type) != ED64_OK) { - // return FLASHCART_ERROR_INT; - // } - ed64_ll_set_save_type(type); return FLASHCART_OK; diff --git a/src/flashcart/ed64/ed64_ll.c b/src/flashcart/ed64/ed64_ll.c index a37183e5..50c01644 100644 --- a/src/flashcart/ed64/ed64_ll.c +++ b/src/flashcart/ed64/ed64_ll.c @@ -129,6 +129,12 @@ void ed64_ll_dma_pi_write(void * ram_address, unsigned long pi_address, unsigned void ed64_ll_dma_read(void *ram, uint32_t address, uint32_t length); void ed64_ll_dma_write(void *ram, uint32_t address, uint32_t length); +/* DMA functions */ +void ed64_ll_dma_read_rom(void *ram, uint32_t start_address, uint32_t slen); +void ed64_ll_dma_write_rom(void *ram, uint32_t start_address, uint32_t slen); +void ed64_ll_dma_read_sram(void *ram, uint32_t address, uint32_t length); +void ed64_ll_dma_write_sram(void *ram, uint32_t address, uint32_t length); + // static uint16_t spi_cfg; uint8_t ed64_ll_ram_bank; ed64_save_type_t ed64_ll_save_type; @@ -193,13 +199,13 @@ void ed64_ll_init_v3() { } /* Initialize cart */ -uint8_t ed64_ll_init() { +int ed64_ll_init() { uint16_t firmware_ver; uint16_t firmware_msg; uint8_t cold_start; - + // TODO: take into account libCart! IO_WRITE(PI_BSD_DOM2_LAT_REG, REG_LAT); IO_WRITE(PI_BSD_DOM2_PWD_REG, REG_PWD); diff --git a/src/flashcart/ed64/ed64_ll.h b/src/flashcart/ed64/ed64_ll.h index ec088c00..1a940035 100644 --- a/src/flashcart/ed64/ed64_ll.h +++ b/src/flashcart/ed64/ed64_ll.h @@ -54,7 +54,7 @@ typedef enum { /* Initialization functions */ -uint8_t ed64_ll_init(); +int ed64_ll_init(); void ed64_ll_init_v2(); void ed64_ll_init_v3(); @@ -81,17 +81,9 @@ void ed64_ll_read_cart_metadata(void *dest); uint16_t ed64_ll_msg_rd(); void ed64_ll_msg_wr(uint16_t val); -/* DMA functions */ -void ed64_ll_dma_read_rom(void *ram, uint32_t start_address, uint32_t slen); -void ed64_ll_dma_write_rom(void *ram, uint32_t start_address, uint32_t slen); -void ed64_ll_dma_read_sram(void *ram, uint32_t address, uint32_t length); -void ed64_ll_dma_write_sram(void *ram, uint32_t address, uint32_t length); - void ed64_ll_lock_regs(); void ed64_ll_unlock_regs(); -uint32_t ed64_ll_reg_read(uint32_t reg); -void ed64_ll_reg_write(uint32_t reg, uint32_t data); void ed64_ll_reset_spx(); /* GPIO functions */ From 3aa12fb9c6dc76a7fa29ee2aaebf84cff843559a Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Mon, 21 Aug 2023 20:43:16 +0100 Subject: [PATCH 36/64] Fix for V2.5 and below They cannot handle full 64 MiB ROM's --- src/flashcart/ed64/ed64.c | 4 ++-- src/flashcart/ed64/ed64_ll.c | 8 ++++---- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/flashcart/ed64/ed64.c b/src/flashcart/ed64/ed64.c index 21d5d032..bce8ed12 100644 --- a/src/flashcart/ed64/ed64.c +++ b/src/flashcart/ed64/ed64.c @@ -57,7 +57,7 @@ static flashcart_error_t ed64_load_rom (char *rom_path, flashcart_progress_callb size_t rom_size = f_size(&fil); // FIXME: if the cart is not V3 or X5 or X7, we need to - 128KiB - if (rom_size > MiB(64)) { + if (rom_size > MiB(64) - KiB(128)) { f_close(&fil); return FLASHCART_ERROR_LOAD; } @@ -102,7 +102,7 @@ static flashcart_error_t ed64_load_file (char *file_path, uint32_t rom_offset, u size_t file_size = f_size(&fil) - file_offset; // FIXME: if the cart is not V3 or X5 or X7, we need to - 128KiB - if (file_size > (MiB(64) - rom_offset)) { + if (file_size > (MiB(64) - KiB(128) - rom_offset)) { f_close(&fil); return FLASHCART_ERROR_ARGS; } diff --git a/src/flashcart/ed64/ed64_ll.c b/src/flashcart/ed64/ed64_ll.c index 50c01644..57b88598 100644 --- a/src/flashcart/ed64/ed64_ll.c +++ b/src/flashcart/ed64/ed64_ll.c @@ -136,7 +136,7 @@ void ed64_ll_dma_read_sram(void *ram, uint32_t address, uint32_t length); void ed64_ll_dma_write_sram(void *ram, uint32_t address, uint32_t length); // static uint16_t spi_cfg; -uint8_t ed64_ll_ram_bank; +uint8_t ed64_ll_sram_bank; ed64_save_type_t ed64_ll_save_type; #define REG_LAT 0x04 @@ -330,7 +330,7 @@ void ed64_ll_set_save_type(ed64_save_type_t type) { sram_on = 0; eeprom_size = 0; sram_size = 0; - ram_bank = ed64_ll_ram_bank; + ram_bank = ed64_ll_sram_bank; switch (type) { @@ -371,9 +371,9 @@ void ed64_ll_set_save_type(ed64_save_type_t type) { } -void ed64_ll_set_ram_bank(uint8_t bank) { +void ed64_ll_set_sram_bank(uint8_t bank) { - ed64_ll_ram_bank = bank == 0 ? 0 : 1; + ed64_ll_sram_bank = bank == 0 ? 0 : 1; } From 5490efbe2551025fac471c7e197cb9dba66de20e Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Mon, 21 Aug 2023 21:05:28 +0100 Subject: [PATCH 37/64] Improve comments. --- src/flashcart/ed64/README.md | 10 ++-------- src/flashcart/ed64/ed64.c | 4 ++-- 2 files changed, 4 insertions(+), 10 deletions(-) diff --git a/src/flashcart/ed64/README.md b/src/flashcart/ed64/README.md index 13412c37..047e6bc0 100644 --- a/src/flashcart/ed64/README.md +++ b/src/flashcart/ed64/README.md @@ -1,15 +1,9 @@ -This folder allows support for the ED64 "Official" flashcart when using V series hardware. -For the moment it is unlikely to support clones. - -It is based on OS 2.12.x as used in the "Unofficial Menu" (https://github.com/n64-tools/ED64-UnofficialOS-binaries/releases/tag/V2.12.9.3-Release) - -It may require further cleansing and updating to use the latest libdragon before it will probably work based on the fact that using the latest libdragon with `libcart` seems to have a detremental effect on the ability to load ROM's. - +This folder allows support for the ED64(P) flashcart when using V series hardware. Initially, this aims to work when loading the official ED64 OS menu, selecting the N64FlashcartMenu and then loading a ROM from there. This works around needing to load the correct firmware. To automate this, it is possible to set this menu to autoload (at least in the unofficial menu). i.e. You can set this ROM to auto load by placing a file called `autoexec.v64` in the `ED64` folder with the content of the file pointing to the path of this ROM. Notes: * `libcart` seems to use a different base register address `0x08040000`, but official implementation uses `0xA8040000` -* The ability to load/save `FLASHRAM` may not yet be supported. +* When loading directly via `ED64\ED64.v64` The ability to load commercial ROM's is broken. diff --git a/src/flashcart/ed64/ed64.c b/src/flashcart/ed64/ed64.c index bce8ed12..0179cc0a 100644 --- a/src/flashcart/ed64/ed64.c +++ b/src/flashcart/ed64/ed64.c @@ -25,7 +25,7 @@ static flashcart_error_t ed64_init (void) { // ed64_ll_set_ram_bank(1); // Seemingly bank 0 (for SRAM 128k) is only supported on V3 and it is not the default. - // If a V3 cart is detected (has a battery?), enable RTC, + // If a V3 or X7 cart is detected (has a battery?), enable RTC, // ed64_ll_gpio_mode_rtc(); // otherwise: // ed64_ll_gpio_mode_io(); @@ -36,7 +36,7 @@ static flashcart_error_t ed64_init (void) { static flashcart_error_t ed64_deinit (void) { - // ed64_ll_gpio_mode_off(); // On V3, this should be ed64_bios_gpio_mode_rtc() if it is required. + // ed64_ll_gpio_mode_off(); // On V3 or X7, this should be ed64_bios_gpio_mode_rtc() if it is required. // For the moment, just use libCart exit. ed_exit(); From 769f75475fdd75ba3f3857381f217fc775b84ff8 Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Mon, 21 Aug 2023 21:45:11 +0100 Subject: [PATCH 38/64] Fix commercial ROM boots. --- src/flashcart/ed64/ed64.c | 34 +++++++++++++++++----------------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/src/flashcart/ed64/ed64.c b/src/flashcart/ed64/ed64.c index 0179cc0a..42f67633 100644 --- a/src/flashcart/ed64/ed64.c +++ b/src/flashcart/ed64/ed64.c @@ -129,7 +129,7 @@ static flashcart_error_t ed64_load_file (char *file_path, uint32_t rom_offset, u } static flashcart_error_t ed64_load_save (char *save_path) { - void *address = NULL; +// void *address = 0x08000000; // ed64_save_type_t type = ed64_ll_get_save_type(); // // if (ed64_get_config(CFG_SAVE_TYPE, &type) != ED64_OK) { @@ -151,27 +151,27 @@ static flashcart_error_t ed64_load_save (char *save_path) { // // return FLASHCART_ERROR_ARGS; // // } - FIL fil; - UINT br; + // FIL fil; + // UINT br; - if (f_open(&fil, strip_sd_prefix(save_path), FA_READ) != FR_OK) { - return FLASHCART_ERROR_LOAD; - } + // if (f_open(&fil, strip_sd_prefix(save_path), FA_READ) != FR_OK) { + // return FLASHCART_ERROR_LOAD; + // } - size_t save_size = f_size(&fil); + // size_t save_size = f_size(&fil); - if (f_read(&fil, address, save_size, &br) != FR_OK) { - f_close(&fil); - return FLASHCART_ERROR_LOAD; - } + // if (f_read(&fil, address, save_size, &br) != FR_OK) { + // f_close(&fil); + // return FLASHCART_ERROR_LOAD; + // } - if (f_close(&fil) != FR_OK) { - return FLASHCART_ERROR_LOAD; - } + // if (f_close(&fil) != FR_OK) { + // return FLASHCART_ERROR_LOAD; + // } - if (br != save_size) { - return FLASHCART_ERROR_LOAD; - } + // if (br != save_size) { + // return FLASHCART_ERROR_LOAD; + // } return FLASHCART_OK; } From a3f7863469c39fc3cb10c802a05084c3301bbf0c Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Mon, 21 Aug 2023 22:11:33 +0100 Subject: [PATCH 39/64] Improve notes. --- Makefile | 2 +- src/flashcart/ed64/README.md | 5 ++++- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/Makefile b/Makefile index 4648cea0..7cbbcf11 100644 --- a/Makefile +++ b/Makefile @@ -137,4 +137,4 @@ endif # test: # TODO: run tests --include $(DEPS) \ No newline at end of file +-include $(DEPS) diff --git a/src/flashcart/ed64/README.md b/src/flashcart/ed64/README.md index 047e6bc0..a8e90fd6 100644 --- a/src/flashcart/ed64/README.md +++ b/src/flashcart/ed64/README.md @@ -2,8 +2,11 @@ This folder allows support for the ED64(P) flashcart when using V series hardwar Initially, this aims to work when loading the official ED64 OS menu, selecting the N64FlashcartMenu and then loading a ROM from there. This works around needing to load the correct firmware. To automate this, it is possible to set this menu to autoload (at least in the unofficial menu). i.e. You can set this ROM to auto load by placing a file called `autoexec.v64` in the `ED64` folder with the content of the file pointing to the path of this ROM. +However, the current implementation is able to replace `/ED64/ED64.v64` and load ROM's using the `output/ED64.v64` ROM. + + Notes: * `libcart` seems to use a different base register address `0x08040000`, but official implementation uses `0xA8040000` -* When loading directly via `ED64\ED64.v64` The ability to load commercial ROM's is broken. +* Loading saves is currently not available. From 117c7a430f66ae7d105fe9a3bd833828e66185c7 Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Mon, 21 Aug 2023 22:57:43 +0100 Subject: [PATCH 40/64] Fix saves (at least for EEPROM_4K --- src/flashcart/ed64/ed64.c | 84 +++++++++++++++++++-------------------- 1 file changed, 41 insertions(+), 43 deletions(-) diff --git a/src/flashcart/ed64/ed64.c b/src/flashcart/ed64/ed64.c index 42f67633..8baae8ae 100644 --- a/src/flashcart/ed64/ed64.c +++ b/src/flashcart/ed64/ed64.c @@ -12,6 +12,8 @@ #include "ed64_ll.h" #include "ed64.h" +#define EEPROM_ADDRESS (0x1FFE2000) + extern int ed_exit(void); static flashcart_error_t ed64_init (void) { @@ -129,49 +131,45 @@ static flashcart_error_t ed64_load_file (char *file_path, uint32_t rom_offset, u } static flashcart_error_t ed64_load_save (char *save_path) { -// void *address = 0x08000000; -// ed64_save_type_t type = ed64_ll_get_save_type(); - -// // if (ed64_get_config(CFG_SAVE_TYPE, &type) != ED64_OK) { -// // return FLASHCART_ERROR_INT; -// // } - -// // switch (type) { -// // case SAVE_TYPE_EEPROM_4K: -// // case SAVE_TYPE_EEPROM_16K: -// // address = (void *) (EEPROM_ADDRESS); -// // break; -// // case SAVE_TYPE_SRAM: -// // case SAVE_TYPE_FLASHRAM: -// // case SAVE_TYPE_SRAM_BANKED: -// // address = (void *) (SRAM_FLASHRAM_ADDRESS); -// // break; -// // case SAVE_TYPE_NONE: -// // default: -// // return FLASHCART_ERROR_ARGS; -// // } - - // FIL fil; - // UINT br; - - // if (f_open(&fil, strip_sd_prefix(save_path), FA_READ) != FR_OK) { - // return FLASHCART_ERROR_LOAD; - // } - - // size_t save_size = f_size(&fil); - - // if (f_read(&fil, address, save_size, &br) != FR_OK) { - // f_close(&fil); - // return FLASHCART_ERROR_LOAD; - // } - - // if (f_close(&fil) != FR_OK) { - // return FLASHCART_ERROR_LOAD; - // } - - // if (br != save_size) { - // return FLASHCART_ERROR_LOAD; - // } + void *address = NULL; + ed64_save_type_t type = ed64_ll_get_save_type(); + + switch (type) { + case SAVE_TYPE_EEPROM_4K: + case SAVE_TYPE_EEPROM_16K: + address = (void *) (EEPROM_ADDRESS); + break; + case SAVE_TYPE_SRAM: + case SAVE_TYPE_SRAM_128K: + case SAVE_TYPE_FLASHRAM: + address = (void *) (SRAM_ADDRESS); + break; + case SAVE_TYPE_NONE: + default: + return FLASHCART_ERROR_ARGS; + } + + FIL fil; + UINT br; + + if (f_open(&fil, strip_sd_prefix(save_path), FA_READ) != FR_OK) { + return FLASHCART_ERROR_LOAD; + } + + size_t save_size = f_size(&fil); + + if (f_read(&fil, address, save_size, &br) != FR_OK) { + f_close(&fil); + return FLASHCART_ERROR_LOAD; + } + + if (f_close(&fil) != FR_OK) { + return FLASHCART_ERROR_LOAD; + } + + if (br != save_size) { + return FLASHCART_ERROR_LOAD; + } return FLASHCART_OK; } From 68293bed52cb56d9ad2bb8837f114a2c9a5dfa68 Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Wed, 27 Dec 2023 23:59:04 +0000 Subject: [PATCH 41/64] Fix merge Add fixes for latest main branch --- Makefile | 1 - src/flashcart/ed64/ed64.c | 56 +++++++++++++++++++++++---------------- 2 files changed, 33 insertions(+), 24 deletions(-) diff --git a/Makefile b/Makefile index 7f612042..63283f05 100644 --- a/Makefile +++ b/Makefile @@ -27,7 +27,6 @@ SRCS = \ flashcart/sc64/sc64.c \ flashcart/ed64/ed64_ll.c \ flashcart/ed64/ed64.c \ - hdmi/hdmi.c \ libs/libspng/spng/spng.c \ libs/mini.c/src/mini.c \ libs/miniz/miniz_tdef.c \ diff --git a/src/flashcart/ed64/ed64.c b/src/flashcart/ed64/ed64.c index 8baae8ae..bc2967dd 100644 --- a/src/flashcart/ed64/ed64.c +++ b/src/flashcart/ed64/ed64.c @@ -16,7 +16,7 @@ extern int ed_exit(void); -static flashcart_error_t ed64_init (void) { +static flashcart_err_t ed64_init (void) { // TODO: partly already done, see https://github.com/DragonMinded/libdragon/blob/4ec469d26b6dc4e308caf3d5b86c2b340b708bbd/src/libcart/cart.c#L1064 @@ -36,7 +36,7 @@ static flashcart_error_t ed64_init (void) { return FLASHCART_OK; } -static flashcart_error_t ed64_deinit (void) { +static flashcart_err_t ed64_deinit (void) { // ed64_ll_gpio_mode_off(); // On V3 or X7, this should be ed64_bios_gpio_mode_rtc() if it is required. @@ -46,12 +46,19 @@ static flashcart_error_t ed64_deinit (void) { return FLASHCART_OK; } -static flashcart_error_t ed64_load_rom (char *rom_path, flashcart_progress_callback_t *progress) { +static bool ed64_has_feature (flashcart_features_t feature) { + switch (feature) { + case FLASHCART_FEATURE_64DD: return false; + default: return false; + } +} + +static flashcart_err_t ed64_load_rom (char *rom_path, flashcart_progress_callback_t *progress) { FIL fil; UINT br; if (f_open(&fil, strip_sd_prefix(rom_path), FA_READ) != FR_OK) { - return FLASHCART_ERROR_LOAD; + return FLASHCART_ERR_LOAD; } fix_file_size(&fil); @@ -61,7 +68,7 @@ static flashcart_error_t ed64_load_rom (char *rom_path, flashcart_progress_callb // FIXME: if the cart is not V3 or X5 or X7, we need to - 128KiB if (rom_size > MiB(64) - KiB(128)) { f_close(&fil); - return FLASHCART_ERROR_LOAD; + return FLASHCART_ERR_LOAD; } @@ -72,7 +79,7 @@ static flashcart_error_t ed64_load_rom (char *rom_path, flashcart_progress_callb size_t block_size = MIN(sdram_size - offset, chunk_size); if (f_read(&fil, (void *) (ROM_ADDRESS + offset), block_size, &br) != FR_OK) { f_close(&fil); - return FLASHCART_ERROR_LOAD; + return FLASHCART_ERR_LOAD; } if (progress) { progress(f_tell(&fil) / (float) (f_size(&fil))); @@ -80,23 +87,23 @@ static flashcart_error_t ed64_load_rom (char *rom_path, flashcart_progress_callb } if (f_tell(&fil) != sdram_size) { f_close(&fil); - return FLASHCART_ERROR_LOAD; + return FLASHCART_ERR_LOAD; } if (f_close(&fil) != FR_OK) { - return FLASHCART_ERROR_LOAD; + return FLASHCART_ERR_LOAD; } return FLASHCART_OK; } -static flashcart_error_t ed64_load_file (char *file_path, uint32_t rom_offset, uint32_t file_offset) { +static flashcart_err_t ed64_load_file (char *file_path, uint32_t rom_offset, uint32_t file_offset) { FIL fil; UINT br; if (f_open(&fil, strip_sd_prefix(file_path), FA_READ) != FR_OK) { - return FLASHCART_ERROR_LOAD; + return FLASHCART_ERR_LOAD; } fix_file_size(&fil); @@ -106,31 +113,31 @@ static flashcart_error_t ed64_load_file (char *file_path, uint32_t rom_offset, u // FIXME: if the cart is not V3 or X5 or X7, we need to - 128KiB if (file_size > (MiB(64) - KiB(128) - rom_offset)) { f_close(&fil); - return FLASHCART_ERROR_ARGS; + return FLASHCART_ERR_ARGS; } if (f_lseek(&fil, file_offset) != FR_OK) { f_close(&fil); - return FLASHCART_ERROR_LOAD; + return FLASHCART_ERR_LOAD; } if (f_read(&fil, (void *) (ROM_ADDRESS + rom_offset), file_size, &br) != FR_OK) { f_close(&fil); - return FLASHCART_ERROR_LOAD; + return FLASHCART_ERR_LOAD; } if (br != file_size) { f_close(&fil); - return FLASHCART_ERROR_LOAD; + return FLASHCART_ERR_LOAD; } if (f_close(&fil) != FR_OK) { - return FLASHCART_ERROR_LOAD; + return FLASHCART_ERR_LOAD; } return FLASHCART_OK; } -static flashcart_error_t ed64_load_save (char *save_path) { +static flashcart_err_t ed64_load_save (char *save_path) { void *address = NULL; ed64_save_type_t type = ed64_ll_get_save_type(); @@ -146,35 +153,35 @@ static flashcart_error_t ed64_load_save (char *save_path) { break; case SAVE_TYPE_NONE: default: - return FLASHCART_ERROR_ARGS; + return FLASHCART_ERR_ARGS; } FIL fil; UINT br; if (f_open(&fil, strip_sd_prefix(save_path), FA_READ) != FR_OK) { - return FLASHCART_ERROR_LOAD; + return FLASHCART_ERR_LOAD; } size_t save_size = f_size(&fil); if (f_read(&fil, address, save_size, &br) != FR_OK) { f_close(&fil); - return FLASHCART_ERROR_LOAD; + return FLASHCART_ERR_LOAD; } if (f_close(&fil) != FR_OK) { - return FLASHCART_ERROR_LOAD; + return FLASHCART_ERR_LOAD; } if (br != save_size) { - return FLASHCART_ERROR_LOAD; + return FLASHCART_ERR_LOAD; } return FLASHCART_OK; } -static flashcart_error_t ed64_set_save_type (flashcart_save_type_t save_type) { +static flashcart_err_t ed64_set_save_type (flashcart_save_type_t save_type) { ed64_save_type_t type; switch (save_type) { @@ -198,7 +205,7 @@ static flashcart_error_t ed64_set_save_type (flashcart_save_type_t save_type) { type = SAVE_TYPE_FLASHRAM; break; default: - return FLASHCART_ERROR_ARGS; + return FLASHCART_ERR_ARGS; } ed64_ll_set_save_type(type); @@ -210,9 +217,12 @@ static flashcart_error_t ed64_set_save_type (flashcart_save_type_t save_type) { static flashcart_t flashcart_ed64 = { .init = ed64_init, .deinit = ed64_deinit, + .has_feature = ed64_has_feature, .load_rom = ed64_load_rom, .load_file = ed64_load_file, .load_save = ed64_load_save, + .load_64dd_ipl = NULL, + .load_64dd_disk = NULL, .set_save_type = ed64_set_save_type, .set_save_writeback = NULL, }; From 49cf33a611f8e17fde2aac150162867c80620639 Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Thu, 28 Dec 2023 00:51:16 +0000 Subject: [PATCH 42/64] Fix issues with ED64 flashcart functions --- src/flashcart/ed64/ed64.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/src/flashcart/ed64/ed64.c b/src/flashcart/ed64/ed64.c index bc2967dd..c110cfe6 100644 --- a/src/flashcart/ed64/ed64.c +++ b/src/flashcart/ed64/ed64.c @@ -65,14 +65,14 @@ static flashcart_err_t ed64_load_rom (char *rom_path, flashcart_progress_callbac size_t rom_size = f_size(&fil); - // FIXME: if the cart is not V3 or X5 or X7, we need to - 128KiB - if (rom_size > MiB(64) - KiB(128)) { + // FIXME: if the cart is not V3 or X5 or X7, we probably need to - 128KiB + if (rom_size > MiB(64)) { f_close(&fil); return FLASHCART_ERR_LOAD; } - size_t sdram_size = rom_size; + size_t sdram_size = MiB(64); size_t chunk_size = MiB(1); for (int offset = 0; offset < sdram_size; offset += chunk_size) { @@ -85,7 +85,7 @@ static flashcart_err_t ed64_load_rom (char *rom_path, flashcart_progress_callbac progress(f_tell(&fil) / (float) (f_size(&fil))); } } - if (f_tell(&fil) != sdram_size) { + if (f_tell(&fil) != rom_size) { f_close(&fil); return FLASHCART_ERR_LOAD; } @@ -110,8 +110,8 @@ static flashcart_err_t ed64_load_file (char *file_path, uint32_t rom_offset, uin size_t file_size = f_size(&fil) - file_offset; - // FIXME: if the cart is not V3 or X5 or X7, we need to - 128KiB - if (file_size > (MiB(64) - KiB(128) - rom_offset)) { + // FIXME: if the cart is not V3 or X5 or X7, we probably need to - 128KiB + if (file_size > (MiB(64) - rom_offset)) { f_close(&fil); return FLASHCART_ERR_ARGS; } @@ -201,6 +201,7 @@ static flashcart_err_t ed64_set_save_type (flashcart_save_type_t save_type) { case FLASHCART_SAVE_TYPE_SRAM_128K: type = SAVE_TYPE_SRAM_128K; break; + case FLASHCART_SAVE_TYPE_FLASHRAM_PKST2: case FLASHCART_SAVE_TYPE_FLASHRAM: type = SAVE_TYPE_FLASHRAM; break; From 4e764ae46493f0a5af5d338949ff410c231f1af8 Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Thu, 28 Dec 2023 01:24:05 +0000 Subject: [PATCH 43/64] Fix some comments --- src/flashcart/ed64/ed64.c | 4 ++++ src/flashcart/ed64/ed64.h | 2 +- src/flashcart/ed64/ed64_ll.h | 2 +- 3 files changed, 6 insertions(+), 2 deletions(-) diff --git a/src/flashcart/ed64/ed64.c b/src/flashcart/ed64/ed64.c index c110cfe6..82996119 100644 --- a/src/flashcart/ed64/ed64.c +++ b/src/flashcart/ed64/ed64.c @@ -31,6 +31,10 @@ static flashcart_err_t ed64_init (void) { // ed64_ll_gpio_mode_rtc(); // otherwise: // ed64_ll_gpio_mode_io(); + + // if (fpga_revision < SUPPORTED_FPGA_REVISION) { + // return FLASHCART_ERR_OUTDATED; + // } return FLASHCART_OK; diff --git a/src/flashcart/ed64/ed64.h b/src/flashcart/ed64/ed64.h index 4738140f..8680b592 100644 --- a/src/flashcart/ed64/ed64.h +++ b/src/flashcart/ed64/ed64.h @@ -1,5 +1,5 @@ /** - * @file flashcart.h + * @file ed64.h * @brief ED64 Flashcart Utilities * @ingroup flashcart */ diff --git a/src/flashcart/ed64/ed64_ll.h b/src/flashcart/ed64/ed64_ll.h index 1a940035..cb886fe3 100644 --- a/src/flashcart/ed64/ed64_ll.h +++ b/src/flashcart/ed64/ed64_ll.h @@ -1,5 +1,5 @@ /** - * @file flashcart.h + * @file ed64_ll.h * @brief ED64 V-Series Flashcart Internal Utilities * @ingroup flashcart */ From 983ecd95a1516b55599efce279dbbcd4bdf13b84 Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Fri, 29 Dec 2023 15:57:05 +0000 Subject: [PATCH 44/64] Minor improvements --- Makefile | 4 ++-- src/flashcart/ed64/ed64_ll.c | 43 ++++++++++++++++++------------------ src/flashcart/ed64/ed64_ll.h | 2 +- 3 files changed, 24 insertions(+), 25 deletions(-) diff --git a/Makefile b/Makefile index 63283f05..61814b3f 100644 --- a/Makefile +++ b/Makefile @@ -21,12 +21,12 @@ SRCS = \ boot/reboot.S \ flashcart/64drive/64drive_ll.c \ flashcart/64drive/64drive.c \ - flashcart/flashcart_utils.c \ - flashcart/flashcart.c \ flashcart/sc64/sc64_ll.c \ flashcart/sc64/sc64.c \ flashcart/ed64/ed64_ll.c \ flashcart/ed64/ed64.c \ + flashcart/flashcart_utils.c \ + flashcart/flashcart.c \ libs/libspng/spng/spng.c \ libs/mini.c/src/mini.c \ libs/miniz/miniz_tdef.c \ diff --git a/src/flashcart/ed64/ed64_ll.c b/src/flashcart/ed64/ed64_ll.c index 57b88598..9f255bb5 100644 --- a/src/flashcart/ed64/ed64_ll.c +++ b/src/flashcart/ed64/ed64_ll.c @@ -1,5 +1,6 @@ #include +#include "../flashcart_utils.h" #include "ed64_ll.h" // NOTE: these are a replica of libcart cart.c defines! @@ -323,47 +324,45 @@ ed64_save_type_t ed64_ll_get_save_type() { void ed64_ll_set_save_type(ed64_save_type_t type) { - uint16_t save_cfg; - uint8_t eeprom_on, sram_on, eeprom_size, sram_size, ram_bank; + uint16_t save_cfg = 0; + uint8_t enable_eeprom = false; + uint8_t eeprom_size_16k = false; + uint8_t enable_sram = false; + uint8_t ram_size_large = false; ed64_ll_save_type = type; - eeprom_on = 0; - sram_on = 0; - eeprom_size = 0; - sram_size = 0; - ram_bank = ed64_ll_sram_bank; + uint8_t ram_bank = ed64_ll_sram_bank; switch (type) { case SAVE_TYPE_EEPROM_16K: - eeprom_on = 1; - eeprom_size = 1; + enable_eeprom = true; + eeprom_size_16k = true; break; case SAVE_TYPE_EEPROM_4K: - eeprom_on = 1; + enable_eeprom = true; break; case SAVE_TYPE_SRAM: - sram_on = 1; + enable_sram = true; break; case SAVE_TYPE_SRAM_128K: - sram_on = 1; - sram_size = 1; + enable_sram = true; + ram_size_large = true; break; case SAVE_TYPE_FLASHRAM: - sram_on = 0; - sram_size = 1; + enable_sram = false; + ram_size_large = true; break; default: - sram_on = 0; - sram_size = 0; + enable_sram = false; + ram_size_large = false; ram_bank = 1; break; } - save_cfg = 0; - if (eeprom_on)save_cfg |= SAV_EEP_ON; - if (sram_on)save_cfg |= SAV_SRM_ON; - if (eeprom_size)save_cfg |= SAV_EEP_SIZE; - if (sram_size)save_cfg |= SAV_SRM_SIZE; + if (enable_eeprom)save_cfg |= SAV_EEP_ON; + if (enable_sram)save_cfg |= SAV_SRM_ON; + if (eeprom_size_16k)save_cfg |= SAV_EEP_SIZE; + if (ram_size_large)save_cfg |= SAV_SRM_SIZE; if (ram_bank)save_cfg |= SAV_RAM_BANK; save_cfg |= SAV_RAM_BANK_APPLY; diff --git a/src/flashcart/ed64/ed64_ll.h b/src/flashcart/ed64/ed64_ll.h index cb886fe3..7b5f9c35 100644 --- a/src/flashcart/ed64/ed64_ll.h +++ b/src/flashcart/ed64/ed64_ll.h @@ -1,6 +1,6 @@ /** * @file ed64_ll.h - * @brief ED64 V-Series Flashcart Internal Utilities + * @brief ED64 V-Series flashcart low level access * @ingroup flashcart */ From 25f1f56c8ce30ccd03bd41bca726d6f5ab3b03cc Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Fri, 29 Dec 2023 19:26:35 +0000 Subject: [PATCH 45/64] Save improvements Correctly handle EEPROM save types. Use libdragon for IO read and writes. Comment out some un-used functions until needed. --- src/flashcart/ed64/ed64.c | 39 +++++--- src/flashcart/ed64/ed64_ll.c | 178 +++++++++++++++++++---------------- src/flashcart/ed64/ed64_ll.h | 7 +- src/flashcart/flashcart.c | 2 +- 4 files changed, 129 insertions(+), 97 deletions(-) diff --git a/src/flashcart/ed64/ed64.c b/src/flashcart/ed64/ed64.c index 82996119..538e2a03 100644 --- a/src/flashcart/ed64/ed64.c +++ b/src/flashcart/ed64/ed64.c @@ -12,7 +12,6 @@ #include "ed64_ll.h" #include "ed64.h" -#define EEPROM_ADDRESS (0x1FFE2000) extern int ed_exit(void); @@ -142,13 +141,24 @@ static flashcart_err_t ed64_load_file (char *file_path, uint32_t rom_offset, uin } static flashcart_err_t ed64_load_save (char *save_path) { + // TODO: look at d64_load_save() and adjust. + uint8_t eeprom_contents[KiB(2)] __attribute__((aligned(8))); void *address = NULL; - ed64_save_type_t type = ed64_ll_get_save_type(); + ed64_save_type_t current_save_type = ed64_ll_get_save_type(); - switch (type) { + FIL fil; + UINT br; + + if (f_open(&fil, strip_sd_prefix(save_path), FA_CREATE_ALWAYS | FA_READ) != FR_OK) { // FIXME: create always is a hack to ensure we always have a valid save. + return FLASHCART_ERR_LOAD; + } + + size_t save_size = f_size(&fil); + + switch (current_save_type) { case SAVE_TYPE_EEPROM_4K: case SAVE_TYPE_EEPROM_16K: - address = (void *) (EEPROM_ADDRESS); + address = eeprom_contents; break; case SAVE_TYPE_SRAM: case SAVE_TYPE_SRAM_128K: @@ -160,18 +170,18 @@ static flashcart_err_t ed64_load_save (char *save_path) { return FLASHCART_ERR_ARGS; } - FIL fil; - UINT br; - - if (f_open(&fil, strip_sd_prefix(save_path), FA_READ) != FR_OK) { + if(f_read(&fil, address, save_size, &br) != FR_OK) { + f_close(&fil); return FLASHCART_ERR_LOAD; } - size_t save_size = f_size(&fil); - - if (f_read(&fil, address, save_size, &br) != FR_OK) { - f_close(&fil); - return FLASHCART_ERR_LOAD; + if (eeprom_present()) { + if (current_save_type == SAVE_TYPE_EEPROM_16K) { // FIXME: could use save_size instead?! + eeprom_write_bytes(eeprom_contents, 0, KiB(2)); + } + else { + eeprom_write_bytes(eeprom_contents, 0, KiB(1)); + } } if (f_close(&fil) != FR_OK) { @@ -215,6 +225,9 @@ static flashcart_err_t ed64_set_save_type (flashcart_save_type_t save_type) { ed64_ll_set_save_type(type); + // TODO: set pesudo save writeback. + // as a start, create the file?! + return FLASHCART_OK; } diff --git a/src/flashcart/ed64/ed64_ll.c b/src/flashcart/ed64/ed64_ll.c index 9f255bb5..7a28fdef 100644 --- a/src/flashcart/ed64/ed64_ll.c +++ b/src/flashcart/ed64/ed64_ll.c @@ -30,11 +30,10 @@ /* PI dom2 release (R/W): [1:0] domain 2 device R/W release duration */ #define PI_BSD_DOM2_RLS_REG (PI_BASE_REG+0x30) /* release duration */ -#define IO_READ(addr) (*(volatile uint32_t *)PHYS_TO_K1(addr)) -#define IO_WRITE(addr,data) \ - (*(volatile uint32_t *)PHYS_TO_K1(addr)=(uint32_t)(data)) +// #define IO_READ(addr) (*(volatile uint32_t *)PHYS_TO_K1(addr)) +// #define IO_WRITE(addr,data) (*(volatile uint32_t *)PHYS_TO_K1(addr)=(uint32_t)(data)) -#define PHYS_TO_K1(x) ((uint32_t)(x)|0xA0000000) /* physical to kseg1 */ +//#define PHYS_TO_K1(x) ((uint32_t)(x)|0xA0000000) /* physical to kseg1 */ // END NOTE. @@ -115,13 +114,13 @@ typedef enum { } ed64_config_t; -#define FPGA_FW_DATA_SKIP_FW_INIT (1 << 8) -#define FPGA_FW_DATA_SKIP_TV_INIT (1 << 9) -#define FPGA_FW_DATA_TV_TYPE1 (1 << 10) -#define FPGA_FW_DATA_TV_TYPE2 (1 << 11) -#define FPGA_FW_DATA_SKIP_SD_INIT (1 << 12) -#define FPGA_FW_DATA_SD_TYPE (1 << 13) -#define FPGA_FW_DATA_HOT_START (1 << 14) +#define FPGA_FW_DATA_SKIP_FW_INIT (1 << 8) +#define FPGA_FW_DATA_SKIP_TV_INIT (1 << 9) +#define FPGA_FW_DATA_TV_TYPE1 (1 << 10) +#define FPGA_FW_DATA_TV_TYPE2 (1 << 11) +#define FPGA_FW_DATA_SKIP_SD_INIT (1 << 12) +#define FPGA_FW_DATA_SD_TYPE (1 << 13) +#define FPGA_FW_DATA_HOT_START (1 << 14) uint32_t ed64_ll_reg_read(uint32_t reg); void ed64_ll_reg_write(uint32_t reg, uint32_t data); @@ -207,8 +206,9 @@ int ed64_ll_init() { uint8_t cold_start; // TODO: take into account libCart! - IO_WRITE(PI_BSD_DOM2_LAT_REG, REG_LAT); - IO_WRITE(PI_BSD_DOM2_PWD_REG, REG_PWD); + io_write(PI_BSD_DOM2_LAT_REG, REG_LAT); + io_write(PI_BSD_DOM2_PWD_REG, REG_PWD); + dma_wait(); // Make sure the libdragon Async io methods have been performed. ed64_ll_reg_write(REG_KEY, ED64_KEY_UNLOCK); @@ -409,57 +409,75 @@ void ed64_ll_dma_write_rom(void *ram, uint32_t start_address, uint32_t slen) { /* Read from SRAM over DMA */ void ed64_ll_dma_read_sram(void *ram, uint32_t address, uint32_t length) { - - volatile uint32_t piLatReg = IO_READ(PI_BSD_DOM2_LAT_REG); - volatile uint32_t piPwdReg = IO_READ(PI_BSD_DOM2_PWD_REG); - volatile uint32_t piPgsReg = IO_READ(PI_BSD_DOM2_PGS_REG); - volatile uint32_t piRlsReg = IO_READ(PI_BSD_DOM2_RLS_REG); - - IO_WRITE(PI_BSD_DOM2_PGS_REG, 0x0D); - IO_WRITE(PI_BSD_DOM2_RLS_REG, 0x02); - IO_WRITE(PI_BSD_DOM2_LAT_REG, 0x05); - IO_WRITE(PI_BSD_DOM2_PWD_REG, 0x0C); - + // Note: seemingly the ED64 cannot read SRAM at full speed, + // so we need to slow it down temporariy! + + // Get the current timings + // TODO: is `volatile` actually needed?! + volatile uint32_t piLatReg = io_read(PI_BSD_DOM2_LAT_REG); + volatile uint32_t piPwdReg = io_read(PI_BSD_DOM2_PWD_REG); + volatile uint32_t piPgsReg = io_read(PI_BSD_DOM2_PGS_REG); + volatile uint32_t piRlsReg = io_read(PI_BSD_DOM2_RLS_REG); + dma_wait(); // Make sure the libdragon Async io methods have been performed. + + // Set slow timings + io_write(PI_BSD_DOM2_PGS_REG, 0x0D); + io_write(PI_BSD_DOM2_RLS_REG, 0x02); + io_write(PI_BSD_DOM2_LAT_REG, 0x05); + io_write(PI_BSD_DOM2_PWD_REG, 0x0C); + dma_wait(); // Make sure the libdragon Async io methods have been performed. + + // Read SRAM ed64_ll_dma_read(ram, SRAM_ADDRESS + address, length); - IO_WRITE(PI_BSD_DOM2_LAT_REG, piLatReg); - IO_WRITE(PI_BSD_DOM2_PWD_REG, piPwdReg); - IO_WRITE(PI_BSD_DOM2_PGS_REG, piPgsReg); - IO_WRITE(PI_BSD_DOM2_RLS_REG, piRlsReg); + // Restore original timings + io_write(PI_BSD_DOM2_LAT_REG, piLatReg); + io_write(PI_BSD_DOM2_PWD_REG, piPwdReg); + io_write(PI_BSD_DOM2_PGS_REG, piPgsReg); + io_write(PI_BSD_DOM2_RLS_REG, piRlsReg); + dma_wait(); // Make sure the libdragon Async io methods have been performed. } /* Write to SRAM over DMA */ void ed64_ll_dma_write_sram(void *ram, uint32_t address, uint32_t length) { - - volatile uint32_t piLatReg = IO_READ(PI_BSD_DOM2_LAT_REG); - volatile uint32_t piPwdReg = IO_READ(PI_BSD_DOM2_PWD_REG); - volatile uint32_t piPgsReg = IO_READ(PI_BSD_DOM2_PGS_REG); - volatile uint32_t piRlsReg = IO_READ(PI_BSD_DOM2_RLS_REG); - - IO_WRITE(PI_BSD_DOM2_PGS_REG, 0x0D); - IO_WRITE(PI_BSD_DOM2_RLS_REG, 0x02); - IO_WRITE(PI_BSD_DOM2_LAT_REG, 0x05); - IO_WRITE(PI_BSD_DOM2_PWD_REG, 0x0C); - + // Note: seemingly the ED64 cannot write SRAM at full speed, + // so we need to slow it down temporariy! + + // Get the current timings + // TODO: is `volatile` actually needed?! + volatile uint32_t piLatReg = io_read(PI_BSD_DOM2_LAT_REG); + volatile uint32_t piPwdReg = io_read(PI_BSD_DOM2_PWD_REG); + volatile uint32_t piPgsReg = io_read(PI_BSD_DOM2_PGS_REG); + volatile uint32_t piRlsReg = io_read(PI_BSD_DOM2_RLS_REG); + dma_wait(); // Make sure the libdragon Async io methods have been performed. + + // Set slow timings + io_write(PI_BSD_DOM2_PGS_REG, 0x0D); + io_write(PI_BSD_DOM2_RLS_REG, 0x02); + io_write(PI_BSD_DOM2_LAT_REG, 0x05); + io_write(PI_BSD_DOM2_PWD_REG, 0x0C); + dma_wait(); // Make sure the libdragon Async io methods have been performed. + + // Write SRAM ed64_ll_dma_write(ram, SRAM_ADDRESS + address, length); - - IO_WRITE(PI_BSD_DOM2_LAT_REG, piLatReg); - IO_WRITE(PI_BSD_DOM2_PWD_REG, piPwdReg); - IO_WRITE(PI_BSD_DOM2_PGS_REG, piPgsReg); - IO_WRITE(PI_BSD_DOM2_RLS_REG, piRlsReg); - + // Restore original timings + io_write(PI_BSD_DOM2_LAT_REG, piLatReg); + io_write(PI_BSD_DOM2_PWD_REG, piPwdReg); + io_write(PI_BSD_DOM2_PGS_REG, piPgsReg); + io_write(PI_BSD_DOM2_RLS_REG, piRlsReg); + dma_wait(); // Make sure the libdragon Async io methods have been performed. } -uint16_t ed64_ll_msg_rd() { +// uint16_t ed64_ll_msg_rd() { - return ed64_ll_reg_read(REG_MSG); -} +// return ed64_ll_reg_read(REG_MSG); +// } -void ed64_ll_msg_wr(uint16_t val) { +// void ed64_ll_msg_wr(uint16_t val) { - ed64_ll_reg_write(REG_MSG, val); -} +// ed64_ll_reg_write(REG_MSG, val); +// } typedef struct PI_regs_s { /** @brief Uncached address in RAM where data should be found */ @@ -480,7 +498,7 @@ void ed64_ll_dma_pi_read(void * ram_address, unsigned long pi_address, unsigned disable_interrupts(); dma_wait(); - IO_WRITE(PI_STATUS_REG, 3); + io_write(PI_STATUS_REG, 3); PI_regs->ram_address = ram_address; PI_regs->pi_address = pi_address & 0x1FFFFFFF; PI_regs->write_length = length - 1; @@ -493,7 +511,7 @@ void ed64_ll_dma_pi_write(void * ram_address, unsigned long pi_address, unsigned disable_interrupts(); dma_wait(); - IO_WRITE(PI_STATUS_REG, 3); + io_write(PI_STATUS_REG, 3); PI_regs->ram_address = ram_address; PI_regs->pi_address = pi_address & 0x1FFFFFFF; PI_regs->read_length = length - 1; @@ -587,42 +605,42 @@ void ed64_ll_unlock_regs() { /* GPIO functions */ -/* Set GPIO mode RTC */ -void ed64_ll_gpio_mode_rtc() { +// /* Set GPIO mode RTC */ +// void ed64_ll_gpio_mode_rtc() { - uint16_t cfg = ed64_ll_reg_read(REG_CFG); - cfg &= ~ED_CFG_GPIO_ON; - cfg |= ED_CFG_RTC_ON; - ed64_ll_reg_write(REG_CFG, cfg); -} +// uint16_t cfg = ed64_ll_reg_read(REG_CFG); +// cfg &= ~ED_CFG_GPIO_ON; +// cfg |= ED_CFG_RTC_ON; +// ed64_ll_reg_write(REG_CFG, cfg); +// } -/* Set GPIO mode ON */ -void ed64_ll_gpio_mode_io() { +// /* Set GPIO mode ON */ +// void ed64_ll_gpio_mode_io() { - uint16_t cfg = ed64_ll_reg_read(REG_CFG); - cfg |= ED_CFG_GPIO_ON; - ed64_ll_reg_write(REG_CFG, cfg); -} +// uint16_t cfg = ed64_ll_reg_read(REG_CFG); +// cfg |= ED_CFG_GPIO_ON; +// ed64_ll_reg_write(REG_CFG, cfg); +// } -/* Set GPIO mode OFF */ -void ed64_ll_gpio_mode_off() { +// /* Set GPIO mode OFF */ +// void ed64_ll_gpio_mode_off() { - uint16_t cfg = ed64_ll_reg_read(REG_CFG); - cfg &= ~ED_CFG_GPIO_ON; - ed64_ll_reg_write(REG_CFG, cfg); -} +// uint16_t cfg = ed64_ll_reg_read(REG_CFG); +// cfg &= ~ED_CFG_GPIO_ON; +// ed64_ll_reg_write(REG_CFG, cfg); +// } -/* GPIO mode write */ -void ed64_ll_gpio_write(uint8_t data) { +// /* GPIO mode write */ +// void ed64_ll_gpio_write(uint8_t data) { - ed64_ll_reg_write(REG_GPIO, data); -} +// ed64_ll_reg_write(REG_GPIO, data); +// } -/* GPIO mode read */ -uint8_t ed64_ll_gpio_read() { +// /* GPIO mode read */ +// uint8_t ed64_ll_gpio_read() { - return ed64_ll_reg_read(REG_GPIO); -} +// return ed64_ll_reg_read(REG_GPIO); +// } diff --git a/src/flashcart/ed64/ed64_ll.h b/src/flashcart/ed64/ed64_ll.h index 7b5f9c35..e5233cc8 100644 --- a/src/flashcart/ed64/ed64_ll.h +++ b/src/flashcart/ed64/ed64_ll.h @@ -40,8 +40,9 @@ typedef enum { // } ed64_cart_metadata_s; - +/* ED64 save location base address */ #define SRAM_ADDRESS (0xA8000000) +/* ED64 ROM location base address */ #define ROM_ADDRESS (0xB0000000) // #define USB_ERROR_FIFO_TIMEOUT 0x90 @@ -78,8 +79,8 @@ void ed64_ll_set_save_type(ed64_save_type_t type); /* reads metadata related to the assembily date and cart capabilities */ void ed64_ll_read_cart_metadata(void *dest); -uint16_t ed64_ll_msg_rd(); -void ed64_ll_msg_wr(uint16_t val); +// uint16_t ed64_ll_msg_rd(); +// void ed64_ll_msg_wr(uint16_t val); void ed64_ll_lock_regs(); void ed64_ll_unlock_regs(); diff --git a/src/flashcart/flashcart.c b/src/flashcart/flashcart.c index 0541a957..9fc4fbda 100644 --- a/src/flashcart/flashcart.c +++ b/src/flashcart/flashcart.c @@ -98,7 +98,7 @@ flashcart_err_t flashcart_init (void) { case CART_EDX: // Series X EverDrive-64 break; - case CART_ED: // Original EverDrive-64 + case CART_ED: // Original EverDrive-64 (V-Series & Clones) flashcart = ed64_get_flashcart(); break; From 5d50f9063179c170eee6a3fe9357a2561ac6d450 Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Fri, 29 Dec 2023 19:36:20 +0000 Subject: [PATCH 46/64] Correct EEPROM size --- src/flashcart/ed64/ed64.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/flashcart/ed64/ed64.c b/src/flashcart/ed64/ed64.c index 538e2a03..9b0d0202 100644 --- a/src/flashcart/ed64/ed64.c +++ b/src/flashcart/ed64/ed64.c @@ -180,7 +180,7 @@ static flashcart_err_t ed64_load_save (char *save_path) { eeprom_write_bytes(eeprom_contents, 0, KiB(2)); } else { - eeprom_write_bytes(eeprom_contents, 0, KiB(1)); + eeprom_write_bytes(eeprom_contents, 0, 512); } } From ad739eda299af61457831331d0da690d26e5af37 Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Fri, 29 Dec 2023 19:54:26 +0000 Subject: [PATCH 47/64] Readme improvements --- README.md | 41 +++++++++++++++++++++++++++++++---------- 1 file changed, 31 insertions(+), 10 deletions(-) diff --git a/README.md b/README.md index f6670732..796f854e 100644 --- a/README.md +++ b/README.md @@ -18,7 +18,6 @@ An open source menu for N64 flashcarts. ### Video showcase (as of Oct 12 2023) - [![N64FlashcartMenu Showcase](http://img.youtube.com/vi/6CKImHTifDA/0.jpg)](http://www.youtube.com/watch?v=6CKImHTifDA "N64FlashcartMenu Showcase (Oct 12 2023)") @@ -51,6 +50,7 @@ Menu currently supports the following emulators and associated ROM file names: - **Game Boy** / **GB Color**: [gb64](https://lambertjamesd.github.io/gb64/romwrapper/romwrapper.html) by *lambertjamesd* - `gb.v64` / `gbc.v64` - **Sega Master System** / **Sega Game Gear** / **Sg1000**: [TotalSMS](https://github.com/ITotalJustice/TotalSMS) - `TotalSMS.z64` (Currently broken) + ### Menu Settings The Menu creates a `config.ini` file in `sd:/menu/` which contains various settings that are used by the menu. Currently these are read-only (can be viewed in the menu by pressing `L` on the Joypad). @@ -60,6 +60,7 @@ If required, you can manually adjust the file on the SD card using your computer - Ensure the cart has the latest [firmware](https://github.com/Polprzewodnikowy/SummerCart64/releases/latest) installed. - Download the latest `sc64menu.n64` file from the releases page, then put it in the root directory of your SD card. + ##### 64DD disk support For the ability to load and run 64DD disk images, you need to add the folder `/menu/64ddipl` on the SD card. Download and add the relevant ipl files and rename them before adding them to the folder: @@ -78,14 +79,28 @@ Note: to load an expansion disk (e.g. F-Zero X) browse to the N64 ROM and load i ### ED64 & ED64P Specific Currently not supported, but work is in progress (See [PR's](https://github.com/Polprzewodnikowy/N64FlashcartMenu/pulls)). -The aim is to replace [Altra64](https://github.com/networkfusion/altra64) and [ED64-UnofficialOS](https://github.com/n64-tools/ED64-UnofficialOS-binaries). +**WiP** The aim is to replace [Altra64](https://github.com/networkfusion/altra64) and [ED64-UnofficialOS](https://github.com/n64-tools/ED64-UnofficialOS-binaries). -# Developer documentation +#### ED64 +Download the `ED64.v64` ROM from the latest action run assets and place it in the `/ED64` folder. + +#### ED64P +Download the `ED64P.v64` ROM from the latest action run assets and place it in the `/ED64P` folder. + + +# Developer documentation You can use a dev container in VSCode to ease development. +## To Build: +`ms-vscode.makefile-tools` will help (installed automatically in dev container). +TODO: it does not yet work with `F5`: see https://devblogs.microsoft.com/cppblog/now-announcing-makefile-support-in-visual-studio-code/ +WORKAROUND: in the dev container terminal, use make directly, i.e.: `make all` +The ROMs can be found in the `output` directory. + + ## To deploy: ### SC64 * Download the deployer [here](https://github.com/Polprzewodnikowy/SummerCart64/releases/download/v2.18.0/sc64-deployer-windows-v2.18.0.zip) @@ -104,20 +119,24 @@ Then in the dev container, use `make run` or `make run-debug` #### From your host (Windows) OS - * Run `./localdeploy.bat` from the terminal Toggle the N64 power switch to load the ROM. -`ms-vscode.makefile-tools` will help (installed automatically in dev container). -TODO: it does not yet work with `F5`: see https://devblogs.microsoft.com/cppblog/now-announcing-makefile-support-in-visual-studio-code/ -WORKAROUND: in the dev container terminal, use make directly, i.e.: `make` -The ROM can be found in the `output` directory. -NOTE: a "release" version of the SC64 menu is called `sc64menu.n64` and can be created for when you want to add it directly to the SDCard. This is generated by running `make all` or running `make sc64`. +#### From the SD Card +A "release" version of the SC64 menu is called `sc64menu.n64` and can be created for when you want to add it directly to the root folder on the SDCard. This is generated by running `make all` or running `make sc64`. -### Others +### ED64 V3 over USB from your host (Windows) OS +* Download the UNFLoader [here](https://github.com/buu342/N64-UNFLoader/releases/download/v2.11/UNFLoader-Windows-x86.zip) +* Extract and place `UNFLoader.exe` in the `tools` directory. +* Ensure the current "official menu" is `V3.06`. +* Run the appropriate command from windows cmd prompt to ensure your current directory is the root project directory. +* Upload the ROM (e.g. `./tools/UNFLoader.exe -r ./output/OS64.v64`) + + +### Others (non USB) * Add the required file to the correct folder on your SD card. @@ -125,6 +144,7 @@ NOTE: a "release" version of the SC64 menu is called `sc64menu.n64` and can be c This repo currently uses the `unstable` branch as a submodule at a specific commit. To update to the latest version, use `git submodule update --remote ` from the terminal. + # Generate documentation Run `doxygen` from the dev container terminal. Make sure you fix the warnings before creating a PR! @@ -132,6 +152,7 @@ Generated documentation is located in `output/docs` folder and auto published to Once merged, they can be viewed [here](https://polprzewodnikowy.github.io/N64FlashcartMenu/) + # Open source software and licenses used - [libdragon](https://github.com/DragonMinded/libdragon) (UNLICENSE License) - [libspng](https://github.com/randy408/libspng) (BSD 2-Clause License) From d1ec7b5f6c33207ea291541e264259eee6893b63 Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Fri, 29 Dec 2023 19:57:09 +0000 Subject: [PATCH 48/64] Update .gitignore --- .gitignore | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.gitignore b/.gitignore index 2cfc2261..de80dacb 100644 --- a/.gitignore +++ b/.gitignore @@ -2,7 +2,7 @@ /build /filesystem /output -/tools/sc64/* +/tools/* # There should never be ROMs uploaded, but just incase, make sure they are excluded. **/*.n64 From 0b348acab847d0d393f3fda10e0cea7d9540914c Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Fri, 29 Dec 2023 21:21:13 +0000 Subject: [PATCH 49/64] Fix ability to deploy and debug As required by V3 to fall through due to need of F/W 3.06 and UNFLoader. --- src/flashcart/flashcart.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/flashcart/flashcart.c b/src/flashcart/flashcart.c index 9fc4fbda..f473e322 100644 --- a/src/flashcart/flashcart.c +++ b/src/flashcart/flashcart.c @@ -97,7 +97,7 @@ flashcart_err_t flashcart_init (void) { break; case CART_EDX: // Series X EverDrive-64 - break; + // break; // FIXME: Commented out as required to fall through due to need of F/W 3.06 and UNFLoader. case CART_ED: // Original EverDrive-64 (V-Series & Clones) flashcart = ed64_get_flashcart(); break; From df207a3e8c8f738cbe212b5e3ab61616bc5dde4c Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Fri, 29 Dec 2023 22:05:49 +0000 Subject: [PATCH 50/64] Fix loading eeprom --- src/flashcart/ed64/ed64.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/flashcart/ed64/ed64.c b/src/flashcart/ed64/ed64.c index 9b0d0202..add3610b 100644 --- a/src/flashcart/ed64/ed64.c +++ b/src/flashcart/ed64/ed64.c @@ -149,7 +149,7 @@ static flashcart_err_t ed64_load_save (char *save_path) { FIL fil; UINT br; - if (f_open(&fil, strip_sd_prefix(save_path), FA_CREATE_ALWAYS | FA_READ) != FR_OK) { // FIXME: create always is a hack to ensure we always have a valid save. + if (f_open(&fil, strip_sd_prefix(save_path), FA_READ) != FR_OK) { return FLASHCART_ERR_LOAD; } @@ -225,7 +225,7 @@ static flashcart_err_t ed64_set_save_type (flashcart_save_type_t save_type) { ed64_ll_set_save_type(type); - // TODO: set pesudo save writeback. + // TODO: set pseudo save writeback. // as a start, create the file?! return FLASHCART_OK; From 20619a4ec9744e3fcf328e8fd84d3fe73c4e531f Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Fri, 29 Dec 2023 22:39:51 +0000 Subject: [PATCH 51/64] Add device information function --- src/flashcart/64drive/64drive.c | 1 + src/flashcart/ed64/ed64.c | 1 + src/flashcart/flashcart.c | 1 + src/flashcart/flashcart.h | 2 ++ src/flashcart/sc64/sc64.c | 1 + 5 files changed, 6 insertions(+) diff --git a/src/flashcart/64drive/64drive.c b/src/flashcart/64drive/64drive.c index 6bcee6cb..54efab2c 100644 --- a/src/flashcart/64drive/64drive.c +++ b/src/flashcart/64drive/64drive.c @@ -273,6 +273,7 @@ static flashcart_t flashcart_d64 = { .load_64dd_disk = NULL, .set_save_type = d64_set_save_type, .set_save_writeback = d64_set_save_writeback, + .get_device_info = NULL, }; diff --git a/src/flashcart/ed64/ed64.c b/src/flashcart/ed64/ed64.c index add3610b..da4a9807 100644 --- a/src/flashcart/ed64/ed64.c +++ b/src/flashcart/ed64/ed64.c @@ -243,6 +243,7 @@ static flashcart_t flashcart_ed64 = { .load_64dd_disk = NULL, .set_save_type = ed64_set_save_type, .set_save_writeback = NULL, + .get_device_info = NULL, }; diff --git a/src/flashcart/flashcart.c b/src/flashcart/flashcart.c index f473e322..6f0563e6 100644 --- a/src/flashcart/flashcart.c +++ b/src/flashcart/flashcart.c @@ -57,6 +57,7 @@ static flashcart_t *flashcart = &((flashcart_t) { .load_save = NULL, .set_save_type = NULL, .set_save_writeback = NULL, + .get_device_info = NULL, }); #ifdef NDEBUG diff --git a/src/flashcart/flashcart.h b/src/flashcart/flashcart.h index 0e97e807..71fa9faf 100644 --- a/src/flashcart/flashcart.h +++ b/src/flashcart/flashcart.h @@ -74,6 +74,8 @@ typedef struct { flashcart_err_t (*set_save_type) (flashcart_save_type_t save_type); /** @brief The flashcart set save writeback function */ flashcart_err_t (*set_save_writeback) (uint32_t *sectors); + /** @brief The flashcart device information function */ + flashcart_err_t (*get_device_info) (void); } flashcart_t; diff --git a/src/flashcart/sc64/sc64.c b/src/flashcart/sc64/sc64.c index a0878c9d..da4b7d87 100644 --- a/src/flashcart/sc64/sc64.c +++ b/src/flashcart/sc64/sc64.c @@ -579,6 +579,7 @@ static flashcart_t flashcart_sc64 = { .load_64dd_disk = sc64_load_64dd_disk, .set_save_type = sc64_set_save_type, .set_save_writeback = sc64_set_save_writeback, + .get_device_info = NULL, }; From af742a2a70146e2420018f0c47f41b293417c0d2 Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Fri, 29 Dec 2023 22:48:00 +0000 Subject: [PATCH 52/64] Add RTC feature --- src/flashcart/64drive/64drive.c | 1 + src/flashcart/ed64/ed64.c | 1 + src/flashcart/flashcart.h | 1 + src/flashcart/sc64/sc64.c | 1 + 4 files changed, 4 insertions(+) diff --git a/src/flashcart/64drive/64drive.c b/src/flashcart/64drive/64drive.c index 54efab2c..8fe51378 100644 --- a/src/flashcart/64drive/64drive.c +++ b/src/flashcart/64drive/64drive.c @@ -73,6 +73,7 @@ static flashcart_err_t d64_deinit (void) { static bool d64_has_feature (flashcart_features_t feature) { switch (feature) { case FLASHCART_FEATURE_64DD: return false; + case FLASHCART_FEATURE_RTC: return true; default: return false; } } diff --git a/src/flashcart/ed64/ed64.c b/src/flashcart/ed64/ed64.c index da4a9807..db556c40 100644 --- a/src/flashcart/ed64/ed64.c +++ b/src/flashcart/ed64/ed64.c @@ -52,6 +52,7 @@ static flashcart_err_t ed64_deinit (void) { static bool ed64_has_feature (flashcart_features_t feature) { switch (feature) { case FLASHCART_FEATURE_64DD: return false; + case FLASHCART_FEATURE_RTC: return false; // FIXME: if it is a V3 we should return true! default: return false; } } diff --git a/src/flashcart/flashcart.h b/src/flashcart/flashcart.h index 71fa9faf..452c36cc 100644 --- a/src/flashcart/flashcart.h +++ b/src/flashcart/flashcart.h @@ -27,6 +27,7 @@ typedef enum { /** @brief List of optional supported flashcart features */ typedef enum { FLASHCART_FEATURE_64DD, + FLASHCART_FEATURE_RTC, } flashcart_features_t; /** @brief Flashcart save type enumeration */ diff --git a/src/flashcart/sc64/sc64.c b/src/flashcart/sc64/sc64.c index da4b7d87..85bf2d96 100644 --- a/src/flashcart/sc64/sc64.c +++ b/src/flashcart/sc64/sc64.c @@ -260,6 +260,7 @@ static flashcart_err_t sc64_deinit (void) { static bool sc64_has_feature (flashcart_features_t feature) { switch (feature) { case FLASHCART_FEATURE_64DD: return true; + case FLASHCART_FEATURE_RTC: return true; default: return false; } } From 6c3e09adbaaeb45b9c652833905769b16025fe7e Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Fri, 29 Dec 2023 23:26:08 +0000 Subject: [PATCH 53/64] Add flashcart info menu --- Makefile | 1 + src/menu/menu.c | 1 + src/menu/menu_state.h | 1 + src/menu/views/browser.c | 5 ++++ src/menu/views/flashcart_info.c | 46 +++++++++++++++++++++++++++++++++ src/menu/views/views.h | 3 +++ 6 files changed, 57 insertions(+) create mode 100644 src/menu/views/flashcart_info.c diff --git a/Makefile b/Makefile index 61814b3f..e59f3a44 100644 --- a/Makefile +++ b/Makefile @@ -65,6 +65,7 @@ SRCS = \ menu/views/system_info.c \ menu/views/settings_editor.c \ menu/views/rtc.c \ + menu/views/flashcart_info.c \ utils/fs.c FONTS = \ diff --git a/src/menu/menu.c b/src/menu/menu.c index 3e695f0d..976ae309 100644 --- a/src/menu/menu.c +++ b/src/menu/menu.c @@ -149,6 +149,7 @@ static struct views_s { { view_credits_init, view_credits_display }, // MENU_MODE_CREDITS { view_settings_init, view_settings_display }, // MENU_MODE_SETTINGS_EDITOR { view_rtc_init, view_rtc_display }, // MENU_MODE_RTC + { view_flashcart_info_init, view_flashcart_info_display }, // MENU_MODE_FLASHCART { view_load_rom_init, view_load_rom_display }, // MENU_MODE_LOAD_ROM { view_load_disk_init, view_load_disk_display }, // MENU_MODE_LOAD_DISK { view_load_emulator_init, view_load_emulator_display }, // MENU_MODE_LOAD_EMULATOR diff --git a/src/menu/menu_state.h b/src/menu/menu_state.h index d29573d4..3a004ad7 100644 --- a/src/menu/menu_state.h +++ b/src/menu/menu_state.h @@ -33,6 +33,7 @@ typedef enum { MENU_MODE_CREDITS, MENU_MODE_SETTINGS_EDITOR, MENU_MODE_RTC, + MENU_MODE_FLASHCART, MENU_MODE_LOAD_ROM, MENU_MODE_LOAD_DISK, MENU_MODE_LOAD_EMULATOR, diff --git a/src/menu/views/browser.c b/src/menu/views/browser.c index 75ab0a4a..8bfe36a9 100644 --- a/src/menu/views/browser.c +++ b/src/menu/views/browser.c @@ -244,12 +244,17 @@ static void edit_rtc (menu_t *menu) { menu->next_mode = MENU_MODE_RTC; } +static void show_flashcart_info (menu_t *menu) { + menu->next_mode = MENU_MODE_FLASHCART; +} + static component_context_menu_t settings_context_menu = { .list = { { .text = "Edit settings", .action = edit_settings }, { .text = "Show system info", .action = show_system_info }, { .text = "Show credits", .action = show_credits }, { .text = "Adjust RTC", .action = edit_rtc }, + { .text = "Show cart info", .action = show_flashcart_info }, COMPONENT_CONTEXT_MENU_LIST_END, } }; diff --git a/src/menu/views/flashcart_info.c b/src/menu/views/flashcart_info.c new file mode 100644 index 00000000..084cc073 --- /dev/null +++ b/src/menu/views/flashcart_info.c @@ -0,0 +1,46 @@ +#include "views.h" + + +static void process (menu_t *menu) { + if (menu->actions.back) { + menu->next_mode = MENU_MODE_BROWSER; + } +} + +static void draw (menu_t *menu, surface_t *d) { + rdpq_attach(d, NULL); + + component_background_draw(); + + component_layout_draw(); + + component_main_text_draw( + ALIGN_CENTER, VALIGN_TOP, + "FLASHCART INFORMATION\n" + ); + + component_main_text_draw( + ALIGN_LEFT, VALIGN_TOP, + "\n" + "\n" + ); + + + component_actions_bar_text_draw( + ALIGN_LEFT, VALIGN_TOP, + "\n" + "B: Back" + ); + + rdpq_detach_show(); +} + + +void view_flashcart_info_init (menu_t *menu) { + // Nothing to initialize (yet) +} + +void view_flashcart_info_display (menu_t *menu, surface_t *display) { + process(menu); + draw(menu, display); +} diff --git a/src/menu/views/views.h b/src/menu/views/views.h index 2b7e0660..4990920c 100644 --- a/src/menu/views/views.h +++ b/src/menu/views/views.h @@ -50,6 +50,9 @@ void view_settings_display (menu_t *menu, surface_t *display); void view_rtc_init (menu_t *menu); void view_rtc_display (menu_t *menu, surface_t *display); +void view_flashcart_info_init (menu_t *menu); +void view_flashcart_info_display (menu_t *menu, surface_t *display); + void view_load_emulator_init (menu_t *menu); void view_load_emulator_display (menu_t *menu, surface_t *display); From 4ef726fca9a840aaadb482ee1fdfbe4c7f115969 Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Sat, 30 Dec 2023 00:26:04 +0000 Subject: [PATCH 54/64] Add device info struct --- src/flashcart/ed64/ed64.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/src/flashcart/ed64/ed64.h b/src/flashcart/ed64/ed64.h index 8680b592..03cdb8d1 100644 --- a/src/flashcart/ed64/ed64.h +++ b/src/flashcart/ed64/ed64.h @@ -16,6 +16,16 @@ * @{ */ +typedef struct { + uint16_t hardware_series; + uint16_t hardware_revision; + uint16_t fpga_firmware_version; + uint16_t cpld_firmware_version; + uint16_t manufacture_date; + uint16_t manufacture_time; + uint16_t serial_number; +} flashcart_information_type; + flashcart_t *ed64_get_flashcart (void); /** @} */ /* ed64 */ From c943a8dccf5f2330232cbcc20981da9cb44ea630 Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Sat, 30 Dec 2023 01:58:43 +0000 Subject: [PATCH 55/64] commented out changes --- src/flashcart/ed64/ed64.c | 17 ++++++++++++++++- src/flashcart/ed64/ed64.h | 10 ---------- src/flashcart/ed64/ed64_ll.c | 2 +- 3 files changed, 17 insertions(+), 12 deletions(-) diff --git a/src/flashcart/ed64/ed64.c b/src/flashcart/ed64/ed64.c index db556c40..76ef9cff 100644 --- a/src/flashcart/ed64/ed64.c +++ b/src/flashcart/ed64/ed64.c @@ -12,6 +12,15 @@ #include "ed64_ll.h" #include "ed64.h" +typedef struct { + uint16_t hardware_series; + uint16_t hardware_revision; + uint16_t fpga_firmware_version; + uint16_t cpld_firmware_version; + uint16_t manufacture_date; + uint16_t manufacture_time; + uint16_t serial_number; +} flashcart_info_t; extern int ed_exit(void); @@ -232,6 +241,12 @@ static flashcart_err_t ed64_set_save_type (flashcart_save_type_t save_type) { return FLASHCART_OK; } +// static flashcart_info_t ed64_get_cart_info (void) { +// flashcart_info_t device_info; + +// return device_info; +// } + static flashcart_t flashcart_ed64 = { .init = ed64_init, @@ -244,7 +259,7 @@ static flashcart_t flashcart_ed64 = { .load_64dd_disk = NULL, .set_save_type = ed64_set_save_type, .set_save_writeback = NULL, - .get_device_info = NULL, + .get_device_info = NULL, //ed64_get_cart_info, }; diff --git a/src/flashcart/ed64/ed64.h b/src/flashcart/ed64/ed64.h index 03cdb8d1..8680b592 100644 --- a/src/flashcart/ed64/ed64.h +++ b/src/flashcart/ed64/ed64.h @@ -16,16 +16,6 @@ * @{ */ -typedef struct { - uint16_t hardware_series; - uint16_t hardware_revision; - uint16_t fpga_firmware_version; - uint16_t cpld_firmware_version; - uint16_t manufacture_date; - uint16_t manufacture_time; - uint16_t serial_number; -} flashcart_information_type; - flashcart_t *ed64_get_flashcart (void); /** @} */ /* ed64 */ diff --git a/src/flashcart/ed64/ed64_ll.c b/src/flashcart/ed64/ed64_ll.c index 7a28fdef..15aec7b0 100644 --- a/src/flashcart/ed64/ed64_ll.c +++ b/src/flashcart/ed64/ed64_ll.c @@ -136,7 +136,7 @@ void ed64_ll_dma_read_sram(void *ram, uint32_t address, uint32_t length); void ed64_ll_dma_write_sram(void *ram, uint32_t address, uint32_t length); // static uint16_t spi_cfg; -uint8_t ed64_ll_sram_bank; +uint8_t ed64_ll_sram_bank = 1; ed64_save_type_t ed64_ll_save_type; #define REG_LAT 0x04 From f8cbbb2048113a88d4a7fb94bfd60d9f6ec6c7fe Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Sun, 31 Dec 2023 23:09:49 +0000 Subject: [PATCH 56/64] Changes towards libcart --- Makefile | 4 +- src/flashcart/ed64/ed64.c | 25 +- src/flashcart/ed64/ed64_ll.c | 810 +++++++++++++++++------------------ src/flashcart/ed64/ed64_ll.h | 39 +- src/flashcart/flashcart.c | 3 +- 5 files changed, 427 insertions(+), 454 deletions(-) diff --git a/Makefile b/Makefile index e59f3a44..c6f65f7a 100644 --- a/Makefile +++ b/Makefile @@ -19,14 +19,14 @@ SRCS = \ boot/boot.c \ boot/cic.c \ boot/reboot.S \ + flashcart/flashcart_utils.c \ + flashcart/flashcart.c \ flashcart/64drive/64drive_ll.c \ flashcart/64drive/64drive.c \ flashcart/sc64/sc64_ll.c \ flashcart/sc64/sc64.c \ flashcart/ed64/ed64_ll.c \ flashcart/ed64/ed64.c \ - flashcart/flashcart_utils.c \ - flashcart/flashcart.c \ libs/libspng/spng/spng.c \ libs/mini.c/src/mini.c \ libs/miniz/miniz_tdef.c \ diff --git a/src/flashcart/ed64/ed64.c b/src/flashcart/ed64/ed64.c index 76ef9cff..cb0b97bb 100644 --- a/src/flashcart/ed64/ed64.c +++ b/src/flashcart/ed64/ed64.c @@ -12,28 +12,19 @@ #include "ed64_ll.h" #include "ed64.h" -typedef struct { - uint16_t hardware_series; - uint16_t hardware_revision; - uint16_t fpga_firmware_version; - uint16_t cpld_firmware_version; - uint16_t manufacture_date; - uint16_t manufacture_time; - uint16_t serial_number; -} flashcart_info_t; - -extern int ed_exit(void); +// static ed64_variant_t device_variant_id = ED64_VARIANT_UNKNOWN; +// static ed64_save_type_t current_save_type = SAVE_TYPE_NONE; static flashcart_err_t ed64_init (void) { // TODO: partly already done, see https://github.com/DragonMinded/libdragon/blob/4ec469d26b6dc4e308caf3d5b86c2b340b708bbd/src/libcart/cart.c#L1064 - //ed64_ll_unlock_regs(); + // ed64_ll_unlock_regs(); // ed64_ll_init(); // FIXME: this causes a crash! // ed64_ll_reset_spx(); // only required if V2+ FW is updating! - // ed64_ll_set_ram_bank(1); // Seemingly bank 0 (for SRAM 128k) is only supported on V3 and it is not the default. + // ed64_ll_set_sram_bank(1); // Seemingly bank 0 (for SRAM 128k) is only supported on V3 and it is not the default. // If a V3 or X7 cart is detected (has a battery?), enable RTC, // ed64_ll_gpio_mode_rtc(); @@ -50,11 +41,6 @@ static flashcart_err_t ed64_init (void) { static flashcart_err_t ed64_deinit (void) { - // ed64_ll_gpio_mode_off(); // On V3 or X7, this should be ed64_bios_gpio_mode_rtc() if it is required. - - // For the moment, just use libCart exit. - ed_exit(); - return FLASHCART_OK; } @@ -235,8 +221,9 @@ static flashcart_err_t ed64_set_save_type (flashcart_save_type_t save_type) { ed64_ll_set_save_type(type); + // FIXME: diagnose why this is not seemingly set! + // TODO: set pseudo save writeback. - // as a start, create the file?! return FLASHCART_OK; } diff --git a/src/flashcart/ed64/ed64_ll.c b/src/flashcart/ed64/ed64_ll.c index 15aec7b0..9680e130 100644 --- a/src/flashcart/ed64/ed64_ll.c +++ b/src/flashcart/ed64/ed64_ll.c @@ -3,37 +3,155 @@ #include "../flashcart_utils.h" #include "ed64_ll.h" -// NOTE: these are a replica of libcart cart.c defines! -#define PI_BASE_REG (0x04600000) -#define PI_STATUS_REG (PI_BASE_REG+0x10) +// NOTE: these are a near replica of libcart cart.c defines and functions! -#define PI_BSD_DOM1_LAT_REG (PI_BASE_REG+0x14) +#define PI_BASE_REG (0x04600000) +#define PI_STATUS_REG (PI_BASE_REG+0x10) + +#define PI_BSD_DOM1_LAT_REG (PI_BASE_REG+0x14) /* PI dom1 pulse width (R/W): [7:0] domain 1 device R/W strobe pulse width */ -#define PI_BSD_DOM1_PWD_REG (PI_BASE_REG+0x18) +#define PI_BSD_DOM1_PWD_REG (PI_BASE_REG+0x18) /* PI dom1 page size (R/W): [3:0] domain 1 device page size */ -#define PI_BSD_DOM1_PGS_REG (PI_BASE_REG+0x1C) /* page size */ +#define PI_BSD_DOM1_PGS_REG (PI_BASE_REG+0x1C) /* page size */ /* PI dom1 release (R/W): [1:0] domain 1 device R/W release duration */ -#define PI_BSD_DOM1_RLS_REG (PI_BASE_REG+0x20) +#define PI_BSD_DOM1_RLS_REG (PI_BASE_REG+0x20) /* PI dom2 latency (R/W): [7:0] domain 2 device latency */ -#define PI_BSD_DOM2_LAT_REG (PI_BASE_REG+0x24) /* Domain 2 latency */ +#define PI_BSD_DOM2_LAT_REG (PI_BASE_REG+0x24) /* Domain 2 latency */ /* PI dom2 pulse width (R/W): [7:0] domain 2 device R/W strobe pulse width */ -#define PI_BSD_DOM2_PWD_REG (PI_BASE_REG+0x28) /* pulse width */ +#define PI_BSD_DOM2_PWD_REG (PI_BASE_REG+0x28) /* pulse width */ /* PI dom2 page size (R/W): [3:0] domain 2 device page size */ -#define PI_BSD_DOM2_PGS_REG (PI_BASE_REG+0x2C) /* page size */ +#define PI_BSD_DOM2_PGS_REG (PI_BASE_REG+0x2C) /* page size */ /* PI dom2 release (R/W): [1:0] domain 2 device R/W release duration */ -#define PI_BSD_DOM2_RLS_REG (PI_BASE_REG+0x30) /* release duration */ +#define PI_BSD_DOM2_RLS_REG (PI_BASE_REG+0x30) /* release duration */ + +#define IO_READ(addr) (*(volatile uint32_t *)PHYS_TO_K1(addr)) +#define IO_WRITE(addr,data) (*(volatile uint32_t *)PHYS_TO_K1(addr)=(uint32_t)(data)) + +#define PHYS_TO_K1(x) ((uint32_t)(x)|0xA0000000) /* physical to kseg1 */ + +#define CART_ABORT() {__cart_acs_rel(); return -1;} + +/* Temporary buffer aligned for DMA */ +//__attribute__((aligned(16))) static uint64_t __cart_buf[512/8]; + +static uint32_t __cart_dom1_rel; +static uint32_t __cart_dom2_rel; +uint32_t cart_dom1 = 0x8030FFFF; // FIXME: Added as should already be initialized. +uint32_t cart_dom2 = 0x80370404; // FIXME: Added as should already be initialized. + +//uint32_t cart_size; + +static void __cart_acs_get(void) +{ + /* Save PI BSD configuration and reconfigure */ + if (cart_dom1) + { + __cart_dom1_rel = + IO_READ(PI_BSD_DOM1_LAT_REG) << 0 | + IO_READ(PI_BSD_DOM1_PWD_REG) << 8 | + IO_READ(PI_BSD_DOM1_PGS_REG) << 16 | + IO_READ(PI_BSD_DOM1_RLS_REG) << 20 | + 1 << 31; + IO_WRITE(PI_BSD_DOM1_LAT_REG, cart_dom1 >> 0); + IO_WRITE(PI_BSD_DOM1_PWD_REG, cart_dom1 >> 8); + IO_WRITE(PI_BSD_DOM1_PGS_REG, cart_dom1 >> 16); + IO_WRITE(PI_BSD_DOM1_RLS_REG, cart_dom1 >> 20); + } + if (cart_dom2) + { + __cart_dom2_rel = + IO_READ(PI_BSD_DOM2_LAT_REG) << 0 | + IO_READ(PI_BSD_DOM2_PWD_REG) << 8 | + IO_READ(PI_BSD_DOM2_PGS_REG) << 16 | + IO_READ(PI_BSD_DOM2_RLS_REG) << 20 | + 1 << 31; + IO_WRITE(PI_BSD_DOM2_LAT_REG, cart_dom2 >> 0); + IO_WRITE(PI_BSD_DOM2_PWD_REG, cart_dom2 >> 8); + IO_WRITE(PI_BSD_DOM2_PGS_REG, cart_dom2 >> 16); + IO_WRITE(PI_BSD_DOM2_RLS_REG, cart_dom2 >> 20); + } +} -// #define IO_READ(addr) (*(volatile uint32_t *)PHYS_TO_K1(addr)) -// #define IO_WRITE(addr,data) (*(volatile uint32_t *)PHYS_TO_K1(addr)=(uint32_t)(data)) +static void __cart_acs_rel(void) +{ + /* Restore PI BSD configuration */ + if (__cart_dom1_rel) + { + IO_WRITE(PI_BSD_DOM1_LAT_REG, __cart_dom1_rel >> 0); + IO_WRITE(PI_BSD_DOM1_PWD_REG, __cart_dom1_rel >> 8); + IO_WRITE(PI_BSD_DOM1_PGS_REG, __cart_dom1_rel >> 16); + IO_WRITE(PI_BSD_DOM1_RLS_REG, __cart_dom1_rel >> 20); + __cart_dom1_rel = 0; + } + if (__cart_dom2_rel) + { + IO_WRITE(PI_BSD_DOM2_LAT_REG, __cart_dom2_rel >> 0); + IO_WRITE(PI_BSD_DOM2_PWD_REG, __cart_dom2_rel >> 8); + IO_WRITE(PI_BSD_DOM2_PGS_REG, __cart_dom2_rel >> 16); + IO_WRITE(PI_BSD_DOM2_RLS_REG, __cart_dom2_rel >> 20); + __cart_dom2_rel = 0; + } +} -//#define PHYS_TO_K1(x) ((uint32_t)(x)|0xA0000000) /* physical to kseg1 */ +static void __cart_dma_rd(void *dram, uint32_t cart, uint32_t size) +{ + data_cache_hit_writeback_invalidate(dram, size); + dma_read_raw_async(dram, cart, size); + dma_wait(); +} + +static void __cart_dma_wr(const void *dram, uint32_t cart, uint32_t size) +{ + data_cache_hit_writeback((void *)dram, size); + dma_write_raw_async(dram, cart, size); + dma_wait(); +} + +/* ED64 registers base address */ +#define ED_BASE_REG (0xA8040000) // FIXME: Or should it be `0x08040000` like libcart? + +/* ED64 config register */ +#define ED_CFG_REG (ED_BASE_REG+0x00) +/* ED64 status register */ +#define ED_STATUS_REG (ED_BASE_REG+0x04) +/* ED64 DMA Length register */ +#define ED_DMA_LEN_REG (ED_BASE_REG+0x08) +/* ED64 DMA Address register */ +#define ED_DMA_ADDR_REG (ED_BASE_REG+0x0C) +/* ED64 Message/Data register */ +#define ED_MSG_REG (ED_BASE_REG+0x10) +/* ED64 DMA Config register */ +#define ED_DMA_CFG_REG (ED_BASE_REG+0x14) +/* ED64 SPI register */ +#define ED_SPI_REG (ED_BASE_REG+0x18) +/* ED64 SPI Config register */ +#define ED_SPI_CFG_REG (ED_BASE_REG+0x1C) +/* ED64 Unlock register */ +#define ED_KEY_REG (ED_BASE_REG+0x20) +/* ED64 Save Config register */ +#define ED_SAV_CFG_REG (ED_BASE_REG+0x24) +#define ED_SEC_REG (ED_BASE_REG+0x28) /* Sectors?? */ +#define ED_VER_REG (ED_BASE_REG+0x2C) /* Hardware series version + firmware rev */ +/* ED64 GPIO register */ +#define ED_GPIO_REG (ED_BASE_REG+0x30) +// Unknown regs (if any) +/* ED64 Config Count register */ +#define ED_CFG_CNT_REG (ED_BASE_REG+0x40) +/* ED64 Config Data register */ +#define ED_CFG_DAT_REG (ED_BASE_REG+0x44) +#define ED_CPLD_MSG_REG (ED_BASE_REG+0x48) // NOTE: was `ED_MAX_MSG_REG` /* Altera (Intel) MAX */ +#define ED_CPLD_VER_REG (ED_BASE_REG+0x4C) // NOTE: Was `ED_CRC_REG` +/* ED64 FlashRAM Address register (V3 series only) */ +#define ED_FLASHRAM_ADDR_REG (ED_BASE_REG+0x50) +/* ED64 FlashRAM Message/Data register (V3 series only) */ +#define ED_FLASHRAM_MSG_REG (ED_BASE_REG+0x54) // END NOTE. @@ -43,232 +161,188 @@ /* Unlocks the ED64 registers */ #define ED64_KEY_UNLOCK 0x1234 -/* ED64 registers base address */ -#define ED64_REGS_BASE (0xA8040000) - -typedef enum { - REG_CFG = 0, - REG_STATUS = 1, - REG_DMA_LENGTH = 2, - REG_DMA_RAM_ADDR = 3, - REG_MSG = 4, - REG_DMA_CFG = 5, - REG_SPI = 6, - REG_SPI_CFG = 7, - REG_KEY = 8, - REG_SAV_CFG = 9, - REG_SEC = 10, /* Sectors?? */ - REG_FPGA_VERSION = 11, /* Altera (Intel) MAX */ - REG_GPIO = 12, - -} ed64_registers_t; - - -typedef enum { - REG_CFG_COUNT = 16, - REG_CFG_DATA = 17, - REG_FPGA_FW_DATA = 18, - REG_FPGA_FW_VER = 19, - REG_FLASHRAM_ADDR = 20, - REG_FLASHRAM_DATA = 21, - -} ed64_register_args_t; - - -typedef enum { - STATE_DMA_BUSY = 1, - STATE_DMA_TOUT = 2, - STATE_USB_TXE = 4, - STATE_USB_RXF = 8, - STATE_SPI = 16, - -} ed64_dma_state_t; - - +// #define ED_STATE_DMA_BUSY (1 << 0) +// #define ED_STATE_DMA_TOUT (1 << 1) +// #define ED_STATE_TXE (1 << 2) +// #define ED_STATE_RXF (1 << 3) +// #define ED_STATE_SPI (1 << 4) // typedef enum { -// DCFG_SD_TO_RAM = 1, -// DCFG_RAM_TO_SD = 2, -// DCFG_USB_TO_RAM = 3, -// DCFG_RAM_TO_USB = 4, - -// } ed64_disk_mode_t; - - +// STATE_DMA_BUSY = 0x01, +// STATE_DMA_TOUT = 0x02, +// STATE_USB_TXE = 0x04, +// STATE_USB_RXF = 0x08, +// STATE_SPI = 0x10, + +// } ed64_dma_state_t; + +// #define ED_DMA_SD_TO_RAM 1 +// #define ED_DMA_RAM_TO_SD 2 +// #define ED_DMA_FIFO_TO_RAM 3 +// #define ED_DMA_RAM_TO_FIFO 4 + +// #define ED_SAV_EEP_OFF (0 << 0) +// #define ED_SAV_EEP_ON (1 << 0) +// #define ED_SAV_SRM_OFF (0 << 1) +// #define ED_SAV_SRM_ON (1 << 1) +// #define ED_SAV_EEP_SMALL (0 << 2) +// #define ED_SAV_EEP_BIG (1 << 2) +// #define ED_SAV_SRM_SMALL (0 << 3) +// #define ED_SAV_SRM_BIG (1 << 3) #define SAV_EEP_ON 1 #define SAV_SRM_ON 2 -#define SAV_EEP_SIZE 4 -#define SAV_SRM_SIZE 8 +#define SAV_EEP_BIG 4 +#define SAV_SRM_BIG 8 #define SAV_RAM_BANK 128 #define SAV_RAM_BANK_APPLY 32768 + +// #define ED_CFG_SDRAM_OFF (0 << 0) +// #define ED_CFG_SDRAM_ON (1 << 0) +// #define ED_CFG_BYTESWAP_OFF (0 << 1) +// #define ED_CFG_BYTESWAP_ON (1 << 1) typedef enum { - ED_CFG_SDRAM_ON = 1, - ED_CFG_BYTESWAP_ON = 2, - ED_CFG_WRITE_MODE_ON = 4, - ED_CFG_WRITE_ADDR_MASK = 8, - ED_CFG_RTC_ON = 32, - ED_CFG_GPIO_ON = 96, - ED_CFG_64DD_ON = 256, - ED_CFG_64DD_WRITE_ENABLED = 512, + ED_CFG_SDRAM_ON = 0x01, + ED_CFG_BYTESWAP_ON = 0x02, + ED_CFG_WRITE_MODE_ON = 0x04, + ED_CFG_WRITE_ADDR_MASK = 0x08, + ED_CFG_RTC_ON = 0x20, //32, + ED_CFG_GPIO_ON = 0x60, //96, + // ED_CFG_64DD_ON = 0x0100, //256, + // ED_CFG_64DD_WRITE_ENABLED = 0x0200, //512, } ed64_config_t; -#define FPGA_FW_DATA_SKIP_FW_INIT (1 << 8) -#define FPGA_FW_DATA_SKIP_TV_INIT (1 << 9) -#define FPGA_FW_DATA_TV_TYPE1 (1 << 10) -#define FPGA_FW_DATA_TV_TYPE2 (1 << 11) -#define FPGA_FW_DATA_SKIP_SD_INIT (1 << 12) -#define FPGA_FW_DATA_SD_TYPE (1 << 13) -#define FPGA_FW_DATA_HOT_START (1 << 14) - -uint32_t ed64_ll_reg_read(uint32_t reg); -void ed64_ll_reg_write(uint32_t reg, uint32_t data); -void ed64_ll_dma_pi_read(void * ram_address, unsigned long pi_address, unsigned long length); -void ed64_ll_dma_pi_write(void * ram_address, unsigned long pi_address, unsigned long length); -void ed64_ll_dma_read(void *ram, uint32_t address, uint32_t length); -void ed64_ll_dma_write(void *ram, uint32_t address, uint32_t length); +// #define FPGA_FW_DATA_SKIP_FW_INIT (1 << 8) +// #define FPGA_FW_DATA_SKIP_TV_INIT (1 << 9) +// #define FPGA_FW_DATA_TV_TYPE1 (1 << 10) +// #define FPGA_FW_DATA_TV_TYPE2 (1 << 11) +// #define FPGA_FW_DATA_SKIP_SD_INIT (1 << 12) +// #define FPGA_FW_DATA_SD_TYPE (1 << 13) +// #define FPGA_FW_DATA_HOT_START (1 << 14) -/* DMA functions */ -void ed64_ll_dma_read_rom(void *ram, uint32_t start_address, uint32_t slen); -void ed64_ll_dma_write_rom(void *ram, uint32_t start_address, uint32_t slen); -void ed64_ll_dma_read_sram(void *ram, uint32_t address, uint32_t length); -void ed64_ll_dma_write_sram(void *ram, uint32_t address, uint32_t length); // static uint16_t spi_cfg; -uint8_t ed64_ll_sram_bank = 1; +uint8_t ed64_ll_sram_bank; ed64_save_type_t ed64_ll_save_type; -#define REG_LAT 0x04 -#define REG_PWD 0x04 +// #define REG_LAT 0x04 +// #define REG_PWD 0x04 -#define ROM_LAT 0x40 -#define ROM_PWD 0x12 +// #define ROM_LAT 0x40 +// #define ROM_PWD 0x12 /* register functions (dependent on flashcart version) */ /* register functions for V2 & V2.5 (These carts do not support FLASHRAM)*/ /* The end of SDRAM is used for SRAM or FlashRAM save types */ -void ed64_ll_io_reg_v2(uint32_t address, uint32_t data) { +// void ed64_ll_io_reg_v2(uint32_t address, uint32_t data) { - *(volatile uint32_t *) (ROM_ADDRESS); - *(volatile uint32_t *) (ROM_ADDRESS + address) = data; -} +// *(volatile uint32_t *) (ROM_ADDRESS); +// *(volatile uint32_t *) (ROM_ADDRESS + address) = data; +// } -/* register functions for V3 */ -void ed64_ll_io_reg_v3(uint32_t address, uint16_t data) { +// /* register functions for V3 */ +// void ed64_ll_io_reg_v3(uint32_t address, uint16_t data) { - ed64_ll_reg_write(REG_FLASHRAM_ADDR, address); - ed64_ll_reg_write(REG_FLASHRAM_DATA, data); -} +// io_write(ED_FLASHRAM_ADDR_REG, address); +// io_write(ED_FLASHRAM_MSG_REG, data); +// } /* initialize functions (dependent on flashcart version) */ -/* Initilize V2 & 2.5 cart */ -void ed64_ll_init_v2() { +// /* Initilize V2 & 2.5 cart */ +// void ed64_ll_init_v2() { - uint8_t buff[512]; - uint16_t cfg = ed64_ll_reg_read(REG_CFG); +// uint8_t buff[512]; +// uint16_t cfg = io_read(ED_CFG_REG); - ed64_ll_reg_write(REG_CFG, 0); - ed64_ll_io_reg_v2(0xaa / 4 * 4, 0x00980098); - ed64_ll_dma_read_rom(buff, 0, 1); - ed64_ll_io_reg_v2(0xaa / 4 * 4, 0x00f000f0); - ed64_ll_dma_read_rom(buff, 0, 1); - ed64_ll_reg_write(REG_CFG, cfg); - -} +// io_write(ED_CFG_REG, 0); +// ed64_ll_io_reg_v2(0xaa / 4 * 4, 0x00980098); +// ed64_ll_dma_read_rom(buff, 0, 1); +// ed64_ll_io_reg_v2(0xaa / 4 * 4, 0x00f000f0); +// ed64_ll_dma_read_rom(buff, 0, 1); +// io_write(ED_CFG_REG, cfg); -/* Initilize V3 cart */ -void ed64_ll_init_v3() { - - uint8_t buff[1024]; - uint16_t cfg = ed64_ll_reg_read(REG_CFG); - - ed64_ll_reg_write(REG_CFG, 0); - ed64_ll_reg_write(REG_CFG_COUNT, 161); - ed64_ll_io_reg_v3(0x55, 0x98); - ed64_ll_dma_read_rom(buff, 0, 2); - ed64_ll_io_reg_v3(0x55, 0xF0); - ed64_ll_dma_read_rom(buff, 0, 2); - ed64_ll_dma_read_rom(buff, 1024, 2); - ed64_ll_dma_read_rom(buff, 1024 + 256 - 2, 2); - ed64_ll_reg_write(REG_CFG_COUNT, 1); - - ed64_ll_reg_write(REG_CFG, cfg); -} +// } -/* Initialize cart */ -int ed64_ll_init() { +// /* Initilize V3 cart */ +// void ed64_ll_init_v3() { - uint16_t firmware_ver; - uint16_t firmware_msg; - uint8_t cold_start; +// uint8_t buff[1024]; +// uint16_t cfg = ed64_ll_reg_read(ED_CFG_REG); - // TODO: take into account libCart! - io_write(PI_BSD_DOM2_LAT_REG, REG_LAT); - io_write(PI_BSD_DOM2_PWD_REG, REG_PWD); - dma_wait(); // Make sure the libdragon Async io methods have been performed. +// io_write(ED_CFG_REG, 0); +// io_write(ED_CFG_CNT_REG, 161); +// ed64_ll_io_reg_v3(0x55, 0x98); +// ed64_ll_dma_read_rom(buff, 0, 2); +// ed64_ll_io_reg_v3(0x55, 0xF0); +// ed64_ll_dma_read_rom(buff, 0, 2); +// ed64_ll_dma_read_rom(buff, 1024, 2); +// ed64_ll_dma_read_rom(buff, 1024 + 256 - 2, 2); +// io_write(ED_CFG_CNT_REG, 1); +// io_write(ED_CFG_REG, cfg); +// } - ed64_ll_reg_write(REG_KEY, ED64_KEY_UNLOCK); - ed64_ll_reg_write(REG_CFG, 0x0000); +// /* Initialize cart */ +// int ed64_ll_init() { +// uint16_t firmware_ver; +// uint16_t firmware_msg; +// uint8_t cold_start; - firmware_msg = ed64_ll_reg_read(REG_FPGA_FW_DATA); - cold_start = (firmware_msg & FPGA_FW_DATA_HOT_START) == 0 ? 1 : 0; - if (cold_start) { - firmware_msg |= FPGA_FW_DATA_HOT_START; - ed64_ll_reg_write(REG_FPGA_FW_DATA, firmware_msg); - } +// // TODO: take into account libCart! +// io_write(PI_BSD_DOM2_LAT_REG, REG_LAT); +// io_write(PI_BSD_DOM2_PWD_REG, REG_PWD); +// dma_wait(); // Make sure the libdragon Async io methods have been performed. - firmware_ver = ed64_ll_reg_read(REG_FPGA_FW_VER); - if ((firmware_ver & 0xf000) >= 0x2000) { - ed64_ll_init_v3(); - } else { - ed64_ll_init_v2(); - } +// ed64_ll_reg_write(REG_KEY, ED64_KEY_UNLOCK); +// ed64_ll_reg_write(REG_CFG, 0x0000); - //spi_cfg = SPI_CFG_SS | BI_SPI_SPD_LO; - ed64_ll_reg_write(REG_CFG, ED_CFG_SDRAM_ON); - //ed64_ll_reg_write(REG_SPI_CFG, spi_cfg); - ed64_ll_save_type = SAVE_TYPE_NONE; +// firmware_msg = ed64_ll_reg_read(REG_FPGA_FW_DATA); +// cold_start = (firmware_msg & FPGA_FW_DATA_HOT_START) == 0 ? 1 : 0; +// if (cold_start) { +// firmware_msg |= FPGA_FW_DATA_HOT_START; +// ed64_ll_reg_write(REG_FPGA_FW_DATA, firmware_msg); +// } +// firmware_ver = ed64_ll_reg_read(REG_FPGA_FW_VER); +// if ((firmware_ver & 0xf000) >= 0x2000) { +// ed64_ll_init_v3(); +// } else { +// ed64_ll_init_v2(); +// } - return cold_start; -} -void ed64_ll_reset_spx() { - uint16_t cfg = ed64_ll_reg_read(REG_CFG); +// //spi_cfg = SPI_CFG_SS | BI_SPI_SPD_LO; +// ed64_ll_reg_write(REG_CFG, ED_CFG_SDRAM_ON); +// //ed64_ll_reg_write(REG_SPI_CFG, spi_cfg); +// ed64_ll_save_type = SAVE_TYPE_NONE; - ed64_ll_reg_write(REG_CFG, 0x8000); - wait_ms(100); - ed64_ll_reg_write(REG_CFG, cfg); - wait_ms(100); -} -uint32_t ed64_ll_reg_read(uint32_t reg) { +// return cold_start; +// } - *(volatile uint32_t *) (ED64_REGS_BASE); - return *(volatile uint32_t *) (ED64_REGS_BASE + reg * 4); -} +// void ed64_ll_reset_spx() { -void ed64_ll_reg_write(uint32_t reg, uint32_t data) { +// uint16_t cfg = io_read(ED_CFG_REG); - *(volatile uint32_t *) (ED64_REGS_BASE); - *(volatile uint32_t *) (ED64_REGS_BASE + reg * 4) = data; - *(volatile uint32_t *) (ROM_ADDRESS); +// io_write(ED_CFG_REG, 0x8000); +// wait_ms(100); +// io_write(ED_CFG_REG, cfg); +// wait_ms(100); +// } -} // /* Used for USB and SPI functions */ // uint8_t ed64_ll_dma_busy() { -// while ((ed64_ll_reg_read(REG_STATUS) & STATE_DMA_BUSY) != 0); -// return ed64_ll_reg_read(REG_STATUS) & STATE_DMA_TOUT; +// while ((io_read(ED_STATUS_REG) & STATE_DMA_BUSY) != 0); +// return io_read(ED_STATUS_REG) & STATE_DMA_TOUT; // } @@ -277,13 +351,13 @@ void ed64_ll_reg_write(uint32_t reg, uint32_t data) { // /* USB read is busy */ // uint8_t ed64_ll_usb_read_busy() { -// return ed64_ll_reg_read(REG_STATUS) & STATE_USB_RXF; +// return io_read(ED_STATUS_REG) & STATE_USB_RXF; // } // /* USB write is busy */ // uint8_t ed64_ll_usb_write_busy() { -// return ed64_ll_reg_read(REG_STATUS) & STATE_USB_TXE; +// return io_read(ED_STATUS_REG) & STATE_USB_TXE; // } // /* USB read */ @@ -292,9 +366,9 @@ void ed64_ll_reg_write(uint32_t reg, uint32_t data) { // start_address /= 4; // while (ed64_ll_usb_read_busy() != 0); -// ed64_ll_reg_write(REG_DMA_LENGTH, slen - 1); -// ed64_ll_reg_write(REG_DMA_RAM_ADDR, start_address); -// ed64_ll_reg_write(REG_DMA_CFG, DCFG_USB_TO_RAM); +// io_write(ED_DMA_LEN_REG, slen - 1); +// io_write(ED_DMA_ADDR_REG, start_address); +// io_write(ED_DMA_CFG_REG, ED_DMA_FIFO_TO_RAM); // if (ed64_ll_dma_busy() != 0)return USB_ERROR_FIFO_TIMEOUT; @@ -307,9 +381,9 @@ void ed64_ll_reg_write(uint32_t reg, uint32_t data) { // start_address /= 4; // while (ed64_ll_usb_write_busy() != 0); -// ed64_ll_reg_write(REG_DMA_LENGTH, slen - 1); -// ed64_ll_reg_write(REG_DMA_RAM_ADDR, start_address); -// ed64_ll_reg_write(REG_DMA_CFG, DCFG_RAM_TO_USB); +// io_write(ED_DMA_LEN_REG, slen - 1); +// io_write(ED_DMA_ADDR_REG, start_address); +// io_write(ED_DMA_CFG_REG, ED_DMA_RAM_TO_FIFO); // if (ed64_ll_dma_busy() != 0)return USB_ERROR_FIFO_TIMEOUT; @@ -329,7 +403,7 @@ void ed64_ll_set_save_type(ed64_save_type_t type) { uint8_t eeprom_size_16k = false; uint8_t enable_sram = false; uint8_t ram_size_large = false; - ed64_ll_save_type = type; + ed64_ll_save_type = type; // So we can retrive it later with `ed64_ll_get_save_type` uint8_t ram_bank = ed64_ll_sram_bank; @@ -361,12 +435,14 @@ void ed64_ll_set_save_type(ed64_save_type_t type) { if (enable_eeprom)save_cfg |= SAV_EEP_ON; if (enable_sram)save_cfg |= SAV_SRM_ON; - if (eeprom_size_16k)save_cfg |= SAV_EEP_SIZE; - if (ram_size_large)save_cfg |= SAV_SRM_SIZE; + if (eeprom_size_16k)save_cfg |= SAV_EEP_BIG; + if (ram_size_large)save_cfg |= SAV_SRM_BIG; if (ram_bank)save_cfg |= SAV_RAM_BANK; save_cfg |= SAV_RAM_BANK_APPLY; - ed64_ll_reg_write(REG_SAV_CFG, save_cfg); + __cart_acs_get(); + io_write(ED_SAV_CFG_REG, save_cfg); + __cart_acs_rel(); } @@ -376,271 +452,177 @@ void ed64_ll_set_sram_bank(uint8_t bank) { } -/* reads metadata related to the assembily date and cart capabilities */ -void ed64_ll_read_cart_metadata(void *dest) { +// /* reads metadata related to the manufacturing date and cart capabilities */ +// ed64_cart_metadata_t ed64_ll_read_cart_metadata(void *dest) { - uint16_t cfg = ed64_ll_reg_read(REG_CFG); +// ed64_cart_metadata_t cart_info; +// __cart_acs_get(); + +// uint16_t cfg = io_read(ED_CFG_REG); - cfg &= ~ED_CFG_SDRAM_ON; - ed64_ll_reg_write(REG_CFG, cfg); +// cfg &= ~ED_CFG_SDRAM_ON; +// io_write(ED_CFG_REG, cfg); - ed64_ll_dma_read_rom(dest, 0, 1); +// ed64_ll_dma_read_rom(dest, 0, 1); - // assembily_date = (buff[0x38] << 8) | buff[0x39]; - // assembily_time = (buff[0x3A] << 8) | buff[0x3B]; - // serial_number = (buff[0x3C] << 8) | buff[0x3D]; - // cic_6105_compatible = buff[0x40] == 0x03 ? true : false; // CIC_6105 : CIC_6102; +// // cart_info.production_date = (buff[0x38] << 8) | buff[0x39]; +// // cart_info.production_time = (buff[0x3A] << 8) | buff[0x3B]; +// // cart_info.serial_number = (buff[0x3C] << 8) | buff[0x3D]; +// // cart_info.cic_6105_compatible = buff[0x40] == 0x03 ? true : false; // CIC_6105 : CIC_6102; - cfg |= ED_CFG_SDRAM_ON; - ed64_ll_reg_write(REG_CFG, cfg); -} - -void ed64_ll_dma_read_rom(void *ram, uint32_t start_address, uint32_t slen) { +// cfg |= ED_CFG_SDRAM_ON; +// io_write(ED_CFG_REG, cfg); +// __cart_acs_rel(); +// return cart_info; +// } - ed64_ll_dma_read(ram, ROM_ADDRESS + start_address * 512, slen * 512); +void ed64_ll_dma_read_rom(void *ram, uint32_t address_offset, uint32_t length) { + __cart_acs_get(); + __cart_dma_rd(ram, ROM_ADDRESS + address_offset, length); + __cart_acs_rel(); } -void ed64_ll_dma_write_rom(void *ram, uint32_t start_address, uint32_t slen) { +void ed64_ll_dma_write_rom(void *ram, uint32_t address_offset, uint32_t length) { + __cart_acs_get(); + __cart_dma_wr(ram, ROM_ADDRESS + address_offset, length); + __cart_acs_rel(); - ed64_ll_dma_write(ram, ROM_ADDRESS + start_address * 512, slen * 512); } /* Read from SRAM over DMA */ -void ed64_ll_dma_read_sram(void *ram, uint32_t address, uint32_t length) { - // Note: seemingly the ED64 cannot read SRAM at full speed, - // so we need to slow it down temporariy! - - // Get the current timings - // TODO: is `volatile` actually needed?! - volatile uint32_t piLatReg = io_read(PI_BSD_DOM2_LAT_REG); - volatile uint32_t piPwdReg = io_read(PI_BSD_DOM2_PWD_REG); - volatile uint32_t piPgsReg = io_read(PI_BSD_DOM2_PGS_REG); - volatile uint32_t piRlsReg = io_read(PI_BSD_DOM2_RLS_REG); - dma_wait(); // Make sure the libdragon Async io methods have been performed. - - // Set slow timings - io_write(PI_BSD_DOM2_PGS_REG, 0x0D); - io_write(PI_BSD_DOM2_RLS_REG, 0x02); - io_write(PI_BSD_DOM2_LAT_REG, 0x05); - io_write(PI_BSD_DOM2_PWD_REG, 0x0C); - dma_wait(); // Make sure the libdragon Async io methods have been performed. +void ed64_ll_dma_read_sram(void *ram, uint32_t address_offset, uint32_t length) { + __cart_acs_get(); // Read SRAM - ed64_ll_dma_read(ram, SRAM_ADDRESS + address, length); - - // Restore original timings - io_write(PI_BSD_DOM2_LAT_REG, piLatReg); - io_write(PI_BSD_DOM2_PWD_REG, piPwdReg); - io_write(PI_BSD_DOM2_PGS_REG, piPgsReg); - io_write(PI_BSD_DOM2_RLS_REG, piRlsReg); - dma_wait(); // Make sure the libdragon Async io methods have been performed. + __cart_dma_rd(ram, SRAM_ADDRESS + address_offset, length); + + __cart_acs_rel(); } /* Write to SRAM over DMA */ -void ed64_ll_dma_write_sram(void *ram, uint32_t address, uint32_t length) { - // Note: seemingly the ED64 cannot write SRAM at full speed, - // so we need to slow it down temporariy! - - // Get the current timings - // TODO: is `volatile` actually needed?! - volatile uint32_t piLatReg = io_read(PI_BSD_DOM2_LAT_REG); - volatile uint32_t piPwdReg = io_read(PI_BSD_DOM2_PWD_REG); - volatile uint32_t piPgsReg = io_read(PI_BSD_DOM2_PGS_REG); - volatile uint32_t piRlsReg = io_read(PI_BSD_DOM2_RLS_REG); - dma_wait(); // Make sure the libdragon Async io methods have been performed. - - // Set slow timings - io_write(PI_BSD_DOM2_PGS_REG, 0x0D); - io_write(PI_BSD_DOM2_RLS_REG, 0x02); - io_write(PI_BSD_DOM2_LAT_REG, 0x05); - io_write(PI_BSD_DOM2_PWD_REG, 0x0C); - dma_wait(); // Make sure the libdragon Async io methods have been performed. +void ed64_ll_dma_write_sram(void *ram, uint32_t address_offset, uint32_t length) { + __cart_acs_get(); // Write SRAM - ed64_ll_dma_write(ram, SRAM_ADDRESS + address, length); - - // Restore original timings - io_write(PI_BSD_DOM2_LAT_REG, piLatReg); - io_write(PI_BSD_DOM2_PWD_REG, piPwdReg); - io_write(PI_BSD_DOM2_PGS_REG, piPgsReg); - io_write(PI_BSD_DOM2_RLS_REG, piRlsReg); - dma_wait(); // Make sure the libdragon Async io methods have been performed. -} - -// uint16_t ed64_ll_msg_rd() { - -// return ed64_ll_reg_read(REG_MSG); -// } - -// void ed64_ll_msg_wr(uint16_t val) { - -// ed64_ll_reg_write(REG_MSG, val); -// } - -typedef struct PI_regs_s { - /** @brief Uncached address in RAM where data should be found */ - void * ram_address; - /** @brief Address of data on peripheral */ - unsigned long pi_address; - /** @brief How much data to read from RAM into the peripheral */ - unsigned long read_length; - /** @brief How much data to write to RAM from the peripheral */ - unsigned long write_length; - /** @brief Status of the PI, including DMA busy */ - unsigned long status; -} _PI_regs_s; - -static volatile struct PI_regs_s * const PI_regs = (struct PI_regs_s *) PI_BASE_REG; - -void ed64_ll_dma_pi_read(void * ram_address, unsigned long pi_address, unsigned long length) { - - disable_interrupts(); - dma_wait(); - io_write(PI_STATUS_REG, 3); - PI_regs->ram_address = ram_address; - PI_regs->pi_address = pi_address & 0x1FFFFFFF; - PI_regs->write_length = length - 1; - dma_wait(); - - enable_interrupts(); -} + __cart_dma_wr(ram, SRAM_ADDRESS + address_offset, length); -void ed64_ll_dma_pi_write(void * ram_address, unsigned long pi_address, unsigned long length) { - - disable_interrupts(); - dma_wait(); - io_write(PI_STATUS_REG, 3); - PI_regs->ram_address = ram_address; - PI_regs->pi_address = pi_address & 0x1FFFFFFF; - PI_regs->read_length = length - 1; - dma_wait(); - enable_interrupts(); -} - -void ed64_ll_dma_read(void *ram, uint32_t address, uint32_t length) { - - - if (((uint32_t) ram & 0xF0000000) == 0x80000000) { - data_cache_hit_writeback_invalidate(ram, length); - ed64_ll_dma_pi_read(ram, address, length); - } else { - ed64_ll_dma_pi_read(ram, address, length); - } - -} - -void ed64_ll_dma_write(void *ram, uint32_t address, uint32_t length) { - - if (((uint32_t) ram & 0xF0000000) == 0x80000000)data_cache_hit_writeback(ram, length); - ed64_ll_dma_pi_write(ram, address, length); + __cart_acs_rel(); } /** @brief Get the current FPGA version */ uint16_t ed64_ll_get_fpga_version() { - - return ed64_ll_reg_read(REG_FPGA_VERSION); + __cart_acs_get(); + return io_read(ED_VER_REG); + __cart_acs_rel(); } /** @brief Get the current CPLD version */ uint16_t ed64_ll_get_cpld_version() { - + __cart_acs_get(); uint16_t cpld_version; - uint16_t cfg = ed64_ll_reg_read(REG_CFG); - - ed64_ll_reg_write(REG_CFG, 0); - cpld_version = ed64_ll_reg_read(REG_FPGA_FW_VER); - ed64_ll_reg_write(REG_CFG, cfg); + uint16_t cfg = io_read(ED_CFG_REG); + io_write(ED_CFG_REG, 0); + cpld_version = io_read(ED_CPLD_VER_REG); + io_write(ED_CFG_REG, cfg); + __cart_acs_rel(); return cpld_version; } -/* Load the specified FPGA firmware */ +/** @brief Load the specified FPGA firmware */ void ed64_ll_load_firmware(uint8_t *firmware) { - - uint32_t i; + __cart_acs_get(); + uint32_t i = 0; uint16_t f_ctr = 0; - uint16_t cfg = ed64_ll_reg_read(REG_CFG); + uint16_t cfg = io_read(ED_CFG_REG); cfg &= ~ED_CFG_SDRAM_ON; - ed64_ll_reg_write(REG_CFG, cfg); - - ed64_ll_reg_write(REG_CFG_COUNT, 0); + io_write(ED_CFG_REG, cfg); wait_ms(10); - ed64_ll_reg_write(REG_CFG_COUNT, 1); + io_write(ED_CFG_CNT_REG, 0); + wait_ms(10); + io_write(ED_CFG_CNT_REG, 1); wait_ms(10); - i = 0; for (;;) { - - ed64_ll_reg_write(REG_CFG_DATA, *(uint16_t *) & firmware[i]); - while ((ed64_ll_reg_read(REG_CFG_COUNT) & 8) != 0); + io_write(ED_CFG_DAT_REG, *(uint16_t *) & firmware[i]); + while ((io_read(ED_CFG_CNT_REG) & 8) != 0); f_ctr = firmware[i++] == 0xff ? f_ctr + 1 : 0; - if (f_ctr >= 47)break; + if (f_ctr >= 47) break; f_ctr = firmware[i++] == 0xff ? f_ctr + 1 : 0; - if (f_ctr >= 47)break; + if (f_ctr >= 47) break; } - - while ((ed64_ll_reg_read(REG_CFG_COUNT) & 4) == 0) { - ed64_ll_reg_write(REG_CFG_DATA, 0xffff); - while ((ed64_ll_reg_read(REG_CFG_COUNT) & 8) != 0); + while ((io_read(ED_CFG_CNT_REG) & 4) == 0) { + io_write(ED_CFG_DAT_REG, 0xffff); + while ((io_read(ED_CFG_CNT_REG) & 8) != 0); } - wait_ms(20); + __cart_acs_rel(); } void ed64_ll_lock_regs() { - ed64_ll_reg_write(REG_KEY, ED64_KEY_LOCK); + __cart_acs_get(); + io_write(ED_KEY_REG, ED64_KEY_LOCK); + __cart_acs_rel(); } void ed64_ll_unlock_regs() { - ed64_ll_reg_write(REG_KEY, ED64_KEY_UNLOCK); + __cart_acs_get(); + io_write(ED_KEY_REG, ED64_KEY_UNLOCK); + __cart_acs_rel(); } /* GPIO functions */ -// /* Set GPIO mode RTC */ -// void ed64_ll_gpio_mode_rtc() { - -// uint16_t cfg = ed64_ll_reg_read(REG_CFG); -// cfg &= ~ED_CFG_GPIO_ON; -// cfg |= ED_CFG_RTC_ON; -// ed64_ll_reg_write(REG_CFG, cfg); -// } - -// /* Set GPIO mode ON */ -// void ed64_ll_gpio_mode_io() { - -// uint16_t cfg = ed64_ll_reg_read(REG_CFG); -// cfg |= ED_CFG_GPIO_ON; -// ed64_ll_reg_write(REG_CFG, cfg); -// } - -// /* Set GPIO mode OFF */ -// void ed64_ll_gpio_mode_off() { - -// uint16_t cfg = ed64_ll_reg_read(REG_CFG); -// cfg &= ~ED_CFG_GPIO_ON; -// ed64_ll_reg_write(REG_CFG, cfg); -// } +/** @brief Set GPIO mode RTC */ +void ed64_ll_gpio_mode_rtc() { + __cart_acs_get(); + uint16_t cfg = io_read(ED_CFG_REG); + cfg &= ~ED_CFG_GPIO_ON; + cfg |= ED_CFG_RTC_ON; + io_write(ED_CFG_REG, cfg); + __cart_acs_rel(); +} -// /* GPIO mode write */ -// void ed64_ll_gpio_write(uint8_t data) { +/** @brief Set GPIO mode ON */ +void ed64_ll_gpio_mode_io() { + __cart_acs_get(); + uint16_t cfg = io_read(ED_CFG_REG); + cfg |= ED_CFG_GPIO_ON; + io_write(ED_CFG_REG, cfg); + __cart_acs_rel(); +} -// ed64_ll_reg_write(REG_GPIO, data); -// } +/** @brief Set GPIO mode OFF */ +void ed64_ll_gpio_mode_off() { + __cart_acs_get(); + uint16_t cfg = io_read(ED_CFG_REG); + cfg &= ~ED_CFG_GPIO_ON; + io_write(ED_CFG_REG, cfg); + __cart_acs_rel(); +} -// /* GPIO mode read */ -// uint8_t ed64_ll_gpio_read() { +/** @brief Set GPIO mode write */ +void ed64_ll_gpio_write(uint8_t data) { + __cart_acs_get(); + io_write(ED_GPIO_REG, data); + __cart_acs_rel(); +} -// return ed64_ll_reg_read(REG_GPIO); -// } +/** @brief Set GPIO mode read */ +uint8_t ed64_ll_gpio_read() { + __cart_acs_get(); + uint8_t gpio_state = io_read(ED_GPIO_REG); + __cart_acs_rel(); + return gpio_state; +} @@ -648,42 +630,46 @@ void ed64_ll_unlock_regs() { // /* Set 64DD ON and Enabled?! */ // void ed64_ll_64dd_ram_oe() { - -// uint16_t cfg = ed64_ll_reg_read(REG_CFG); +// __cart_acs_get(); +// uint16_t cfg = io_read(ED_CFG_REG); // cfg &= ~ED_CFG_64DD_WRITE_ENABLED; // cfg |= ED_CFG_64DD_ON; -// ed64_ll_reg_write(REG_CFG, cfg); +// io_write(ED_CFG_REG, cfg); +// __cart_acs_rel(); // } // /* Set 64DD Write Enable?? */ // void ed64_ll_64dd_ram_we() { - -// uint16_t cfg = ed64_ll_reg_read(REG_CFG); +// __cart_acs_get(); +// uint16_t cfg = io_read(ED_CFG_REG); // cfg |= ED_CFG_64DD_ON | ED_CFG_64DD_WRITE_ENABLED; -// ed64_ll_reg_write(REG_CFG, cfg); +// io_write(ED_CFG_REG, cfg); +// __cart_acs_rel(); // } // /* Set 64DD Disabled?? */ // void ed64_ll_64dd_ram_off() { - -// uint16_t cfg = ed64_ll_reg_read(REG_CFG); +// __cart_acs_get(); +// uint16_t cfg = io_read(ED_CFG_REG); // cfg &= ~(ED_CFG_64DD_ON | ED_CFG_64DD_WRITE_ENABLED); -// ed64_ll_reg_write(REG_CFG, cfg); +// io_write(ED_CFG_REG, cfg); +// __cart_acs_rel(); // } // /* 64DD Save RAM Clear */ // void ed64_ll_64dd_ram_clear() { - -// uint16_t cfg = ed64_ll_reg_read(REG_CFG); +// __cart_acs_get(); +// uint16_t cfg = io_read(ED_CFG_REG); // cfg |= ED_CFG_64DD_WRITE_ENABLED; // cfg &= ~ED_CFG_64DD_ON; -// ed64_ll_reg_write(REG_CFG, cfg); +// io_write(ED_CFG_REG, cfg); // wait_ms(100); +// __cart_acs_rel(); // } -// /* 64DD Allowed on this cart?! */ -// uint8_t ed64_ll_get_64dd_ram_supported() { - -// return (ed64_ll_reg_read(REG_STATUS) >> 15) & 1; - -// } +/** @brief Check if 64DD Cart conversions allowed on this cart?! */ +uint8_t ed64_ll_get_64dd_ram_supported() { + __cart_acs_get(); + return (io_read(ED_STATUS_REG) >> 15) & 1; + __cart_acs_rel(); +} diff --git a/src/flashcart/ed64/ed64_ll.h b/src/flashcart/ed64/ed64_ll.h index e5233cc8..0a98a459 100644 --- a/src/flashcart/ed64/ed64_ll.h +++ b/src/flashcart/ed64/ed64_ll.h @@ -30,15 +30,14 @@ typedef enum { } ed64_save_type_t; -// typedef struct { -// uint16_t assembily_date; /* The Date that the ED64 was manufactured */ -// uint16_t assembily_time; /* The Time that the ED64 was manufactured */ -// uint16_t serial_number; /* The ED64 serial number (unique for each ED64) */ -// bool cic_6105_compatible; /* This returns whether the the cart CIC is 6105 compatible -// as many were produced before Ultra CIC existed! -// Carts that are not compatible will be unable to run certain ROMs */ - -// } ed64_cart_metadata_s; +typedef struct { + uint16_t production_date; /* The Date that the ED64 was manufactured */ + uint16_t production_time; /* The Time that the ED64 was manufactured */ + uint16_t serial_number; /* The ED64 serial number (unique for each ED64) */ + bool cic_6105_compatible; /* This returns whether the the cart CIC is 6105 compatible + as many were produced before Ultra CIC existed! + Carts that are not compatible will be unable to run certain ROMs */ +} ed64_cart_metadata_t; /* ED64 save location base address */ #define SRAM_ADDRESS (0xA8000000) @@ -55,16 +54,16 @@ typedef enum { /* Initialization functions */ -int ed64_ll_init(); -void ed64_ll_init_v2(); -void ed64_ll_init_v3(); +// int ed64_ll_init(); +// void ed64_ll_init_v2(); +// void ed64_ll_init_v3(); /* Device information functions */ uint16_t ed64_ll_get_fpga_version(); uint16_t ed64_ll_get_cpld_version(); /* Firmware update functions */ -void ed64_ll_load_firmware(uint8_t *firmware); +// void ed64_ll_load_firmware(uint8_t *firmware); // /* USB functions */ // uint8_t ed64_ll_usb_read_busy(); @@ -72,20 +71,20 @@ void ed64_ll_load_firmware(uint8_t *firmware); // uint8_t ed64_ll_usb_write(uint32_t start_address, uint32_t slen); /* Save functions */ -void ed64_ll_set_ram_bank(uint8_t bank); +void ed64_ll_set_sram_bank(uint8_t bank); ed64_save_type_t ed64_ll_get_save_type(); void ed64_ll_set_save_type(ed64_save_type_t type); -/* reads metadata related to the assembily date and cart capabilities */ -void ed64_ll_read_cart_metadata(void *dest); +// /* reads metadata related to the production date and cart capabilities */ +// ed64_cart_metadata_t ed64_ll_read_cart_metadata(void *dest); -// uint16_t ed64_ll_msg_rd(); -// void ed64_ll_msg_wr(uint16_t val); +void ed64_ll_dma_read_rom(void *ram, uint32_t address_offset, uint32_t length); +void ed64_ll_dma_write_rom(void *ram, uint32_t address_offset, uint32_t length); void ed64_ll_lock_regs(); void ed64_ll_unlock_regs(); -void ed64_ll_reset_spx(); +// void ed64_ll_reset_spx(); /* GPIO functions */ void ed64_ll_gpio_mode_rtc(); @@ -98,7 +97,7 @@ uint8_t ed64_ll_gpio_read(); // void ed64_ll_64dd_ram_we(); // void ed64_ll_64dd_ram_off(); // void ed64_ll_64dd_ram_clear(); -// uint8_t ed64_ll_get_64dd_ram_supported(); +uint8_t ed64_ll_get_64dd_ram_supported(); /** @} */ /* ed64 */ diff --git a/src/flashcart/flashcart.c b/src/flashcart/flashcart.c index 6f0563e6..56f6e828 100644 --- a/src/flashcart/flashcart.c +++ b/src/flashcart/flashcart.c @@ -98,7 +98,8 @@ flashcart_err_t flashcart_init (void) { break; case CART_EDX: // Series X EverDrive-64 - // break; // FIXME: Commented out as required to fall through due to need of F/W 3.06 and UNFLoader. + // break; // FIXME: Commented out as required to fall through due to need of F/W 3.06 and UNFLoader. + // but, this is possibily causing the issues related to saves etc. case CART_ED: // Original EverDrive-64 (V-Series & Clones) flashcart = ed64_get_flashcart(); break; From 4365def1e9551ef611936d1afa8800cad7df4e4f Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Mon, 1 Jan 2024 01:28:33 +0000 Subject: [PATCH 57/64] Uncomment some functions That don't seem to cause issues (currently). --- src/flashcart/ed64/ed64.c | 13 +++++- src/flashcart/ed64/ed64_ll.c | 83 ++++++++++++++++++------------------ src/flashcart/ed64/ed64_ll.h | 9 ++-- 3 files changed, 57 insertions(+), 48 deletions(-) diff --git a/src/flashcart/ed64/ed64.c b/src/flashcart/ed64/ed64.c index cb0b97bb..91476b31 100644 --- a/src/flashcart/ed64/ed64.c +++ b/src/flashcart/ed64/ed64.c @@ -13,10 +13,17 @@ #include "ed64.h" // static ed64_variant_t device_variant_id = ED64_VARIANT_UNKNOWN; -// static ed64_save_type_t current_save_type = SAVE_TYPE_NONE; +static ed64_save_type_t current_save_type = SAVE_TYPE_NONE; static flashcart_err_t ed64_init (void) { + // FIXME: check FW compatible. + + // current_save_type = ed64_ll_get_save_type(); + // if (current_save_type < SAVE_TYPE_NONE || current_save_type > SAVE_TYPE_FLASHRAM) { + // return FLASHCART_ERR_INT; + // } + // TODO: partly already done, see https://github.com/DragonMinded/libdragon/blob/4ec469d26b6dc4e308caf3d5b86c2b340b708bbd/src/libcart/cart.c#L1064 // ed64_ll_unlock_regs(); @@ -171,7 +178,7 @@ static flashcart_err_t ed64_load_save (char *save_path) { return FLASHCART_ERR_LOAD; } - if (eeprom_present()) { + if (current_save_type == SAVE_TYPE_EEPROM_4K || current_save_type == SAVE_TYPE_EEPROM_16K) { if (current_save_type == SAVE_TYPE_EEPROM_16K) { // FIXME: could use save_size instead?! eeprom_write_bytes(eeprom_contents, 0, KiB(2)); } @@ -221,6 +228,8 @@ static flashcart_err_t ed64_set_save_type (flashcart_save_type_t save_type) { ed64_ll_set_save_type(type); + current_save_type = type; + // FIXME: diagnose why this is not seemingly set! // TODO: set pseudo save writeback. diff --git a/src/flashcart/ed64/ed64_ll.c b/src/flashcart/ed64/ed64_ll.c index 9680e130..cba780a2 100644 --- a/src/flashcart/ed64/ed64_ll.c +++ b/src/flashcart/ed64/ed64_ll.c @@ -141,7 +141,9 @@ static void __cart_dma_wr(const void *dram, uint32_t cart, uint32_t size) #define ED_VER_REG (ED_BASE_REG+0x2C) /* Hardware series version + firmware rev */ /* ED64 GPIO register */ #define ED_GPIO_REG (ED_BASE_REG+0x30) + // Unknown regs (if any) + /* ED64 Config Count register */ #define ED_CFG_CNT_REG (ED_BASE_REG+0x40) /* ED64 Config Data register */ @@ -177,8 +179,8 @@ static void __cart_dma_wr(const void *dram, uint32_t cart, uint32_t size) // #define ED_DMA_SD_TO_RAM 1 // #define ED_DMA_RAM_TO_SD 2 -// #define ED_DMA_FIFO_TO_RAM 3 -// #define ED_DMA_RAM_TO_FIFO 4 +// #define ED_DMA_FIFO_TO_RAM 3 // USB +// #define ED_DMA_RAM_TO_FIFO 4 // USB // #define ED_SAV_EEP_OFF (0 << 0) // #define ED_SAV_EEP_ON (1 << 0) @@ -208,8 +210,8 @@ typedef enum { ED_CFG_WRITE_ADDR_MASK = 0x08, ED_CFG_RTC_ON = 0x20, //32, ED_CFG_GPIO_ON = 0x60, //96, - // ED_CFG_64DD_ON = 0x0100, //256, - // ED_CFG_64DD_WRITE_ENABLED = 0x0200, //512, + ED_CFG_64DD_ON = 0x0100, //256, + ED_CFG_64DD_WRITE_ENABLED = 0x0200, //512, } ed64_config_t; @@ -443,7 +445,6 @@ void ed64_ll_set_save_type(ed64_save_type_t type) { __cart_acs_get(); io_write(ED_SAV_CFG_REG, save_cfg); __cart_acs_rel(); - } void ed64_ll_set_sram_bank(uint8_t bank) { @@ -626,46 +627,46 @@ uint8_t ed64_ll_gpio_read() { -// /* 64DD cart conversion save functions */ +/* 64DD cart conversion save functions */ -// /* Set 64DD ON and Enabled?! */ -// void ed64_ll_64dd_ram_oe() { -// __cart_acs_get(); -// uint16_t cfg = io_read(ED_CFG_REG); -// cfg &= ~ED_CFG_64DD_WRITE_ENABLED; -// cfg |= ED_CFG_64DD_ON; -// io_write(ED_CFG_REG, cfg); -// __cart_acs_rel(); -// } +/* Set 64DD ON and Enabled?! */ +void ed64_ll_64dd_ram_oe() { + __cart_acs_get(); + uint16_t cfg = io_read(ED_CFG_REG); + cfg &= ~ED_CFG_64DD_WRITE_ENABLED; + cfg |= ED_CFG_64DD_ON; + io_write(ED_CFG_REG, cfg); + __cart_acs_rel(); +} -// /* Set 64DD Write Enable?? */ -// void ed64_ll_64dd_ram_we() { -// __cart_acs_get(); -// uint16_t cfg = io_read(ED_CFG_REG); -// cfg |= ED_CFG_64DD_ON | ED_CFG_64DD_WRITE_ENABLED; -// io_write(ED_CFG_REG, cfg); -// __cart_acs_rel(); -// } +/* Set 64DD Write Enable?? */ +void ed64_ll_64dd_ram_we() { + __cart_acs_get(); + uint16_t cfg = io_read(ED_CFG_REG); + cfg |= ED_CFG_64DD_ON | ED_CFG_64DD_WRITE_ENABLED; + io_write(ED_CFG_REG, cfg); + __cart_acs_rel(); +} -// /* Set 64DD Disabled?? */ -// void ed64_ll_64dd_ram_off() { -// __cart_acs_get(); -// uint16_t cfg = io_read(ED_CFG_REG); -// cfg &= ~(ED_CFG_64DD_ON | ED_CFG_64DD_WRITE_ENABLED); -// io_write(ED_CFG_REG, cfg); -// __cart_acs_rel(); -// } +/* Set 64DD Disabled?? */ +void ed64_ll_64dd_ram_off() { + __cart_acs_get(); + uint16_t cfg = io_read(ED_CFG_REG); + cfg &= ~(ED_CFG_64DD_ON | ED_CFG_64DD_WRITE_ENABLED); + io_write(ED_CFG_REG, cfg); + __cart_acs_rel(); +} -// /* 64DD Save RAM Clear */ -// void ed64_ll_64dd_ram_clear() { -// __cart_acs_get(); -// uint16_t cfg = io_read(ED_CFG_REG); -// cfg |= ED_CFG_64DD_WRITE_ENABLED; -// cfg &= ~ED_CFG_64DD_ON; -// io_write(ED_CFG_REG, cfg); -// wait_ms(100); -// __cart_acs_rel(); -// } +/* 64DD Save RAM Clear */ +void ed64_ll_64dd_ram_clear() { + __cart_acs_get(); + uint16_t cfg = io_read(ED_CFG_REG); + cfg |= ED_CFG_64DD_WRITE_ENABLED; + cfg &= ~ED_CFG_64DD_ON; + io_write(ED_CFG_REG, cfg); + wait_ms(100); + __cart_acs_rel(); +} /** @brief Check if 64DD Cart conversions allowed on this cart?! */ uint8_t ed64_ll_get_64dd_ram_supported() { diff --git a/src/flashcart/ed64/ed64_ll.h b/src/flashcart/ed64/ed64_ll.h index 0a98a459..6cd701ae 100644 --- a/src/flashcart/ed64/ed64_ll.h +++ b/src/flashcart/ed64/ed64_ll.h @@ -7,7 +7,6 @@ #ifndef FLASHCART_ED64_LL_H__ #define FLASHCART_ED64_LL_H__ - #include #include #include @@ -93,10 +92,10 @@ void ed64_ll_gpio_mode_off(); uint8_t ed64_ll_gpio_read(); // /* 64DD cart conversion save functions */ -// void ed64_ll_64dd_ram_oe(); -// void ed64_ll_64dd_ram_we(); -// void ed64_ll_64dd_ram_off(); -// void ed64_ll_64dd_ram_clear(); +void ed64_ll_64dd_ram_oe(); +void ed64_ll_64dd_ram_we(); +void ed64_ll_64dd_ram_off(); +void ed64_ll_64dd_ram_clear(); uint8_t ed64_ll_get_64dd_ram_supported(); /** @} */ /* ed64 */ From f6bdd90d59ecb981920ff9865edd4a96aae3a1f4 Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Mon, 1 Jan 2024 01:49:46 +0000 Subject: [PATCH 58/64] Uncomment USB --- src/flashcart/ed64/ed64_ll.c | 91 ++++++++++++++++++------------------ src/flashcart/ed64/ed64_ll.h | 4 +- 2 files changed, 47 insertions(+), 48 deletions(-) diff --git a/src/flashcart/ed64/ed64_ll.c b/src/flashcart/ed64/ed64_ll.c index cba780a2..caa1cb34 100644 --- a/src/flashcart/ed64/ed64_ll.c +++ b/src/flashcart/ed64/ed64_ll.c @@ -168,19 +168,19 @@ static void __cart_dma_wr(const void *dram, uint32_t cart, uint32_t size) // #define ED_STATE_TXE (1 << 2) // #define ED_STATE_RXF (1 << 3) // #define ED_STATE_SPI (1 << 4) -// typedef enum { -// STATE_DMA_BUSY = 0x01, -// STATE_DMA_TOUT = 0x02, -// STATE_USB_TXE = 0x04, -// STATE_USB_RXF = 0x08, -// STATE_SPI = 0x10, +typedef enum { + STATE_DMA_BUSY = 0x01, + STATE_DMA_TOUT = 0x02, + STATE_USB_TXE = 0x04, + STATE_USB_RXF = 0x08, + STATE_SPI = 0x10, -// } ed64_dma_state_t; +} ed64_dma_state_t; -// #define ED_DMA_SD_TO_RAM 1 -// #define ED_DMA_RAM_TO_SD 2 -// #define ED_DMA_FIFO_TO_RAM 3 // USB -// #define ED_DMA_RAM_TO_FIFO 4 // USB +#define ED_DMA_SD_TO_RAM 1 +#define ED_DMA_RAM_TO_SD 2 +#define ED_DMA_FIFO_TO_RAM 3 // USB +#define ED_DMA_RAM_TO_FIFO 4 // USB // #define ED_SAV_EEP_OFF (0 << 0) // #define ED_SAV_EEP_ON (1 << 0) @@ -340,57 +340,57 @@ ed64_save_type_t ed64_ll_save_type; // } -// /* Used for USB and SPI functions */ -// uint8_t ed64_ll_dma_busy() { +/* Used for USB and SPI functions */ +uint8_t ed64_ll_dma_busy() { -// while ((io_read(ED_STATUS_REG) & STATE_DMA_BUSY) != 0); -// return io_read(ED_STATUS_REG) & STATE_DMA_TOUT; -// } + while ((io_read(ED_STATUS_REG) & STATE_DMA_BUSY) != 0); + return io_read(ED_STATUS_REG) & STATE_DMA_TOUT; +} -// /* USB functions */ +/* USB functions */ -// /* USB read is busy */ -// uint8_t ed64_ll_usb_read_busy() { +/* USB read is busy */ +uint8_t ed64_ll_usb_read_busy() { -// return io_read(ED_STATUS_REG) & STATE_USB_RXF; -// } + return io_read(ED_STATUS_REG) & STATE_USB_RXF; +} -// /* USB write is busy */ -// uint8_t ed64_ll_usb_write_busy() { +/* USB write is busy */ +uint8_t ed64_ll_usb_write_busy() { -// return io_read(ED_STATUS_REG) & STATE_USB_TXE; -// } + return io_read(ED_STATUS_REG) & STATE_USB_TXE; +} -// /* USB read */ -// uint8_t ed64_ll_usb_read(uint32_t start_address, uint32_t slen) { +/* USB read */ +uint8_t ed64_ll_usb_read(uint32_t start_address, uint32_t slen) { -// start_address /= 4; -// while (ed64_ll_usb_read_busy() != 0); + start_address /= 4; + while (ed64_ll_usb_read_busy() != 0); -// io_write(ED_DMA_LEN_REG, slen - 1); -// io_write(ED_DMA_ADDR_REG, start_address); -// io_write(ED_DMA_CFG_REG, ED_DMA_FIFO_TO_RAM); + io_write(ED_DMA_LEN_REG, slen - 1); + io_write(ED_DMA_ADDR_REG, start_address); + io_write(ED_DMA_CFG_REG, ED_DMA_FIFO_TO_RAM); -// if (ed64_ll_dma_busy() != 0)return USB_ERROR_FIFO_TIMEOUT; + if (ed64_ll_dma_busy() != 0)return ED_USB_ERR_FIFO_TIMEOUT; -// return 0; -// } + return 0; +} -// /* USB write */ -// uint8_t ed64_ll_usb_write(uint32_t start_address, uint32_t slen) { +/* USB write */ +uint8_t ed64_ll_usb_write(uint32_t start_address, uint32_t slen) { -// start_address /= 4; -// while (ed64_ll_usb_write_busy() != 0); + start_address /= 4; + while (ed64_ll_usb_write_busy() != 0); -// io_write(ED_DMA_LEN_REG, slen - 1); -// io_write(ED_DMA_ADDR_REG, start_address); -// io_write(ED_DMA_CFG_REG, ED_DMA_RAM_TO_FIFO); + io_write(ED_DMA_LEN_REG, slen - 1); + io_write(ED_DMA_ADDR_REG, start_address); + io_write(ED_DMA_CFG_REG, ED_DMA_RAM_TO_FIFO); -// if (ed64_ll_dma_busy() != 0)return USB_ERROR_FIFO_TIMEOUT; + if (ed64_ll_dma_busy() != 0)return ED_USB_ERR_FIFO_TIMEOUT; -// return 0; -// } + return 0; +} ed64_save_type_t ed64_ll_get_save_type() { @@ -626,7 +626,6 @@ uint8_t ed64_ll_gpio_read() { } - /* 64DD cart conversion save functions */ /* Set 64DD ON and Enabled?! */ diff --git a/src/flashcart/ed64/ed64_ll.h b/src/flashcart/ed64/ed64_ll.h index 6cd701ae..7dc490bc 100644 --- a/src/flashcart/ed64/ed64_ll.h +++ b/src/flashcart/ed64/ed64_ll.h @@ -43,8 +43,8 @@ typedef struct { /* ED64 ROM location base address */ #define ROM_ADDRESS (0xB0000000) -// #define USB_ERROR_FIFO_TIMEOUT 0x90 -// #define EVD_ERROR_MMC_TIMEOUT 0x91 +#define ED_USB_ERR_FIFO_TIMEOUT 0x90 // FIXME: We can return a better error code?! +// #define ED_ERROR_MMC_TIMEOUT 0x91 // #define BOOT_UPD_ERR_WRONG_SIZE 0x95 // #define BOOT_UPD_ERR_HDR 0x96 From 84c4aef6658958748224e490c6ca8016dcf1fbc9 Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Mon, 1 Jan 2024 01:55:52 +0000 Subject: [PATCH 59/64] Add USB feature --- src/flashcart/64drive/64drive.c | 1 + src/flashcart/ed64/ed64.c | 1 + src/flashcart/flashcart.h | 1 + src/flashcart/sc64/sc64.c | 1 + 4 files changed, 4 insertions(+) diff --git a/src/flashcart/64drive/64drive.c b/src/flashcart/64drive/64drive.c index 8fe51378..bd3178e2 100644 --- a/src/flashcart/64drive/64drive.c +++ b/src/flashcart/64drive/64drive.c @@ -74,6 +74,7 @@ static bool d64_has_feature (flashcart_features_t feature) { switch (feature) { case FLASHCART_FEATURE_64DD: return false; case FLASHCART_FEATURE_RTC: return true; + case FLASHCART_FEATURE_USB: return true; default: return false; } } diff --git a/src/flashcart/ed64/ed64.c b/src/flashcart/ed64/ed64.c index 91476b31..d8efd34b 100644 --- a/src/flashcart/ed64/ed64.c +++ b/src/flashcart/ed64/ed64.c @@ -55,6 +55,7 @@ static bool ed64_has_feature (flashcart_features_t feature) { switch (feature) { case FLASHCART_FEATURE_64DD: return false; case FLASHCART_FEATURE_RTC: return false; // FIXME: if it is a V3 we should return true! + case FLASHCART_FEATURE_USB: return false; // FIXME: if it is a V3 we should return true (although virtual)! default: return false; } } diff --git a/src/flashcart/flashcart.h b/src/flashcart/flashcart.h index 452c36cc..70c3bad2 100644 --- a/src/flashcart/flashcart.h +++ b/src/flashcart/flashcart.h @@ -28,6 +28,7 @@ typedef enum { typedef enum { FLASHCART_FEATURE_64DD, FLASHCART_FEATURE_RTC, + FLASHCART_FEATURE_USB, } flashcart_features_t; /** @brief Flashcart save type enumeration */ diff --git a/src/flashcart/sc64/sc64.c b/src/flashcart/sc64/sc64.c index 85bf2d96..dedc1d54 100644 --- a/src/flashcart/sc64/sc64.c +++ b/src/flashcart/sc64/sc64.c @@ -261,6 +261,7 @@ static bool sc64_has_feature (flashcart_features_t feature) { switch (feature) { case FLASHCART_FEATURE_64DD: return true; case FLASHCART_FEATURE_RTC: return true; + case FLASHCART_FEATURE_USB: return true; default: return false; } } From 41675335be75d05348641d7f09dc51b260e5680e Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Mon, 1 Jan 2024 02:47:45 +0000 Subject: [PATCH 60/64] Add some more comments --- src/flashcart/ed64/ed64_ll.c | 50 +++++++++++++++++++----------------- 1 file changed, 27 insertions(+), 23 deletions(-) diff --git a/src/flashcart/ed64/ed64_ll.c b/src/flashcart/ed64/ed64_ll.c index caa1cb34..08cf7046 100644 --- a/src/flashcart/ed64/ed64_ll.c +++ b/src/flashcart/ed64/ed64_ll.c @@ -177,8 +177,8 @@ typedef enum { } ed64_dma_state_t; -#define ED_DMA_SD_TO_RAM 1 -#define ED_DMA_RAM_TO_SD 2 +#define ED_DMA_SD_TO_RAM 1 // SD Card +#define ED_DMA_RAM_TO_SD 2 // SD Card #define ED_DMA_FIFO_TO_RAM 3 // USB #define ED_DMA_RAM_TO_FIFO 4 // USB @@ -190,9 +190,13 @@ typedef enum { // #define ED_SAV_EEP_BIG (1 << 2) // #define ED_SAV_SRM_SMALL (0 << 3) // #define ED_SAV_SRM_BIG (1 << 3) +/* Enables the EEP save type */ #define SAV_EEP_ON 1 +/* Enables the SRAM save type */ #define SAV_SRM_ON 2 +/* Sets the EEP save type to 16K */ #define SAV_EEP_BIG 4 +/* Sets the SRAM save type to 128K */ #define SAV_SRM_BIG 8 #define SAV_RAM_BANK 128 @@ -204,24 +208,24 @@ typedef enum { // #define ED_CFG_BYTESWAP_OFF (0 << 1) // #define ED_CFG_BYTESWAP_ON (1 << 1) typedef enum { - ED_CFG_SDRAM_ON = 0x01, - ED_CFG_BYTESWAP_ON = 0x02, - ED_CFG_WRITE_MODE_ON = 0x04, - ED_CFG_WRITE_ADDR_MASK = 0x08, - ED_CFG_RTC_ON = 0x20, //32, - ED_CFG_GPIO_ON = 0x60, //96, - ED_CFG_64DD_ON = 0x0100, //256, + ED_CFG_SDRAM_ON = 0x0001, + ED_CFG_BYTESWAP_ON = 0x0002, + ED_CFG_WRITE_MODE_ON = 0x0004, + ED_CFG_WRITE_ADDR_MASK = 0x0008, + ED_CFG_RTC_ON = 0x0020, //32, + ED_CFG_GPIO_ON = 0x0060, //96, + ED_CFG_64DD_ON = 0x0100, //256, ED_CFG_64DD_WRITE_ENABLED = 0x0200, //512, } ed64_config_t; -// #define FPGA_FW_DATA_SKIP_FW_INIT (1 << 8) -// #define FPGA_FW_DATA_SKIP_TV_INIT (1 << 9) -// #define FPGA_FW_DATA_TV_TYPE1 (1 << 10) -// #define FPGA_FW_DATA_TV_TYPE2 (1 << 11) -// #define FPGA_FW_DATA_SKIP_SD_INIT (1 << 12) -// #define FPGA_FW_DATA_SD_TYPE (1 << 13) -// #define FPGA_FW_DATA_HOT_START (1 << 14) +#define FPGA_FW_DATA_SKIP_FW_INIT (1 << 8) +#define FPGA_FW_DATA_SKIP_TV_INIT (1 << 9) +#define FPGA_FW_DATA_TV_TYPE1 (1 << 10) +#define FPGA_FW_DATA_TV_TYPE2 (1 << 11) +#define FPGA_FW_DATA_SKIP_SD_INIT (1 << 12) +#define FPGA_FW_DATA_SD_TYPE (1 << 13) +#define FPGA_FW_DATA_HOT_START (1 << 14) // static uint16_t spi_cfg; @@ -329,15 +333,15 @@ ed64_save_type_t ed64_ll_save_type; // return cold_start; // } -// void ed64_ll_reset_spx() { +void ed64_ll_reset_spx() { -// uint16_t cfg = io_read(ED_CFG_REG); + uint16_t cfg = io_read(ED_CFG_REG); -// io_write(ED_CFG_REG, 0x8000); -// wait_ms(100); -// io_write(ED_CFG_REG, cfg); -// wait_ms(100); -// } + io_write(ED_CFG_REG, 0x8000); + wait_ms(100); + io_write(ED_CFG_REG, cfg); + wait_ms(100); +} /* Used for USB and SPI functions */ From 99c3d3998198c25c5f95e99f18c382dbcd3d3bfa Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Wed, 10 Jan 2024 16:01:33 +0000 Subject: [PATCH 61/64] Comment out USB feature for the moment --- src/flashcart/64drive/64drive.c | 2 +- src/flashcart/ed64/ed64.c | 2 +- src/flashcart/ed64/ed64_ll.c | 90 ++++++++++++++++----------------- src/flashcart/flashcart.h | 2 +- src/flashcart/sc64/sc64.c | 2 +- 5 files changed, 49 insertions(+), 49 deletions(-) diff --git a/src/flashcart/64drive/64drive.c b/src/flashcart/64drive/64drive.c index bd3178e2..a39b2c94 100644 --- a/src/flashcart/64drive/64drive.c +++ b/src/flashcart/64drive/64drive.c @@ -74,7 +74,7 @@ static bool d64_has_feature (flashcart_features_t feature) { switch (feature) { case FLASHCART_FEATURE_64DD: return false; case FLASHCART_FEATURE_RTC: return true; - case FLASHCART_FEATURE_USB: return true; + //case FLASHCART_FEATURE_USB: return true; default: return false; } } diff --git a/src/flashcart/ed64/ed64.c b/src/flashcart/ed64/ed64.c index d8efd34b..99a092ff 100644 --- a/src/flashcart/ed64/ed64.c +++ b/src/flashcart/ed64/ed64.c @@ -55,7 +55,7 @@ static bool ed64_has_feature (flashcart_features_t feature) { switch (feature) { case FLASHCART_FEATURE_64DD: return false; case FLASHCART_FEATURE_RTC: return false; // FIXME: if it is a V3 we should return true! - case FLASHCART_FEATURE_USB: return false; // FIXME: if it is a V3 we should return true (although virtual)! + //case FLASHCART_FEATURE_USB: return false; // FIXME: if it is a V3 we should return true (although virtual)! default: return false; } } diff --git a/src/flashcart/ed64/ed64_ll.c b/src/flashcart/ed64/ed64_ll.c index 08cf7046..d2141c28 100644 --- a/src/flashcart/ed64/ed64_ll.c +++ b/src/flashcart/ed64/ed64_ll.c @@ -333,15 +333,15 @@ ed64_save_type_t ed64_ll_save_type; // return cold_start; // } -void ed64_ll_reset_spx() { +// void ed64_ll_reset_spx() { - uint16_t cfg = io_read(ED_CFG_REG); +// uint16_t cfg = io_read(ED_CFG_REG); - io_write(ED_CFG_REG, 0x8000); - wait_ms(100); - io_write(ED_CFG_REG, cfg); - wait_ms(100); -} +// io_write(ED_CFG_REG, 0x8000); +// wait_ms(100); +// io_write(ED_CFG_REG, cfg); +// wait_ms(100); +// } /* Used for USB and SPI functions */ @@ -446,9 +446,9 @@ void ed64_ll_set_save_type(ed64_save_type_t type) { if (ram_bank)save_cfg |= SAV_RAM_BANK; save_cfg |= SAV_RAM_BANK_APPLY; - __cart_acs_get(); + //__cart_acs_get(); io_write(ED_SAV_CFG_REG, save_cfg); - __cart_acs_rel(); + //__cart_acs_rel(); } void ed64_ll_set_sram_bank(uint8_t bank) { @@ -483,62 +483,62 @@ void ed64_ll_set_sram_bank(uint8_t bank) { // } void ed64_ll_dma_read_rom(void *ram, uint32_t address_offset, uint32_t length) { - __cart_acs_get(); + //__cart_acs_get(); __cart_dma_rd(ram, ROM_ADDRESS + address_offset, length); - __cart_acs_rel(); + //__cart_acs_rel(); } void ed64_ll_dma_write_rom(void *ram, uint32_t address_offset, uint32_t length) { - __cart_acs_get(); + //__cart_acs_get(); __cart_dma_wr(ram, ROM_ADDRESS + address_offset, length); - __cart_acs_rel(); + //__cart_acs_rel(); } /* Read from SRAM over DMA */ void ed64_ll_dma_read_sram(void *ram, uint32_t address_offset, uint32_t length) { - __cart_acs_get(); + //__cart_acs_get(); // Read SRAM __cart_dma_rd(ram, SRAM_ADDRESS + address_offset, length); - __cart_acs_rel(); + //__cart_acs_rel(); } /* Write to SRAM over DMA */ void ed64_ll_dma_write_sram(void *ram, uint32_t address_offset, uint32_t length) { - __cart_acs_get(); + //__cart_acs_get(); // Write SRAM __cart_dma_wr(ram, SRAM_ADDRESS + address_offset, length); - __cart_acs_rel(); + //__cart_acs_rel(); } /** @brief Get the current FPGA version */ uint16_t ed64_ll_get_fpga_version() { - __cart_acs_get(); + //__cart_acs_get(); return io_read(ED_VER_REG); - __cart_acs_rel(); + //__cart_acs_rel(); } /** @brief Get the current CPLD version */ uint16_t ed64_ll_get_cpld_version() { - __cart_acs_get(); + //__cart_acs_get(); uint16_t cpld_version; uint16_t cfg = io_read(ED_CFG_REG); io_write(ED_CFG_REG, 0); cpld_version = io_read(ED_CPLD_VER_REG); io_write(ED_CFG_REG, cfg); - __cart_acs_rel(); + //__cart_acs_rel(); return cpld_version; } /** @brief Load the specified FPGA firmware */ void ed64_ll_load_firmware(uint8_t *firmware) { - __cart_acs_get(); + //__cart_acs_get(); uint32_t i = 0; uint16_t f_ctr = 0; uint16_t cfg = io_read(ED_CFG_REG); @@ -567,20 +567,20 @@ void ed64_ll_load_firmware(uint8_t *firmware) { } wait_ms(20); - __cart_acs_rel(); + //__cart_acs_rel(); } void ed64_ll_lock_regs() { - __cart_acs_get(); + //__cart_acs_get(); io_write(ED_KEY_REG, ED64_KEY_LOCK); - __cart_acs_rel(); + //__cart_acs_rel(); } void ed64_ll_unlock_regs() { - __cart_acs_get(); + //__cart_acs_get(); io_write(ED_KEY_REG, ED64_KEY_UNLOCK); - __cart_acs_rel(); + //__cart_acs_rel(); } @@ -588,37 +588,37 @@ void ed64_ll_unlock_regs() { /** @brief Set GPIO mode RTC */ void ed64_ll_gpio_mode_rtc() { - __cart_acs_get(); + //__cart_acs_get(); uint16_t cfg = io_read(ED_CFG_REG); cfg &= ~ED_CFG_GPIO_ON; cfg |= ED_CFG_RTC_ON; io_write(ED_CFG_REG, cfg); - __cart_acs_rel(); + //__cart_acs_rel(); } /** @brief Set GPIO mode ON */ void ed64_ll_gpio_mode_io() { - __cart_acs_get(); + //__cart_acs_get(); uint16_t cfg = io_read(ED_CFG_REG); cfg |= ED_CFG_GPIO_ON; io_write(ED_CFG_REG, cfg); - __cart_acs_rel(); + //__cart_acs_rel(); } /** @brief Set GPIO mode OFF */ void ed64_ll_gpio_mode_off() { - __cart_acs_get(); + //__cart_acs_get(); uint16_t cfg = io_read(ED_CFG_REG); cfg &= ~ED_CFG_GPIO_ON; io_write(ED_CFG_REG, cfg); - __cart_acs_rel(); + //__cart_acs_rel(); } /** @brief Set GPIO mode write */ void ed64_ll_gpio_write(uint8_t data) { - __cart_acs_get(); + //__cart_acs_get(); io_write(ED_GPIO_REG, data); - __cart_acs_rel(); + //__cart_acs_rel(); } /** @brief Set GPIO mode read */ @@ -634,46 +634,46 @@ uint8_t ed64_ll_gpio_read() { /* Set 64DD ON and Enabled?! */ void ed64_ll_64dd_ram_oe() { - __cart_acs_get(); + //__cart_acs_get(); uint16_t cfg = io_read(ED_CFG_REG); cfg &= ~ED_CFG_64DD_WRITE_ENABLED; cfg |= ED_CFG_64DD_ON; io_write(ED_CFG_REG, cfg); - __cart_acs_rel(); + //__cart_acs_rel(); } /* Set 64DD Write Enable?? */ void ed64_ll_64dd_ram_we() { - __cart_acs_get(); + //__cart_acs_get(); uint16_t cfg = io_read(ED_CFG_REG); cfg |= ED_CFG_64DD_ON | ED_CFG_64DD_WRITE_ENABLED; io_write(ED_CFG_REG, cfg); - __cart_acs_rel(); + //__cart_acs_rel(); } /* Set 64DD Disabled?? */ void ed64_ll_64dd_ram_off() { - __cart_acs_get(); + //__cart_acs_get(); uint16_t cfg = io_read(ED_CFG_REG); cfg &= ~(ED_CFG_64DD_ON | ED_CFG_64DD_WRITE_ENABLED); io_write(ED_CFG_REG, cfg); - __cart_acs_rel(); + //__cart_acs_rel(); } /* 64DD Save RAM Clear */ void ed64_ll_64dd_ram_clear() { - __cart_acs_get(); + //__cart_acs_get(); uint16_t cfg = io_read(ED_CFG_REG); cfg |= ED_CFG_64DD_WRITE_ENABLED; cfg &= ~ED_CFG_64DD_ON; io_write(ED_CFG_REG, cfg); wait_ms(100); - __cart_acs_rel(); + //__cart_acs_rel(); } /** @brief Check if 64DD Cart conversions allowed on this cart?! */ uint8_t ed64_ll_get_64dd_ram_supported() { - __cart_acs_get(); + //__cart_acs_get(); return (io_read(ED_STATUS_REG) >> 15) & 1; - __cart_acs_rel(); + //__cart_acs_rel(); } diff --git a/src/flashcart/flashcart.h b/src/flashcart/flashcart.h index 70c3bad2..15251028 100644 --- a/src/flashcart/flashcart.h +++ b/src/flashcart/flashcart.h @@ -28,7 +28,7 @@ typedef enum { typedef enum { FLASHCART_FEATURE_64DD, FLASHCART_FEATURE_RTC, - FLASHCART_FEATURE_USB, + //FLASHCART_FEATURE_USB, } flashcart_features_t; /** @brief Flashcart save type enumeration */ diff --git a/src/flashcart/sc64/sc64.c b/src/flashcart/sc64/sc64.c index dedc1d54..6e388493 100644 --- a/src/flashcart/sc64/sc64.c +++ b/src/flashcart/sc64/sc64.c @@ -261,7 +261,7 @@ static bool sc64_has_feature (flashcart_features_t feature) { switch (feature) { case FLASHCART_FEATURE_64DD: return true; case FLASHCART_FEATURE_RTC: return true; - case FLASHCART_FEATURE_USB: return true; + //case FLASHCART_FEATURE_USB: return true; default: return false; } } From ccf643b686154a7b349349148b74252f227774a1 Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Thu, 11 Jan 2024 00:47:32 +0000 Subject: [PATCH 62/64] keep name order --- Makefile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/Makefile b/Makefile index c6f65f7a..8db3031e 100644 --- a/Makefile +++ b/Makefile @@ -23,10 +23,10 @@ SRCS = \ flashcart/flashcart.c \ flashcart/64drive/64drive_ll.c \ flashcart/64drive/64drive.c \ - flashcart/sc64/sc64_ll.c \ - flashcart/sc64/sc64.c \ flashcart/ed64/ed64_ll.c \ flashcart/ed64/ed64.c \ + flashcart/sc64/sc64_ll.c \ + flashcart/sc64/sc64.c \ libs/libspng/spng/spng.c \ libs/mini.c/src/mini.c \ libs/miniz/miniz_tdef.c \ @@ -56,6 +56,7 @@ SRCS = \ menu/views/error.c \ menu/views/fault.c \ menu/views/file_info.c \ + menu/views/flashcart_info.c \ menu/views/image_viewer.c \ menu/views/load_disk.c \ menu/views/load_emulator.c \ @@ -65,7 +66,6 @@ SRCS = \ menu/views/system_info.c \ menu/views/settings_editor.c \ menu/views/rtc.c \ - menu/views/flashcart_info.c \ utils/fs.c FONTS = \ From 0635d44034021ec0b4ecc2666945d5a00d0a739a Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Wed, 17 Jan 2024 19:49:41 +0000 Subject: [PATCH 63/64] Update ed64.c Add USB feature --- src/flashcart/ed64/ed64.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/flashcart/ed64/ed64.c b/src/flashcart/ed64/ed64.c index 99a092ff..d8efd34b 100644 --- a/src/flashcart/ed64/ed64.c +++ b/src/flashcart/ed64/ed64.c @@ -55,7 +55,7 @@ static bool ed64_has_feature (flashcart_features_t feature) { switch (feature) { case FLASHCART_FEATURE_64DD: return false; case FLASHCART_FEATURE_RTC: return false; // FIXME: if it is a V3 we should return true! - //case FLASHCART_FEATURE_USB: return false; // FIXME: if it is a V3 we should return true (although virtual)! + case FLASHCART_FEATURE_USB: return false; // FIXME: if it is a V3 we should return true (although virtual)! default: return false; } } From c2aab0ea527de337fd344bbd12cd1bd14a527d1e Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Wed, 17 Jan 2024 19:50:46 +0000 Subject: [PATCH 64/64] Update views.h --- src/menu/views/views.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/menu/views/views.h b/src/menu/views/views.h index 7fef54a9..8da900dc 100644 --- a/src/menu/views/views.h +++ b/src/menu/views/views.h @@ -50,6 +50,12 @@ void view_rtc_display (menu_t *menu, surface_t *display); void view_flashcart_info_init (menu_t *menu); void view_flashcart_info_display (menu_t *menu, surface_t *display); +void view_load_rom_init (menu_t *menu); +void view_load_rom_display (menu_t *menu, surface_t *display); + +void view_load_disk_init (menu_t *menu); +void view_load_disk_display (menu_t *menu, surface_t *display); + void view_load_emulator_init (menu_t *menu); void view_load_emulator_display (menu_t *menu, surface_t *display);