LKP-Core-2040

[dogtopus]

Yet another cheap+JLCPCBAble attempt. Uses RP2040+CY8CMBR3116-LQXI. Will likely have a different firmware than LKP-Core due to significant architecture change.

• Initial feasibility study
  • Datasheet, register map and design guide (has more info on purpose of registers and design patterns) for CY8CMBR3116-LQXI
  • In the dev board manual: "Cannot be used because GPO7 is multiplexed with
    the host interrupt so brought out to a header." Is interrupt not usable? (Looks like it should be usable if we just set it to ~HI right after boot.)
  • No active shielding will be available since it's muxed with one of the 16 sensor pins, which we need all of them to be used as sensors. Might be an OK tradeoff since the official controller doesn't have shielding either. In this case, the shield pins on the tile should probably be connected to the ground or floating.
    • Measure it on LKP-Core by disabling and {,not} shorting SH to ground (or put them in open drain low/high mode).
      • Result: Driving to ground increases Imod considerably (~22 -> ~33) due to higher parasitic capacitance although still within spec and SNR stays roughly in line with default, but floating causes the SNR to drop significantly (~80-90 to ~33 on naked PCB). Go with grounding SH seems to be the better choice.
    • This can probably also be compensated somewhat by parallel scanning and sensitivity increase, as long as parasitic capacitance is under control.
• Schematics
• Firmware PoC
• Initial PnR
  • 4 layer stack (in general): touch, 3v3+keepout, gnd+hatch, rp2040. may put touch @ bottom. put some passives (namely cmod but potentially other caps as well) at opposite plus using blind vias to increase density
  • PH power at the bottom, USB at the top
• PCB Prototype
• Firmware PoC test