diff --git a/qiskit/visualization/circuit/circuit_visualization.py b/qiskit/visualization/circuit/circuit_visualization.py index 1aaa42c32d4f..ebb0d69bebe2 100644 --- a/qiskit/visualization/circuit/circuit_visualization.py +++ b/qiskit/visualization/circuit/circuit_visualization.py @@ -141,8 +141,9 @@ def circuit_drawer( it is redundant. initial_state (bool): Optional. Adds ``|0>`` in the beginning of the wire. Default is False. - cregbundle (bool): Optional. If set True, bundle classical registers. - Default is True, except for when ``output`` is set to ``"text"``. + cregbundle (bool): Optional. If set True, bundle classical registers into a single wire. + Default is true if possible, and false if a block instruction needs to access an + individual bit from a register. wire_order (list): Optional. A list of integers used to reorder the display of the bits. The list must have an entry for every bit with the bits in the range 0 to (num_qubits + num_clbits). @@ -207,13 +208,14 @@ def circuit_drawer( "wire_order list for the index of each qubit and each clbit in the circuit." ) - if circuit.clbits and cregbundle and (reverse_bits or wire_order is not None): + if circuit.clbits and (reverse_bits or wire_order is not None): + if cregbundle: + warn( + "cregbundle set to False since either reverse_bits or wire_order has been set.", + RuntimeWarning, + 2, + ) cregbundle = False - warn( - "Cregbundle set to False since either reverse_bits or wire_order has been set.", - RuntimeWarning, - 2, - ) if output == "text": return _text_circuit_drawer( circuit, @@ -241,7 +243,7 @@ def circuit_drawer( idle_wires=idle_wires, with_layout=with_layout, initial_state=initial_state, - cregbundle=cregbundle if cregbundle is not None else True, + cregbundle=cregbundle, wire_order=wire_order, ) elif output == "latex_source": @@ -256,7 +258,7 @@ def circuit_drawer( idle_wires=idle_wires, with_layout=with_layout, initial_state=initial_state, - cregbundle=cregbundle if cregbundle is not None else True, + cregbundle=cregbundle, wire_order=wire_order, ) elif output == "mpl": @@ -391,7 +393,7 @@ def _latex_circuit_drawer( idle_wires=True, with_layout=True, initial_state=False, - cregbundle=False, + cregbundle=None, wire_order=None, ): """Draw a quantum circuit based on latex (Qcircuit package) @@ -414,8 +416,8 @@ def _latex_circuit_drawer( layout. Default: True initial_state (bool): Optional. Adds |0> in the beginning of the line. Default: `False`. - cregbundle (bool): Optional. If set True, bundle classical registers. - Default: ``False``. + cregbundle (bool): Optional. If set True, bundle classical registers. On by default, if + this is possible for the given circuit, otherwise off. wire_order (list): Optional. A list of integers used to reorder the display of the bits. The list must have an entry for every bit with the bits in the range 0 to (num_qubits + num_clbits). @@ -510,7 +512,7 @@ def _generate_latex_source( idle_wires=True, with_layout=True, initial_state=False, - cregbundle=False, + cregbundle=None, wire_order=None, ): """Convert QuantumCircuit to LaTeX string. @@ -532,7 +534,6 @@ def _generate_latex_source( initial_state (bool): Optional. Adds |0> in the beginning of the line. Default: `False`. cregbundle (bool): Optional. If set True, bundle classical registers. - Default: ``False``. wire_order (list): Optional. A list of integers used to reorder the display of the bits. The list must have an entry for every bit with the bits in the range 0 to (num_qubits + num_clbits). @@ -590,7 +591,7 @@ def _matplotlib_circuit_drawer( fold=None, ax=None, initial_state=False, - cregbundle=True, + cregbundle=None, wire_order=None, ): @@ -652,7 +653,7 @@ def _matplotlib_circuit_drawer( fold=fold, ax=ax, initial_state=initial_state, - cregbundle=cregbundle if cregbundle is not None else True, + cregbundle=cregbundle, global_phase=None, calibrations=None, qregs=None, diff --git a/qiskit/visualization/circuit/latex.py b/qiskit/visualization/circuit/latex.py index bfd57d6472de..4f97ea34fc44 100644 --- a/qiskit/visualization/circuit/latex.py +++ b/qiskit/visualization/circuit/latex.py @@ -13,6 +13,7 @@ """latex visualization backend.""" import io +import itertools import math import re from warnings import warn @@ -57,7 +58,7 @@ def __init__( plot_barriers=True, layout=None, initial_state=False, - cregbundle=False, + cregbundle=None, global_phase=None, qregs=None, cregs=None, @@ -78,7 +79,7 @@ def __init__( layout (Layout or None): If present, the layout information will be included. initial_state (bool): Optional. Adds |0> in the beginning of the line. Default: `False`. - cregbundle (bool): Optional. If set True bundle classical registers. Default: `False`. + cregbundle (bool): Optional. If set True bundle classical registers. global_phase (float): Optional, the global phase for the circuit. circuit (QuantumCircuit): the circuit that's being displayed Raises: @@ -183,15 +184,23 @@ def __init__( self._layout = None self._initial_state = initial_state - self._cregbundle = cregbundle self._global_phase = circuit.global_phase # If there is any custom instruction that uses classical bits # then cregbundle is forced to be False. - for layer in self._nodes: - for node in layer: - if node.op.name not in {"measure"} and node.cargs: - self._cregbundle = False + for node in itertools.chain.from_iterable(self._nodes): + if node.cargs and node.op.name != "measure": + if cregbundle: + warn( + "Cregbundle set to False since an instruction needs to refer" + " to individual classical wire", + RuntimeWarning, + 2, + ) + self._cregbundle = False + break + else: + self._cregbundle = True if cregbundle is None else cregbundle self._wire_map = get_wire_map(circuit, qubits + clbits, self._cregbundle) self._img_width = len(self._wire_map) diff --git a/qiskit/visualization/circuit/matplotlib.py b/qiskit/visualization/circuit/matplotlib.py index 32393cd9bef4..155afff43776 100644 --- a/qiskit/visualization/circuit/matplotlib.py +++ b/qiskit/visualization/circuit/matplotlib.py @@ -14,6 +14,7 @@ """mpl circuit visualization backend.""" +import itertools import re from warnings import warn @@ -76,7 +77,7 @@ def __init__( fold=25, ax=None, initial_state=False, - cregbundle=True, + cregbundle=None, global_phase=None, qregs=None, cregs=None, @@ -194,10 +195,23 @@ def __init__( self._ax.tick_params(labelbottom=False, labeltop=False, labelleft=False, labelright=False) self._initial_state = initial_state - self._cregbundle = cregbundle self._global_phase = self._circuit.global_phase self._calibrations = self._circuit.calibrations + for node in itertools.chain.from_iterable(self._nodes): + if node.cargs and node.op.name != "measure": + if cregbundle: + warn( + "Cregbundle set to False since an instruction needs to refer" + " to individual classical wire", + RuntimeWarning, + 3, + ) + self._cregbundle = False + break + else: + self._cregbundle = True if cregbundle is None else cregbundle + self._fs = self._style["fs"] self._sfs = self._style["sfs"] self._lwidth1 = 1.0 @@ -407,14 +421,6 @@ def _get_layer_widths(self): widest_box = WID for node in layer: op = node.op - if self._cregbundle and node.cargs and not isinstance(op, Measure): - self._cregbundle = False - warn( - "Cregbundle set to False since an instruction needs to refer" - " to individual classical wire", - RuntimeWarning, - 2, - ) self._data[node] = {} self._data[node]["width"] = WID num_ctrl_qubits = 0 if not hasattr(op, "num_ctrl_qubits") else op.num_ctrl_qubits diff --git a/qiskit/visualization/circuit/text.py b/qiskit/visualization/circuit/text.py index 71c70cf2d0e0..ee927e51a5da 100644 --- a/qiskit/visualization/circuit/text.py +++ b/qiskit/visualization/circuit/text.py @@ -16,6 +16,7 @@ from warnings import warn from shutil import get_terminal_size +import itertools import sys from qiskit.circuit import Qubit, Clbit, ClassicalRegister, QuantumRegister, QuantumCircuit @@ -37,13 +38,6 @@ from ..exceptions import VisualizationError -class TextDrawerCregBundle(VisualizationError): - """The parameter "cregbundle" was set to True in an impossible situation. For example, - a node needs to refer to individual classical wires'""" - - pass - - class TextDrawerEncodingError(VisualizationError): """A problem with encoding""" @@ -678,8 +672,6 @@ def __init__( self.layout = None self.initial_state = initial_state - self._cregbundle = cregbundle - self._default_cregbundle = False self.global_phase = circuit.global_phase self.plotbarriers = plotbarriers self.reverse_bits = reverse_bits @@ -689,6 +681,20 @@ def __init__( self.vertical_compression = vertical_compression self._wire_map = {} + for node in itertools.chain.from_iterable(self.nodes): + if node.cargs and node.op.name != "measure": + if cregbundle: + warn( + "Cregbundle set to False since an instruction needs to refer" + " to individual classical wire", + RuntimeWarning, + 2, + ) + self.cregbundle = False + break + else: + self.cregbundle = True if cregbundle is None else cregbundle + if encoding: self.encoding = encoding else: @@ -697,13 +703,6 @@ def __init__( else: self.encoding = "utf8" - @property - def cregbundle(self): - """cregbundle, depending if it was explicitly set or not""" - if self._cregbundle is not None: - return self._cregbundle - return self._default_cregbundle - def __str__(self): return self.single_string() @@ -769,19 +768,7 @@ def lines(self, line_length=None): noqubits = len(self.qubits) - try: - layers = self.build_layers() - except TextDrawerCregBundle: - if self._cregbundle is not None: - self._cregbundle = False - warn( - 'The parameter "cregbundle" was disabled, since an instruction needs to refer to ' - "individual classical wires", - RuntimeWarning, - 2, - ) - layers = self.build_layers() - + layers = self.build_layers() layer_groups = [[]] rest_of_the_line = line_length for layerno, layer in enumerate(layers): @@ -1167,8 +1154,6 @@ def add_connected_gate(node, gates, layer, current_cons): layer.set_qu_multibox(node.qargs, gate_text, conditional=conditional) elif node.qargs and node.cargs: - if self.cregbundle and node.cargs: - raise TextDrawerCregBundle("TODO") layer._set_multibox( gate_text, qubits=node.qargs, diff --git a/releasenotes/notes/fix-cregbundle-warning-d3c991bb6276761d.yaml b/releasenotes/notes/fix-cregbundle-warning-d3c991bb6276761d.yaml new file mode 100644 index 000000000000..490b875762a7 --- /dev/null +++ b/releasenotes/notes/fix-cregbundle-warning-d3c991bb6276761d.yaml @@ -0,0 +1,7 @@ +--- +fixes: + - | + The circuit drawers (:meth:`.QuantumCircuit.draw` and :func:`.circuit_drawer`) will no + longer emit a warning about the ``cregbundle`` parameter when using the default arguments, + if the content of the circuit requires all bits to be drawn individually. This was most + likely to appear when trying to draw circuits with new-style control-flow operations. diff --git a/test/python/visualization/test_circuit_drawer.py b/test/python/visualization/test_circuit_drawer.py index f85839db09bc..8e5462eca67e 100644 --- a/test/python/visualization/test_circuit_drawer.py +++ b/test/python/visualization/test_circuit_drawer.py @@ -117,7 +117,7 @@ def test_wire_order_raises(self): with self.assertRaisesRegex(VisualizationError, "cannot be set when the reverse_bits"): visualization.circuit_drawer(circuit, wire_order=[0, 1, 2, 5, 4, 3], reverse_bits=True) - with self.assertWarnsRegex(RuntimeWarning, "Cregbundle set"): + with self.assertWarnsRegex(RuntimeWarning, "cregbundle set"): visualization.circuit_drawer(circuit, cregbundle=True, wire_order=[0, 1, 2, 5, 4, 3]) def test_reverse_bits(self): @@ -159,5 +159,10 @@ def test_no_explict_cregbundle(self): " ", ] ) - result = visualization.circuit_drawer(circuit) + result = circuit.draw("text") self.assertEqual(result.__str__(), expected) + # Extra tests that no cregbundle (or any other) warning is raised with the default settings + # for the other drawers, if they're available to test. + circuit.draw("latex_source") + if optionals.HAS_MATPLOTLIB and optionals.HAS_PYLATEX: + circuit.draw("mpl") diff --git a/test/python/visualization/test_circuit_text_drawer.py b/test/python/visualization/test_circuit_text_drawer.py index c9ac2a9f9629..839193934a7f 100644 --- a/test/python/visualization/test_circuit_text_drawer.py +++ b/test/python/visualization/test_circuit_text_drawer.py @@ -112,22 +112,22 @@ def test_text_pager(self): " └─┬─┘┌─┴─┐»", "q_1: |0>──■──┤ X ├»", " └───┘»", - " c: 0 ══════════»", + " c: 0 1/══════════»", " »", "« ┌─┐┌───┐ »", "«q_0: ┤M├┤ X ├──■──»", "« └╥┘└─┬─┘┌─┴─┐»", "«q_1: ─╫───■──┤ X ├»", "« ║ └───┘»", - "« c: ═╩═══════════»", - "« »", + "«c: 1/═╩═══════════»", + "« 0 »", "« ┌─┐┌───┐ ", "«q_0: ┤M├┤ X ├──■──", "« └╥┘└─┬─┘┌─┴─┐", "«q_1: ─╫───■──┤ X ├", "« ║ └───┘", - "« c: ═╩═══════════", - "« ", + "«c: 1/═╩═══════════", + "« 0 ", ] ) @@ -227,7 +227,7 @@ def test_text_measure_1(self): cr = ClassicalRegister(3, "c") circuit = QuantumCircuit(qr, cr) circuit.measure(qr, cr) - self.assertEqual(str(_text_circuit_drawer(circuit)), expected) + self.assertEqual(str(_text_circuit_drawer(circuit, cregbundle=False)), expected) def test_text_measure_1_reverse_bits(self): """The measure operator, using 3-bit-length registers, with reverse_bits""" @@ -240,12 +240,8 @@ def test_text_measure_1_reverse_bits(self): " ┌─┐└╥┘ ║ ", "q_0: |0>┤M├─╫──╫─", " └╥┘ ║ ║ ", - " c_2: 0 ═╬══╬══╩═", - " ║ ║ ", - " c_1: 0 ═╬══╩════", - " ║ ", - " c_0: 0 ═╩═══════", - " ", + " c: 0 3/═╩══╩══╩═", + " 0 1 2 ", ] ) @@ -268,14 +264,10 @@ def test_text_measure_2(self): " └╥┘┌─┐", "q2_1: |0>─╫─┤M├", " ║ └╥┘", - " c1_0: 0 ═╬══╬═", - " ║ ║ ", - " c1_1: 0 ═╬══╬═", + " c1: 0 2/═╬══╬═", " ║ ║ ", - " c2_0: 0 ═╩══╬═", - " ║ ", - " c2_1: 0 ════╩═", - " ", + " c2: 0 2/═╩══╩═", + " 0 1 ", ] ) @@ -300,13 +292,9 @@ def test_text_measure_2_reverse_bits(self): " ║ ║ ", "q1_0: |0>─╫──╫─", " ║ ║ ", - " c2_1: 0 ═╬══╩═", - " ║ ", - " c2_0: 0 ═╩════", - " ", - " c1_1: 0 ══════", - " ", - " c1_0: 0 ══════", + " c2: 0 2/═╩══╩═", + " 0 1 ", + " c1: 0 2/══════", " ", ] ) @@ -323,27 +311,19 @@ def test_wire_order(self): """Test the wire_order option""" expected = "\n".join( [ - " ", - "q_2: |0>──────────", - " ┌───┐ ", - "q_1: |0>┤ X ├─────", - " ├───┤┌───┐", - "q_3: |0>┤ H ├┤ X ├", - " ├───┤└─╥─┘", - "q_0: |0>┤ H ├──╫──", - " └───┘ ║ ", - " c_2: 0 ═══════o══", - " ║ ", - "ca_0: 0 ═══════╬══", - " ║ ", - "ca_1: 0 ═══════╬══", - " ║ ", - " c_1: 0 ═══════■══", - " ║ ", - " c_0: 0 ═══════o══", - " ║ ", - " c_3: 0 ═══════■══", - " 0xa ", + " ", + "q_2: |0>────────────", + " ┌───┐ ", + "q_1: |0>┤ X ├───────", + " ├───┤ ┌───┐ ", + "q_3: |0>┤ H ├─┤ X ├─", + " ├───┤ └─╥─┘ ", + "q_0: |0>┤ H ├───╫───", + " └───┘┌──╨──┐", + " c: 0 4/═════╡ 0xa ╞", + " └─────┘", + "ca: 0 2/════════════", + " ", ] ) qr = QuantumRegister(4, "q") @@ -684,13 +664,9 @@ def test_text_cu1_condition(self): "q_1: ────────■────────", " ║ ", "q_2: ────────╫────────", - " ║ ", - "c_0: ════════╬════════", - " ║ ", - "c_1: ════════■════════", - " ", - "c_2: ═════════════════", - " ", + " ┌────╨────┐ ", + "c: 3/═══╡ c_1=0x1 ╞═══", + " └─────────┘ ", ] ) qr = QuantumRegister(3, "q") @@ -709,13 +685,9 @@ def test_text_rzz_condition(self): "q_1: ────────■────────", " ║ ", "q_2: ────────╫────────", - " ║ ", - "c_0: ════════╬════════", - " ║ ", - "c_1: ════════■════════", - " ", - "c_2: ═════════════════", - " ", + " ┌────╨────┐ ", + "c: 3/═══╡ c_1=0x1 ╞═══", + " └─────────┘ ", ] ) qr = QuantumRegister(3, "q") @@ -734,13 +706,9 @@ def test_text_cp_condition(self): "q_1: ───────■───────", " ║ ", "q_2: ───────╫───────", - " ║ ", - "c_0: ═══════╬═══════", - " ║ ", - "c_1: ═══════■═══════", - " ", - "c_2: ═══════════════", - " ", + " ┌────╨────┐ ", + "c: 3/══╡ c_1=0x1 ╞══", + " └─────────┘ ", ] ) qr = QuantumRegister(3, "q") @@ -914,11 +882,11 @@ def test_text_measure_html(self): "background: #fff0;" "line-height: 1.1;" 'font-family: "Courier New",Courier,monospace">' - " ┌─┐", - "q: |0>┤M├", - " └╥┘", - " c: 0 ═╩═", - " ", + " ┌─┐", + " q: |0>┤M├", + " └╥┘", + "c: 0 1/═╩═", + " 0 ", ] ) qr = QuantumRegister(1, "q") @@ -929,13 +897,15 @@ def test_text_measure_html(self): def test_text_repr(self): """The measure operator. repr.""" - # fmt: off - expected = "\n".join([" ┌─┐", - "q: |0>┤M├", - " └╥┘", - " c: 0 ═╩═", - " "]) - # fmt: on + expected = "\n".join( + [ + " ┌─┐", + " q: |0>┤M├", + " └╥┘", + "c: 0 1/═╩═", + " 0 ", + ] + ) qr = QuantumRegister(1, "q") cr = ClassicalRegister(1, "c") circuit = QuantumCircuit(qr, cr) @@ -951,10 +921,8 @@ def test_text_justify_left(self): " ├───┤┌─┐", "q1_1: |0>┤ H ├┤M├", " └───┘└╥┘", - " c1_0: 0 ══════╬═", - " ║ ", - " c1_1: 0 ══════╩═", - " ", + " c1: 0 2/══════╩═", + " 1 ", ] ) @@ -975,10 +943,8 @@ def test_text_justify_right(self): " ┌───┐└┬─┬┘", "q1_1: |0>┤ H ├─┤M├─", " └───┘ └╥┘ ", - " c1_0: 0 ═══════╬══", - " ║ ", - " c1_1: 0 ═══════╩══", - " ", + " c1: 0 2/═══════╩══", + " 1 ", ] ) @@ -999,10 +965,8 @@ def test_text_justify_none(self): " └───┘┌───┐┌─┐", "q1_1: |0>─────┤ H ├┤M├", " └───┘└╥┘", - " c1_0: 0 ═══════════╬═", - " ║ ", - " c1_1: 0 ═══════════╩═", - " ", + " c1: 0 2/═══════════╩═", + " 1 ", ] ) @@ -1105,10 +1069,8 @@ def test_text_overlap_measure(self): " └╥┘┌───┐", "q1_1: |0>─╫─┤ X ├", " ║ └───┘", - " c1_0: 0 ═╩══════", - " ", - " c1_1: 0 ════════", - " ", + " c1: 0 2/═╩══════", + " 0 ", ] ) @@ -1150,10 +1112,8 @@ def test_text_justify_right_measure_resize(self): " └┬─┬┘", "q1_1: |0>─┤M├─", " └╥┘ ", - " c1_0: 0 ══╬══", - " ║ ", - " c1_1: 0 ══╩══", - " ", + " c1: 0 2/══╩══", + " 1 ", ] ) @@ -1538,9 +1498,9 @@ def test_control_gate_label_with_cond_1_low(self): " ┌──┴───┐", "q_1: |0>┤ my h ├", " └──╥───┘", - " ║ ", - " c: 0 ═══■════", - " 0x1 ", + " ┌──╨──┐ ", + " c: 0 1/╡ 0x1 ╞═", + " └─────┘ ", ] ) @@ -1603,7 +1563,10 @@ def test_control_gate_label_with_cond_1_med(self): controlh = hgate.control(label="my ch").c_if(cr, 1) circ.append(controlh, [0, 1]) - self.assertEqual(str(_text_circuit_drawer(circ, vertical_compression="medium")), expected) + self.assertEqual( + str(_text_circuit_drawer(circ, cregbundle=False, vertical_compression="medium")), + expected, + ) def test_control_gate_label_with_cond_1_med_cregbundle(self): """Control gate has a label and a conditional (compression=med) with cregbundle @@ -1655,7 +1618,9 @@ def test_control_gate_label_with_cond_1_high(self): controlh = hgate.control(label="my ch").c_if(cr, 1) circ.append(controlh, [0, 1]) - self.assertEqual(str(_text_circuit_drawer(circ, vertical_compression="high")), expected) + self.assertEqual( + str(_text_circuit_drawer(circ, cregbundle=False, vertical_compression="high")), expected + ) def test_control_gate_label_with_cond_1_high_cregbundle(self): """Control gate has a label and a conditional (compression=high) with cregbundle @@ -1692,9 +1657,10 @@ def test_control_gate_label_with_cond_2_med_space(self): "q_0: |0>┤ my h ├", " └──┬───┘", "q_1: |0>───■────", - " my║ch ", - " c: 0 ═══■════", - " 0x1 ", + " my ch ", + " ┌──╨──┐ ", + " c: 0 1/╡ 0x1 ╞═", + " └─────┘ ", ] ) @@ -1730,7 +1696,10 @@ def test_control_gate_label_with_cond_2_med(self): controlh = hgate.control(label="my ctrl-h").c_if(cr, 1) circ.append(controlh, [1, 0]) - self.assertEqual(str(_text_circuit_drawer(circ, vertical_compression="medium")), expected) + self.assertEqual( + str(_text_circuit_drawer(circ, cregbundle=False, vertical_compression="medium")), + expected, + ) def test_control_gate_label_with_cond_2_med_cregbundle(self): """Control gate has a label and a conditional (on label, compression=med) with cregbundle @@ -1784,7 +1753,9 @@ def test_control_gate_label_with_cond_2_low(self): controlh = hgate.control(label="my ch").c_if(cr, 1) circ.append(controlh, [1, 0]) - self.assertEqual(str(_text_circuit_drawer(circ, vertical_compression="low")), expected) + self.assertEqual( + str(_text_circuit_drawer(circ, cregbundle=False, vertical_compression="low")), expected + ) def test_control_gate_label_with_cond_2_low_cregbundle(self): """Control gate has a label and a conditional (on label, compression=low) with cregbundle @@ -1913,7 +1884,10 @@ def test_text_conditional_1(self): ) circuit = QuantumCircuit.from_qasm_str(qasm_string) - self.assertEqual(str(_text_circuit_drawer(circuit, vertical_compression="low")), expected) + self.assertEqual( + str(_text_circuit_drawer(circuit, cregbundle=False, vertical_compression="low")), + expected, + ) def test_text_conditional_1_bundle(self): """Conditional drawing with 1-bit-length regs.""" @@ -2029,11 +2003,8 @@ def test_text_justify_right(self): "q1_1: |0>┤ H ├─┤M├─", " └───┘ └╥┘ ", " ║ ", - " c1_0: 0 ═══════╬══", - " ║ ", - " ║ ", - " c1_1: 0 ═══════╩══", - " ", + " c1: 0 2/═══════╩══", + " 1 ", ] ) @@ -2076,7 +2047,8 @@ def test_text_conditional_1(self): ) circuit = QuantumCircuit.from_qasm_str(qasm_string) self.assertEqual( - str(_text_circuit_drawer(circuit, vertical_compression="medium")), expected + str(_text_circuit_drawer(circuit, cregbundle=False, vertical_compression="medium")), + expected, ) def test_text_conditional_1_bundle(self): @@ -2138,7 +2110,8 @@ def test_text_measure_with_spaces(self): ) circuit = QuantumCircuit.from_qasm_str(qasm_string) self.assertEqual( - str(_text_circuit_drawer(circuit, vertical_compression="medium")), expected + str(_text_circuit_drawer(circuit, cregbundle=False, vertical_compression="medium")), + expected, ) def test_text_measure_with_spaces_bundle(self): @@ -2317,7 +2290,7 @@ def test_text_conditional_1(self): ) circuit = QuantumCircuit.from_qasm_str(qasm_string) - self.assertEqual(str(_text_circuit_drawer(circuit)), expected) + self.assertEqual(str(_text_circuit_drawer(circuit, cregbundle=False)), expected) def test_text_conditional_2_cregbundle(self): """Conditional drawing with 2-bit-length regs with cregbundle""" @@ -2371,7 +2344,7 @@ def test_text_conditional_2(self): ] ) circuit = QuantumCircuit.from_qasm_str(qasm_string) - self.assertEqual(str(_text_circuit_drawer(circuit)), expected) + self.assertEqual(str(_text_circuit_drawer(circuit, cregbundle=False)), expected) def test_text_conditional_3_cregbundle(self): """Conditional drawing with 3-bit-length regs with cregbundle.""" @@ -2429,7 +2402,7 @@ def test_text_conditional_3(self): ] ) circuit = QuantumCircuit.from_qasm_str(qasm_string) - self.assertEqual(str(_text_circuit_drawer(circuit)), expected) + self.assertEqual(str(_text_circuit_drawer(circuit, cregbundle=False)), expected) def test_text_conditional_4(self): """Conditional drawing with 4-bit-length regs.""" @@ -2444,25 +2417,13 @@ def test_text_conditional_4(self): """ expected = "\n".join( [ - " ┌───┐┌───┐", - " q: |0>┤ X ├┤ X ├", - " └─╥─┘└─╥─┘", - "c0_0: 0 ══o════╬══", - " ║ ║ ", - "c0_1: 0 ══o════╬══", - " ║ ║ ", - "c0_2: 0 ══■════╬══", - " ║ ║ ", - "c0_3: 0 ══o════╬══", - " 0x4 ║ ", - "c1_0: 0 ═══════o══", - " ║ ", - "c1_1: 0 ═══════o══", - " ║ ", - "c1_2: 0 ═══════■══", - " ║ ", - "c1_3: 0 ═══════o══", - " 0x4 ", + " ┌───┐ ┌───┐ ", + " q: |0>─┤ X ├──┤ X ├─", + " ┌┴─╨─┴┐ └─╥─┘ ", + "c0: 0 4/╡ 0x4 ╞═══╬═══", + " └─────┘┌──╨──┐", + "c1: 0 4/═══════╡ 0x4 ╞", + " └─────┘", ] ) circuit = QuantumCircuit.from_qasm_str(qasm_string) @@ -2507,7 +2468,7 @@ def test_text_conditional_5(self): ] ) circuit = QuantumCircuit.from_qasm_str(qasm_string) - self.assertEqual(str(_text_circuit_drawer(circuit)), expected) + self.assertEqual(str(_text_circuit_drawer(circuit, cregbundle=False)), expected) def test_text_conditional_cz_no_space_cregbundle(self): """Conditional CZ without space""" @@ -2549,7 +2510,7 @@ def test_text_conditional_cz_no_space(self): ] ) - self.assertEqual(str(_text_circuit_drawer(circuit)), expected) + self.assertEqual(str(_text_circuit_drawer(circuit, cregbundle=False)), expected) def test_text_conditional_cz_cregbundle(self): """Conditional CZ with a wire in the middle""" @@ -2595,7 +2556,7 @@ def test_text_conditional_cz(self): ] ) - self.assertEqual(str(_text_circuit_drawer(circuit)), expected) + self.assertEqual(str(_text_circuit_drawer(circuit, cregbundle=False)), expected) def test_text_conditional_cx_ct_cregbundle(self): """Conditional CX (control-target) with a wire in the middle""" @@ -2641,7 +2602,7 @@ def test_text_conditional_cx_ct(self): ] ) - self.assertEqual(str(_text_circuit_drawer(circuit)), expected) + self.assertEqual(str(_text_circuit_drawer(circuit, cregbundle=False)), expected) def test_text_conditional_cx_tc_cregbundle(self): """Conditional CX (target-control) with a wire in the middle with cregbundle.""" @@ -2687,7 +2648,7 @@ def test_text_conditional_cx_tc(self): ] ) - self.assertEqual(str(_text_circuit_drawer(circuit)), expected) + self.assertEqual(str(_text_circuit_drawer(circuit, cregbundle=False)), expected) def test_text_conditional_cu3_ct_cregbundle(self): """Conditional Cu3 (control-target) with a wire in the middle with cregbundle""" @@ -2733,7 +2694,7 @@ def test_text_conditional_cu3_ct(self): ] ) - self.assertEqual(str(_text_circuit_drawer(circuit)), expected) + self.assertEqual(str(_text_circuit_drawer(circuit, cregbundle=False)), expected) def test_text_conditional_cu3_tc_cregbundle(self): """Conditional Cu3 (target-control) with a wire in the middle with cregbundle""" @@ -2779,7 +2740,7 @@ def test_text_conditional_cu3_tc(self): ] ) - self.assertEqual(str(_text_circuit_drawer(circuit)), expected) + self.assertEqual(str(_text_circuit_drawer(circuit, cregbundle=False)), expected) def test_text_conditional_ccx_cregbundle(self): """Conditional CCX with a wire in the middle with cregbundle""" @@ -2829,7 +2790,7 @@ def test_text_conditional_ccx(self): ] ) - self.assertEqual(str(_text_circuit_drawer(circuit)), expected) + self.assertEqual(str(_text_circuit_drawer(circuit, cregbundle=False)), expected) def test_text_conditional_ccx_no_space_cregbundle(self): """Conditional CCX without space with cregbundle""" @@ -2875,7 +2836,7 @@ def test_text_conditional_ccx_no_space(self): ] ) - self.assertEqual(str(_text_circuit_drawer(circuit)), expected) + self.assertEqual(str(_text_circuit_drawer(circuit, cregbundle=False)), expected) def test_text_conditional_h_cregbundle(self): """Conditional H with a wire in the middle with cregbundle""" @@ -2917,7 +2878,7 @@ def test_text_conditional_h(self): ] ) - self.assertEqual(str(_text_circuit_drawer(circuit)), expected) + self.assertEqual(str(_text_circuit_drawer(circuit, cregbundle=False)), expected) def test_text_conditional_swap_cregbundle(self): """Conditional SWAP with cregbundle""" @@ -2963,7 +2924,7 @@ def test_text_conditional_swap(self): ] ) - self.assertEqual(str(_text_circuit_drawer(circuit)), expected) + self.assertEqual(str(_text_circuit_drawer(circuit, cregbundle=False)), expected) def test_text_conditional_cswap_cregbundle(self): """Conditional CSwap with cregbundle""" @@ -3013,7 +2974,7 @@ def test_text_conditional_cswap(self): ] ) - self.assertEqual(str(_text_circuit_drawer(circuit)), expected) + self.assertEqual(str(_text_circuit_drawer(circuit, cregbundle=False)), expected) def test_conditional_reset_cregbundle(self): """Reset drawing with cregbundle.""" @@ -3057,7 +3018,7 @@ def test_conditional_reset(self): ] ) - self.assertEqual(str(_text_circuit_drawer(circuit)), expected) + self.assertEqual(str(_text_circuit_drawer(circuit, cregbundle=False)), expected) def test_conditional_multiplexer_cregbundle(self): """Test Multiplexer with cregbundle.""" @@ -3105,7 +3066,7 @@ def test_conditional_multiplexer(self): ] ) - self.assertEqual(str(_text_circuit_drawer(qc)), expected) + self.assertEqual(str(_text_circuit_drawer(qc, cregbundle=False)), expected) def test_text_conditional_measure_cregbundle(self): """Conditional with measure on same clbit with cregbundle""" @@ -3152,7 +3113,7 @@ def test_text_conditional_measure(self): " 0x1 ", ] ) - self.assertEqual(str(_text_circuit_drawer(circuit)), expected) + self.assertEqual(str(_text_circuit_drawer(circuit, cregbundle=False)), expected) def test_text_bit_conditional(self): """Test bit conditions on gates""" @@ -3177,7 +3138,7 @@ def test_text_bit_conditional(self): ] ) - self.assertEqual(str(_text_circuit_drawer(circuit)), expected) + self.assertEqual(str(_text_circuit_drawer(circuit, cregbundle=False)), expected) def test_text_bit_conditional_cregbundle(self): """Test bit conditions on gates when cregbundle=True""" @@ -3399,10 +3360,8 @@ def test_text_measure(self): " └╥┘┌─┐", "q2_1: |0>─╫─┤M├", " ║ └╥┘", - " c2_0: 0 ═╩══╬═", - " ║ ", - " c2_1: 0 ════╩═", - " ", + " c2: 0 2/═╩══╩═", + " 0 1 ", ] ) qr1 = QuantumRegister(2, "q1") @@ -4191,17 +4150,17 @@ def test_cccz_conditional(self): """Closed-Open controlled Z (with conditional)""" expected = "\n".join( [ - " ", - "q_0: |0>──■──", - " │ ", - "q_1: |0>──o──", - " │ ", - "q_2: |0>──■──", - " │ ", - "q_3: |0>──■──", - " ║ ", - " c: 0 ══■══", - " 0x1 ", + " ", + "q_0: |0>───■───", + " │ ", + "q_1: |0>───o───", + " │ ", + "q_2: |0>───■───", + " │ ", + "q_3: |0>───■───", + " ┌──╨──┐", + " c: 0 1/╡ 0x1 ╞", + " └─────┘", ] ) qr = QuantumRegister(4, "q") @@ -4769,10 +4728,8 @@ def test_with_classical_regs(self): " └╥┘┌─┐", "qr2_1 -> 3 |0>─╫─┤M├", " ║ └╥┘", - " cr_0: 0 ═╩══╬═", - " ║ ", - " cr_1: 0 ════╩═", - " ", + " cr: 0 2/═╩══╩═", + " 0 1 ", ] ) qr1 = QuantumRegister(2, "qr1") @@ -4802,10 +4759,8 @@ def test_with_layout_but_disable(self): " └╥┘┌─┐", "q_3: |0>─╫─┤M├", " ║ └╥┘", - "cr_0: 0 ═╩══╬═", - " ║ ", - "cr_1: 0 ════╩═", - " ", + "cr: 0 2/═╩══╩═", + " 0 1 ", ] ) pqr = QuantumRegister(4, "q") @@ -4954,10 +4909,8 @@ def test_initial_value_false(self): " └╥┘┌─┐", "q_1: ─╫─┤M├", " ║ └╥┘", - "c_0: ═╩══╬═", - " ║ ", - "c_1: ════╩═", - " ", + "c: 2/═╩══╩═", + " 0 1 ", ] )