From 673e54d3adcba2152a68dfe205845a79ea61bbd7 Mon Sep 17 00:00:00 2001
From: "mergify[bot]" <37929162+mergify[bot]@users.noreply.github.com>
Date: Sat, 22 Jan 2022 01:07:44 +0000
Subject: [PATCH] Check the existence of AncillaQubits before adding (#7450)
 (#7555)

* Check the existance of AncillaQubits before adding

* Add a test case that calls add_register twice

* Add a release note

* Reword release note

Co-authored-by: Jake Lishman <jake.lishman@ibm.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
Co-authored-by: Kevin Krsulich <kevin.krsulich@ibm.com>
(cherry picked from commit 84c3985a216dcd96ccf3e78c8c01aba29e81c348)

Co-authored-by: Jintao YU <yjt98765@gmail.com>
---
 qiskit/circuit/quantumcircuit.py              |  4 ++-
 ...ter-without-checking-abe367dab5a63dbb.yaml |  6 ++++
 .../python/circuit/test_circuit_operations.py | 36 +++++++++++++++++++
 3 files changed, 45 insertions(+), 1 deletion(-)
 create mode 100644 releasenotes/notes/fix-adding-ancilla-register-without-checking-abe367dab5a63dbb.yaml

diff --git a/qiskit/circuit/quantumcircuit.py b/qiskit/circuit/quantumcircuit.py
index c0fbda455e94..24df569b3d51 100644
--- a/qiskit/circuit/quantumcircuit.py
+++ b/qiskit/circuit/quantumcircuit.py
@@ -1352,7 +1352,9 @@ def add_register(self, *regs: Union[Register, int, Sequence[Bit]]) -> None:
                 raise CircuitError('register name "%s" already exists' % register.name)
 
             if isinstance(register, AncillaRegister):
-                self._ancillas.extend(register)
+                for bit in register:
+                    if bit not in self._qubit_indices:
+                        self._ancillas.append(bit)
 
             if isinstance(register, QuantumRegister):
                 self.qregs.append(register)
diff --git a/releasenotes/notes/fix-adding-ancilla-register-without-checking-abe367dab5a63dbb.yaml b/releasenotes/notes/fix-adding-ancilla-register-without-checking-abe367dab5a63dbb.yaml
new file mode 100644
index 000000000000..08a997a1fae2
--- /dev/null
+++ b/releasenotes/notes/fix-adding-ancilla-register-without-checking-abe367dab5a63dbb.yaml
@@ -0,0 +1,6 @@
+---
+fixes:
+  - |
+    :meth:`.QuantumCircuit.add_register` will no longer cause duplicate
+    :class:`.AncillaQubit` references in a circuit when given an
+    :class:`.AncillaRegister` whose bits are already present.
diff --git a/test/python/circuit/test_circuit_operations.py b/test/python/circuit/test_circuit_operations.py
index 3f0a36a398db..b5e12c25f697 100644
--- a/test/python/circuit/test_circuit_operations.py
+++ b/test/python/circuit/test_circuit_operations.py
@@ -22,6 +22,7 @@
 from qiskit.circuit.classicalregister import Clbit
 from qiskit.circuit.exceptions import CircuitError
 from qiskit.circuit.quantumcircuit import BitLocations
+from qiskit.circuit.quantumregister import AncillaQubit, AncillaRegister, Qubit
 from qiskit.test import QiskitTestCase
 from qiskit.circuit.library.standard_gates import SGate
 from qiskit.quantum_info import Operator
@@ -948,6 +949,41 @@ def test_compare_a_circuit_with_none(self):
 
         self.assertFalse(qc1 == qc2)
 
+    def test_overlapped_add_bits_and_add_register(self):
+        """Test add registers whose bits have already been added by add_bits."""
+        qc = QuantumCircuit()
+        for bit_type, reg_type in (
+            [Qubit, QuantumRegister],
+            [Clbit, ClassicalRegister],
+            [AncillaQubit, AncillaRegister],
+        ):
+            bits = [bit_type() for _ in range(10)]
+            reg = reg_type(bits=bits)
+            qc.add_bits(bits)
+            qc.add_register(reg)
+
+        self.assertEqual(qc.num_qubits, 20)
+        self.assertEqual(qc.num_clbits, 10)
+        self.assertEqual(qc.num_ancillas, 10)
+
+    def test_overlapped_add_register_and_add_register(self):
+        """Test add registers whose bits have already been added by add_register."""
+        qc = QuantumCircuit()
+        for bit_type, reg_type in (
+            [Qubit, QuantumRegister],
+            [Clbit, ClassicalRegister],
+            [AncillaQubit, AncillaRegister],
+        ):
+            bits = [bit_type() for _ in range(10)]
+            reg1 = reg_type(bits=bits)
+            reg2 = reg_type(bits=bits)
+            qc.add_register(reg1)
+            qc.add_register(reg2)
+
+        self.assertEqual(qc.num_qubits, 20)
+        self.assertEqual(qc.num_clbits, 10)
+        self.assertEqual(qc.num_ancillas, 10)
+
     def test_deprecated_measure_function(self):
         """Test that the deprecated version of the loose 'measure' function works correctly."""
         from qiskit.circuit.measure import measure