From 27f42ded39e92fb4f52d94fa5eb8600f314a5f48 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?S=C3=B6ren=20Tempel?= Date: Mon, 17 Feb 2020 09:37:26 +0100 Subject: [PATCH] Make sure the mpu_noexec_ram regions has the lowest priority From the ARMv7-M ARM section B3.5.3: Where there is an overlap between two regions, the register with the highest region number takes priority. We want to make sure the mpu_noexec_ram region has the lowest priority to allow the mpu_stack_guard region to overwrite the first N bytes of it. This change fixes using mpu_noexec_ram and mpu_stack_guard together. --- core/sched.c | 2 +- cpu/cortexm_common/vectors_cortexm.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/core/sched.c b/core/sched.c index e307d7dffd4e0..52a32c1dbe20e 100644 --- a/core/sched.c +++ b/core/sched.c @@ -121,7 +121,7 @@ int __attribute__((used)) sched_run(void) #ifdef MODULE_MPU_STACK_GUARD mpu_configure( - 1, /* MPU region 1 */ + 2, /* MPU region 2 */ (uintptr_t)sched_active_thread->stack_start + 31, /* Base Address (rounded up) */ MPU_ATTR(1, AP_RO_RO, 0, 1, 0, 1, MPU_SIZE_32B) /* Attributes and Size */ ); diff --git a/cpu/cortexm_common/vectors_cortexm.c b/cpu/cortexm_common/vectors_cortexm.c index 6e9401fa865b6..a81162ccfc7bc 100644 --- a/cpu/cortexm_common/vectors_cortexm.c +++ b/cpu/cortexm_common/vectors_cortexm.c @@ -152,7 +152,7 @@ void reset_handler_default(void) * executable. This is the Cortex-M SRAM region used for on-chip RAM. */ mpu_configure( - 2, /* Region 0 and 1 are used by mpu_stack_guard */ + 0, /* Region 0 (lowest priority) */ (uintptr_t)&_sram, /* RAM base address */ MPU_ATTR(1, AP_RW_RW, 0, 1, 0, 1, MPU_SIZE_512M) /* Allow read/write but no exec */ ); @@ -161,7 +161,7 @@ void reset_handler_default(void) #ifdef MODULE_MPU_STACK_GUARD if (((uintptr_t)&_sstack) != SRAM_BASE) { mpu_configure( - 0, /* MPU region 0 */ + 1, /* MPU region 1 */ (uintptr_t)&_sstack + 31, /* Base Address (rounded up) */ MPU_ATTR(1, AP_RO_RO, 0, 1, 0, 1, MPU_SIZE_32B) /* Attributes and Size */ );