diff --git a/groups/GNR/MEM.txt b/groups/GNR/MEM.txt new file mode 100644 index 000000000..ff44c290b --- /dev/null +++ b/groups/GNR/MEM.txt @@ -0,0 +1,99 @@ +SHORT Memory bandwidth in MBytes/s + +EVENTSET +FIXC0 INSTR_RETIRED_ANY +FIXC1 CPU_CLK_UNHALTED_CORE +FIXC2 CPU_CLK_UNHALTED_REF +FIXC3 TOPDOWN_SLOTS +MBOX0C0 CAS_COUNT_SCH0_RD +MBOX0C1 CAS_COUNT_SCH0_WR +MBOX0C2 CAS_COUNT_SCH1_RD +MBOX0C3 CAS_COUNT_SCH1_WR +MBOX1C0 CAS_COUNT_SCH0_RD +MBOX1C1 CAS_COUNT_SCH0_WR +MBOX1C2 CAS_COUNT_SCH1_RD +MBOX1C3 CAS_COUNT_SCH1_WR +MBOX2C0 CAS_COUNT_SCH0_RD +MBOX2C1 CAS_COUNT_SCH0_WR +MBOX2C2 CAS_COUNT_SCH1_RD +MBOX2C3 CAS_COUNT_SCH1_WR +MBOX3C0 CAS_COUNT_SCH0_RD +MBOX3C1 CAS_COUNT_SCH0_WR +MBOX3C2 CAS_COUNT_SCH1_RD +MBOX3C3 CAS_COUNT_SCH1_WR +MBOX4C0 CAS_COUNT_SCH0_RD +MBOX4C1 CAS_COUNT_SCH0_WR +MBOX4C2 CAS_COUNT_SCH1_RD +MBOX4C3 CAS_COUNT_SCH1_WR +MBOX5C0 CAS_COUNT_SCH0_RD +MBOX5C1 CAS_COUNT_SCH0_WR +MBOX5C2 CAS_COUNT_SCH1_RD +MBOX5C3 CAS_COUNT_SCH1_WR +MBOX6C0 CAS_COUNT_SCH0_RD +MBOX6C1 CAS_COUNT_SCH0_WR +MBOX6C2 CAS_COUNT_SCH1_RD +MBOX6C3 CAS_COUNT_SCH1_WR +MBOX7C0 CAS_COUNT_SCH0_RD +MBOX7C1 CAS_COUNT_SCH0_WR +MBOX7C2 CAS_COUNT_SCH1_RD +MBOX7C3 CAS_COUNT_SCH1_WR +MBOX8C0 CAS_COUNT_SCH0_RD +MBOX8C1 CAS_COUNT_SCH0_WR +MBOX8C2 CAS_COUNT_SCH1_RD +MBOX8C3 CAS_COUNT_SCH1_WR +MBOX9C0 CAS_COUNT_SCH0_RD +MBOX9C1 CAS_COUNT_SCH0_WR +MBOX9C2 CAS_COUNT_SCH1_RD +MBOX9C3 CAS_COUNT_SCH1_WR +MBOX10C0 CAS_COUNT_SCH0_RD +MBOX10C1 CAS_COUNT_SCH0_WR +MBOX10C2 CAS_COUNT_SCH1_RD +MBOX10C3 CAS_COUNT_SCH1_WR +MBOX11C0 CAS_COUNT_SCH0_RD +MBOX11C1 CAS_COUNT_SCH0_WR +MBOX11C2 CAS_COUNT_SCH1_RD +MBOX11C3 CAS_COUNT_SCH1_WR +MBOX12C0 CAS_COUNT_SCH0_RD +MBOX12C1 CAS_COUNT_SCH0_WR +MBOX12C2 CAS_COUNT_SCH1_RD +MBOX12C3 CAS_COUNT_SCH1_WR +MBOX13C0 CAS_COUNT_SCH0_RD +MBOX13C1 CAS_COUNT_SCH0_WR +MBOX13C2 CAS_COUNT_SCH1_RD +MBOX13C3 CAS_COUNT_SCH1_WR +MBOX14C0 CAS_COUNT_SCH0_RD +MBOX14C1 CAS_COUNT_SCH0_WR +MBOX14C2 CAS_COUNT_SCH1_RD +MBOX14C3 CAS_COUNT_SCH1_WR +MBOX15C0 CAS_COUNT_SCH0_RD +MBOX15C1 CAS_COUNT_SCH0_WR +MBOX15C2 CAS_COUNT_SCH1_RD +MBOX15C3 CAS_COUNT_SCH1_WR + + +METRICS +Runtime (RDTSC) [s] time +Runtime unhalted [s] FIXC1*inverseClock +Clock [MHz] 1.E-06*(FIXC1/FIXC2)/inverseClock +CPI FIXC1/FIXC0 +Memory read bandwidth [MBytes/s] 1.0E-06*(MBOX0C0+MBOX0C2+MBOX1C0+MBOX1C2+MBOX2C0+MBOX2C2+MBOX3C0+MBOX3C2+MBOX4C0+MBOX4C2+MBOX5C0+MBOX5C2+MBOX6C0+MBOX6C2+MBOX7C0+MBOX7C2+MBOX8C0+MBOX8C2+MBOX9C0+MBOX9C2+MBOX10C0+MBOX10C2+MBOX11C0+MBOX11C2+MBOX12C0+MBOX12C2+MBOX13C0+MBOX13C2+MBOX14C0+MBOX14C2+MBOX15C0+MBOX15C2)*64.0/time +Memory read data volume [GBytes] 1.0E-09*(MBOX0C0+MBOX0C2+MBOX1C0+MBOX1C2+MBOX2C0+MBOX2C2+MBOX3C0+MBOX3C2+MBOX4C0+MBOX4C2+MBOX5C0+MBOX5C2+MBOX6C0+MBOX6C2+MBOX7C0+MBOX7C2+MBOX8C0+MBOX8C2+MBOX9C0+MBOX9C2+MBOX10C0+MBOX10C2+MBOX11C0+MBOX11C2+MBOX12C0+MBOX12C2+MBOX13C0+MBOX13C2+MBOX14C0+MBOX14C2+MBOX15C0+MBOX15C2)*64.0 +Memory write bandwidth [MBytes/s] 1.0E-06*(MBOX0C1+MBOX0C3+MBOX1C1+MBOX1C3+MBOX2C1+MBOX2C3+MBOX3C1+MBOX3C3+MBOX4C1+MBOX4C3+MBOX5C1+MBOX5C3+MBOX6C1+MBOX6C3+MBOX7C1+MBOX7C3+MBOX8C1+MBOX8C3+MBOX9C1+MBOX9C3+MBOX10C1+MBOX10C3+MBOX11C1+MBOX11C3+MBOX12C1+MBOX12C3+MBOX13C1+MBOX13C3+MBOX14C1+MBOX14C3+MBOX15C1+MBOX15C3)*64.0/time +Memory write data volume [GBytes] 1.0E-09*(MBOX0C1+MBOX0C3+MBOX1C1+MBOX1C3+MBOX2C1+MBOX2C3+MBOX3C1+MBOX3C3+MBOX4C1+MBOX4C3+MBOX5C1+MBOX5C3+MBOX6C1+MBOX6C3+MBOX7C1+MBOX7C3+MBOX8C1+MBOX8C3+MBOX9C1+MBOX9C3+MBOX10C1+MBOX10C3+MBOX11C1+MBOX11C3+MBOX12C1+MBOX12C3+MBOX13C1+MBOX13C3+MBOX14C1+MBOX14C3+MBOX15C1+MBOX15C3)*64.0 +Memory bandwidth [MBytes/s] 1.0E-06*(MBOX0C0+MBOX0C2+MBOX1C0+MBOX1C2+MBOX2C0+MBOX2C2+MBOX3C0+MBOX3C2+MBOX4C0+MBOX4C2+MBOX5C0+MBOX5C2+MBOX6C0+MBOX6C2+MBOX7C0+MBOX7C2+MBOX8C0+MBOX8C2+MBOX9C0+MBOX9C2+MBOX10C0+MBOX10C2+MBOX11C0+MBOX11C2+MBOX12C0+MBOX12C2+MBOX13C0+MBOX13C2+MBOX14C0+MBOX14C2+MBOX15C0+MBOX15C2+MBOX0C1+MBOX0C3+MBOX1C1+MBOX1C3+MBOX2C1+MBOX2C3+MBOX3C1+MBOX3C3+MBOX4C1+MBOX4C3+MBOX5C1+MBOX5C3+MBOX6C1+MBOX6C3+MBOX7C1+MBOX7C3+MBOX8C1+MBOX8C3+MBOX9C1+MBOX9C3+MBOX10C1+MBOX10C3+MBOX11C1+MBOX11C3+MBOX12C1+MBOX12C3+MBOX13C1+MBOX13C3+MBOX14C1+MBOX14C3+MBOX15C1+MBOX15C3)*64.0/time +Memory data volume [GBytes] 1.0E-09*(MBOX0C0+MBOX0C2+MBOX1C0+MBOX1C2+MBOX2C0+MBOX2C2+MBOX3C0+MBOX3C2+MBOX4C0+MBOX4C2+MBOX5C0+MBOX5C2+MBOX6C0+MBOX6C2+MBOX7C0+MBOX7C2+MBOX8C0+MBOX8C2+MBOX9C0+MBOX9C2+MBOX10C0+MBOX10C2+MBOX11C0+MBOX11C2+MBOX12C0+MBOX12C2+MBOX13C0+MBOX13C2+MBOX14C0+MBOX14C2+MBOX15C0+MBOX15C2+MBOX0C1+MBOX0C3+MBOX1C1+MBOX1C3+MBOX2C1+MBOX2C3+MBOX3C1+MBOX3C3+MBOX4C1+MBOX4C3+MBOX5C1+MBOX5C3+MBOX6C1+MBOX6C3+MBOX7C1+MBOX7C3+MBOX8C1+MBOX8C3+MBOX9C1+MBOX9C3+MBOX10C1+MBOX10C3+MBOX11C1+MBOX11C3+MBOX12C1+MBOX12C3+MBOX13C1+MBOX13C3+MBOX14C1+MBOX14C3+MBOX15C1+MBOX15C3)*64.0 + +LONG +Formulas: +Memory read bandwidth [MBytes/s] = 1.0E-06*(SUM(CAS_COUNT_SCH0_RD)+SUM(CAS_COUNT_SCH1_RD))*64.0/runtime +Memory read data volume [GBytes] = 1.0E-09*(SUM(CAS_COUNT_SCH0_RD)+SUM(CAS_COUNT_SCH1_RD))*64.0 +Memory write bandwidth [MBytes/s] = 1.0E-06*(SUM(CAS_COUNT_SCH0_WR)+SUM(CAS_COUNT_SCH1_WR))*64.0/runtime +Memory write data volume [GBytes] = 1.0E-09*(SUM(CAS_COUNT_SCH0_WR)+SUM(CAS_COUNT_SCH1_WR))*64.0 +Memory bandwidth [MBytes/s] = 1.0E-06*(SUM(CAS_COUNT_SCH0_RD)+SUM(CAS_COUNT_SCH1_RD)+SUM(CAS_COUNT_SCH0_WR)+SUM(CAS_COUNT_SCH1_WR))*64.0/runtime +Memory data volume [GBytes] = 1.0E-09*(SUM(CAS_COUNT_SCH0_RD)+SUM(CAS_COUNT_SCH1_RD)+SUM(CAS_COUNT_SCH0_WR)+SUM(CAS_COUNT_SCH1_WR))*64.0 +-- +Profiling group to measure memory bandwidth drawn by all cores of a socket. +Since this group is based on Uncore events it is only possible to measure on a +per socket base. Some of the counters may not be available on your system. +Also outputs total data volume transferred from main memory. + diff --git a/src/access-daemon/accessDaemon.c b/src/access-daemon/accessDaemon.c index 50d569477..beed540cc 100644 --- a/src/access-daemon/accessDaemon.c +++ b/src/access-daemon/accessDaemon.c @@ -64,6 +64,8 @@ #include #include #include +#include +#include #include #include #include @@ -3110,7 +3112,8 @@ static void spr_read_unit(AccessDataRecord *record) { case ACCESS_TYPE_MMIO: if ((record->device >= MMIO_IMC_DEVICE_0_CH_0 && record->device <= MMIO_IMC_DEVICE_1_CH_7) || - (record->device >= MMIO_HBM_DEVICE_0 && record->device <= MMIO_HBM_DEVICE_31)) + (record->device >= MMIO_HBM_DEVICE_0 && record->device <= MMIO_HBM_DEVICE_31) || + (record->device >= PCI_R2PCIE_DEVICE0 && record->device <= PCI_R2PCIE_DEVICE31)) { record->data = (uint32_t)*((uint32_t *)(unit->io_addr + unit->mmap_offset + unit->ctrl_offset + (sizeof(uint32_t) * offset))); } @@ -3370,7 +3373,8 @@ static void spr_write_unit(AccessDataRecord *record) { case ACCESS_TYPE_MMIO: if ((record->device >= MMIO_IMC_DEVICE_0_CH_0 && record->device <= MMIO_IMC_DEVICE_1_CH_7) || - (record->device >= MMIO_HBM_DEVICE_0 && record->device <= MMIO_HBM_DEVICE_31)) + (record->device >= MMIO_HBM_DEVICE_0 && record->device <= MMIO_HBM_DEVICE_31) || + (record->device >= PCI_R2PCIE_DEVICE0 && record->device <= PCI_R2PCIE_DEVICE31)) { *((uint32_t *)(unit->io_addr + unit->mmap_offset + unit->ctrl_offset + (sizeof(uint32_t) * offset))) = (uint32_t)record->data; } @@ -3484,7 +3488,7 @@ static void spr_write_unit(AccessDataRecord *record) static void spr_read(AccessDataRecord *record) { - if (record->device == MSR_UBOX_DEVICE && ((record->reg == FAKE_UNC_GLOBAL_CTRL) || ((record->reg >= FAKE_UNC_GLOBAL_STATUS0) && (record->reg <= FAKE_UNC_GLOBAL_STATUS3)))) + if (record->device == MSR_UBOX_DEVICE && ((record->reg == FAKE_UNC_GLOBAL_CTRL) || ((record->reg >= FAKE_UNC_GLOBAL_STATUS0) && (record->reg <= FAKE_UNC_GLOBAL_STATUS8)))) { spr_read_global(record); } @@ -3496,7 +3500,7 @@ static void spr_read(AccessDataRecord *record) static void spr_write(AccessDataRecord *record) { - if (record->device == MSR_UBOX_DEVICE && ((record->reg == FAKE_UNC_GLOBAL_CTRL) || ((record->reg >= FAKE_UNC_GLOBAL_STATUS0) && (record->reg <= FAKE_UNC_GLOBAL_STATUS3)))) + if (record->device == MSR_UBOX_DEVICE && ((record->reg == FAKE_UNC_GLOBAL_CTRL) || ((record->reg >= FAKE_UNC_GLOBAL_STATUS0) && (record->reg <= FAKE_UNC_GLOBAL_STATUS8)))) { spr_write_global(record); } @@ -3696,6 +3700,22 @@ int main(void) allowedPci = allowed_pci_spr; isIntelUncoreDiscovery = 1; } + else if (model == GRANITERAPIDS) + { + isPCIUncore = 1; + allowed = allowed_spr; + isPCI64 = 1; + allowedPci = allowed_pci_spr; + isIntelUncoreDiscovery = 1; + } + else if (model == SIERRAFORREST) + { + isPCIUncore = 1; + allowed = allowed_spr; + isPCI64 = 1; + allowedPci = allowed_pci_spr; + isIntelUncoreDiscovery = 1; + } else if ((model == ATOM_SILVERMONT_C) || (model == ATOM_SILVERMONT_E) || (model == ATOM_SILVERMONT_Z1) || @@ -3712,11 +3732,6 @@ int main(void) isPCIUncore = 1; allowedPci = allowed_pci_knl; } - else if (model == SAPPHIRERAPIDS) - { - allowed = allowed_icx; - isPCI64 = 1; - } break; case K8_FAMILY: case K10_FAMILY: @@ -3903,7 +3918,7 @@ int main(void) else if (isIntelUncoreDiscovery) { pci_devices_daemon = NULL; - int err = perfmon_uncore_discovery(&perfmon_discovery); + int err = perfmon_uncore_discovery(model, &perfmon_discovery); if (err < 0) { syslog(LOG_ERR, "Failed to run uncore discovery"); diff --git a/src/access_x86.c b/src/access_x86.c index 05b56062b..63c4c4114 100644 --- a/src/access_x86.c +++ b/src/access_x86.c @@ -50,6 +50,8 @@ #include #include +#define ARCH_SPR_GNR_SRF ((cpuid_info.family == P6_FAMILY) && (cpuid_info.model == SAPPHIRERAPIDS || cpuid_info.model == GRANITERAPIDS || cpuid_info.model == SIERRAFORREST)) + /* ##### FUNCTION DEFINITIONS - EXPORTED FUNCTIONS ################## */ int @@ -60,7 +62,7 @@ access_x86_init(int cpu_id) { if (cpuid_info.supportUncore) { - if (!((cpuid_info.family == P6_FAMILY) && (cpuid_info.model == SAPPHIRERAPIDS))) + if (!(ARCH_SPR_GNR_SRF)) { ret = access_x86_pci_init(affinity_thread2socket_lookup[cpu_id]); } @@ -72,7 +74,7 @@ access_x86_init(int cpu_id) ERROR_PRINT(Initialization of MMIO access failed); } } - else if ((cpuid_info.family == P6_FAMILY) && (cpuid_info.model == SAPPHIRERAPIDS)) + else if (ARCH_SPR_GNR_SRF) { ret = access_x86_translate_init(cpu_id); } @@ -109,7 +111,7 @@ access_x86_read(PciDeviceIndex dev, const int cpu_id, uint32_t reg, uint64_t *da *data = tmp; } } - else if ((cpuid_info.family == P6_FAMILY) && (cpuid_info.model == SAPPHIRERAPIDS)) + else if (ARCH_SPR_GNR_SRF) { if (access_x86_translate_check(dev, cpu_id)) { @@ -158,7 +160,7 @@ access_x86_write(PciDeviceIndex dev, const int cpu_id, uint32_t reg, uint64_t da err = access_x86_mmio_write(dev, affinity_thread2socket_lookup[cpu_id], reg, data); } } - else if ((cpuid_info.family == P6_FAMILY) && (cpuid_info.model == SAPPHIRERAPIDS)) + else if (ARCH_SPR_GNR_SRF) { if (access_x86_translate_check(dev, cpu_id)) { @@ -198,7 +200,7 @@ access_x86_finalize(int cpu_id) DEBUG_PRINT(DEBUGLEV_DEVELOP, Finalize of MMIO access); access_x86_mmio_finalize(affinity_thread2socket_lookup[cpu_id]); } - else if ((cpuid_info.family == P6_FAMILY) && (cpuid_info.model == SAPPHIRERAPIDS)) + else if (ARCH_SPR_GNR_SRF) { DEBUG_PRINT(DEBUGLEV_DEVELOP, Finalize of Fake access); access_x86_translate_finalize(cpu_id); @@ -227,7 +229,7 @@ access_x86_check(PciDeviceIndex dev, int cpu_id) { return access_x86_mmio_check(dev, affinity_thread2socket_lookup[cpu_id]); } - else if ((cpuid_info.family == P6_FAMILY) && (cpuid_info.model == SAPPHIRERAPIDS)) + else if (ARCH_SPR_GNR_SRF) { return access_x86_translate_check(dev, cpu_id); } diff --git a/src/access_x86_translate.c b/src/access_x86_translate.c index 270641819..a1fed85e2 100644 --- a/src/access_x86_translate.c +++ b/src/access_x86_translate.c @@ -73,6 +73,7 @@ int access_x86_translate_open_unit(PerfmonDiscoveryUnit* unit) } if (unit->access_type == ACCESS_TYPE_MMIO) { + DEBUG_PRINT(DEBUGLEV_DEVELOP, Opening /dev/mem at 0x%X, unit->mmap_addr); void* io_addr = mmap(NULL, unit->mmap_size, PROT_READ|PROT_WRITE, MAP_SHARED, pcihandle, unit->mmap_addr); if (io_addr == MAP_FAILED) { @@ -81,10 +82,12 @@ int access_x86_translate_open_unit(PerfmonDiscoveryUnit* unit) ERROR_PRINT(Failed to mmap offset 0x%lX (MMIO), unit->box_ctl); return -err; } + DEBUG_PRINT(DEBUGLEV_DEVELOP, Opening /dev/mem at 0x%X -> 0x%X, unit->mmap_addr, io_addr); unit->io_addr = io_addr; } else if (unit->access_type == ACCESS_TYPE_PCI) { + DEBUG_PRINT(DEBUGLEV_DEVELOP, Opening /dev/mem at 0x%X, unit->mmap_addr); void* io_addr = mmap(NULL, unit->mmap_size, PROT_READ|PROT_WRITE, MAP_SHARED, pcihandle, unit->mmap_addr ); if (io_addr == MAP_FAILED) { @@ -141,7 +144,7 @@ access_x86_translate_init(const int cpu_id) if (!perfmon_discovery) { DEBUG_PLAIN_PRINT(DEBUGLEV_DEVELOP, Running Perfmon Discovery to populate counter lists); - int ret = perfmon_uncore_discovery(&perfmon_discovery); + int ret = perfmon_uncore_discovery(cpuid_info.model, &perfmon_discovery); if (ret != 0) { ERROR_PRINT(Failed to run Perfmon Discovery); @@ -173,7 +176,7 @@ access_x86_translate_read(PciDeviceIndex dev, const int cpu_id, uint32_t reg, ui { newreg = cur->global.global_ctl; } - else if ((reg >= FAKE_UNC_GLOBAL_STATUS0) && (reg <= FAKE_UNC_GLOBAL_STATUS3)) + else if ((reg >= FAKE_UNC_GLOBAL_STATUS0) && (reg <= FAKE_UNC_GLOBAL_STATUS8)) { newreg = cur->global.global_ctl + cur->global.status_offset + ((reg - FAKE_UNC_GLOBAL_STATUS0)); } @@ -206,7 +209,7 @@ access_x86_translate_read(PciDeviceIndex dev, const int cpu_id, uint32_t reg, ui ERROR_PRINT(Failed to find unit %s, pci_device_names[dev]); return -ENODEV; } - DEBUG_PRINT(DEBUGLEV_DEVELOP, Read Uncore counter 0x%X (%s) on CPU %d (socket %d), reg, pci_device_names[dev], cpu_id, socket_id); + DEBUG_PRINT(DEBUGLEV_DEVELOP, Read Uncore counter 0x%X (%s) on CPU %d (socket %d, access %s), reg, pci_device_names[dev], cpu_id, socket_id, AccessTypeNames[unit->access_type]); switch(reg) { case FAKE_UNC_UNIT_CTRL: @@ -275,10 +278,12 @@ access_x86_translate_read(PciDeviceIndex dev, const int cpu_id, uint32_t reg, ui if ((dev >= MMIO_IMC_DEVICE_0_CH_0 && dev <= MMIO_IMC_DEVICE_1_CH_7) || (dev >= MMIO_HBM_DEVICE_0 && dev <= MMIO_HBM_DEVICE_31)) { + DEBUG_PRINT(DEBUGLEV_DEVELOP, 0x%X + 0x%X + 0x%X + (%d * %d), unit->io_addr, unit->mmap_offset, unit->ctrl_offset, sizeof(uint32_t), offset); *data = (uint32_t)*((uint32_t *)(unit->io_addr + unit->mmap_offset + unit->ctrl_offset + (sizeof(uint32_t) * offset))); } else { + DEBUG_PRINT(DEBUGLEV_DEVELOP, 0x%X + 0x%X + 0x%X + (%d * %d), unit->io_addr, unit->mmap_offset, unit->ctrl_offset, reg_offset, offset); *data = (uint64_t)*((uint64_t *)(unit->io_addr + unit->mmap_offset + unit->ctrl_offset + (reg_offset * offset))); } break; @@ -319,7 +324,6 @@ access_x86_translate_read(PciDeviceIndex dev, const int cpu_id, uint32_t reg, ui (dev >= PCI_R3QPI_DEVICE_LINK_0 && dev <= PCI_R3QPI_DEVICE_LINK_3) || (dev >= PCI_QPI_DEVICE_PORT_0 && dev <= PCI_QPI_DEVICE_PORT_3)) { - uint32_t lo = 0ULL, hi = 0ULL; lo = (uint32_t)*((uint32_t *)(unit->io_addr + unit->mmap_offset + unit->ctr_offset + (sizeof(uint32_t) * offset))); hi = (uint32_t)*((uint32_t *)(unit->io_addr + unit->mmap_offset + unit->ctr_offset + (sizeof(uint32_t) * offset) + sizeof(uint32_t))); @@ -399,7 +403,7 @@ access_x86_translate_write(PciDeviceIndex dev, const int cpu_id, uint32_t reg, u { newreg = cur->global.global_ctl; } - else if ((reg >= FAKE_UNC_GLOBAL_STATUS0) && (reg <= FAKE_UNC_GLOBAL_STATUS3)) + else if ((reg >= FAKE_UNC_GLOBAL_STATUS0) && (reg <= FAKE_UNC_GLOBAL_STATUS8)) { newreg = cur->global.global_ctl + cur->global.status_offset + ((reg - FAKE_UNC_GLOBAL_STATUS0)); } @@ -431,7 +435,7 @@ access_x86_translate_write(PciDeviceIndex dev, const int cpu_id, uint32_t reg, u ERROR_PRINT(Failed to find unit %s, pci_device_names[dev]); return -ENODEV; } - DEBUG_PRINT(DEBUGLEV_DEVELOP, Write Uncore counter 0x%X (%s) on CPU %d (socket %d): 0x%lX, reg, pci_device_names[dev], cpu_id, socket_id, data); + DEBUG_PRINT(DEBUGLEV_DEVELOP, Write Uncore counter 0x%X (%s) on CPU %d (socket %d, access %s): 0x%lX, reg, pci_device_names[dev], cpu_id, socket_id, AccessTypeNames[unit->access_type], data); switch(reg) { case FAKE_UNC_UNIT_CTRL: @@ -497,10 +501,12 @@ access_x86_translate_write(PciDeviceIndex dev, const int cpu_id, uint32_t reg, u if ((dev >= MMIO_IMC_DEVICE_0_CH_0 && dev <= MMIO_IMC_DEVICE_1_CH_7) || (dev >= MMIO_HBM_DEVICE_0 && dev <= MMIO_HBM_DEVICE_31)) { + DEBUG_PRINT(DEBUGLEV_DEVELOP, 0x%X + 0x%X + 0x%X + (%d * %d) = 0x%X, unit->io_addr, unit->mmap_offset, unit->ctrl_offset, sizeof(uint32_t), offset, (uint32_t)data); *((uint32_t *)(unit->io_addr + unit->mmap_offset + unit->ctrl_offset + (sizeof(uint32_t) * offset))) = (uint32_t)data; } else { + DEBUG_PRINT(DEBUGLEV_DEVELOP, 0x%X + 0x%X + 0x%X + (%d * %d) = 0x%X, unit->io_addr, unit->mmap_offset, unit->ctrl_offset, reg_offset, offset, (uint64_t)data); *((uint64_t *)(unit->io_addr + unit->mmap_offset + unit->ctrl_offset + (reg_offset * offset))) = (uint64_t)data; } break; @@ -612,14 +618,21 @@ access_x86_translate_check(PciDeviceIndex dev, int cpu_id) return 0; } int socket_id = affinity_thread2socket_lookup[cpu_id]; - PerfmonDiscoverySocket* cur = &perfmon_discovery->sockets[socket_id]; - if (cur->units && cur->socket_id == socket_id && cur->units[dev].num_regs > 0) + if (socket_id < 0) { - return 1; + return 0; } - if (dev == MSR_UBOX_DEVICE && cur->units) + PerfmonDiscoverySocket* cur = &perfmon_discovery->sockets[socket_id]; + if (cur) { - return 1; + if (cur->units && cur->socket_id == socket_id && cur->units[dev].num_regs > 0) + { + return 1; + } + if (dev == MSR_UBOX_DEVICE && cur->units) + { + return 1; + } } return 0; } diff --git a/src/cpuFeatures.c b/src/cpuFeatures.c index e68f0cda0..820197f99 100644 --- a/src/cpuFeatures.c +++ b/src/cpuFeatures.c @@ -385,6 +385,8 @@ cpuFeatures_enable(int cpu, CpuFeature type, int print) (cpuid_info.model == ICELAKE1) || (cpuid_info.model == ICELAKE2) || (cpuid_info.model == SAPPHIRERAPIDS) || + (cpuid_info.model == GRANITERAPIDS) || + (cpuid_info.model == SIERRAFORREST) || (cpuid_info.model == ROCKETLAKE) || (cpuid_info.model == ICELAKEX1) || (cpuid_info.model == ICELAKEX2) || @@ -550,6 +552,8 @@ cpuFeatures_disable(int cpu, CpuFeature type, int print) (cpuid_info.model == ICELAKE1) || (cpuid_info.model == ICELAKE2) || (cpuid_info.model == SAPPHIRERAPIDS) || + (cpuid_info.model == GRANITERAPIDS) || + (cpuid_info.model == SIERRAFORREST) || (cpuid_info.model == ROCKETLAKE) || (cpuid_info.model == ICELAKEX1) || (cpuid_info.model == ICELAKEX2) || diff --git a/src/includes/intel_perfmon_uncore_discovery.h b/src/includes/intel_perfmon_uncore_discovery.h index c4b0417f8..ee1ecaddf 100644 --- a/src/includes/intel_perfmon_uncore_discovery.h +++ b/src/includes/intel_perfmon_uncore_discovery.h @@ -1,7 +1,16 @@ #ifndef INTEL_PERFMON_UNCORE_DISCOVERY_H #define INTEL_PERFMON_UNCORE_DISCOVERY_H +#include +#include +#include +#include +#include + // Data structures provided by Intel +typedef uint64_t u64; +typedef uint32_t u32; +typedef uint16_t u16; #define PCI_EXT_CAP_BASE_OFFSET 0x100 #define PCI_EXT_CAP_ID_MASK 0xffff @@ -39,6 +48,7 @@ #define UNCORE_DISCOVERY_PCI_BOX_CTRL(data) (data & 0xfff) #define PCI_ANY_ID (-1) +#define PCI_VENDOR_ID_INTEL 0x8086 #define uncore_discovery_invalid_unit(unit) \ (!unit.table1 || \ @@ -48,27 +58,27 @@ struct uncore_global_discovery { union { - uint64_t table1; + u64 table1; struct { - uint64_t type : 8; - uint64_t stride : 8; - uint64_t max_units : 10; - uint64_t __reserved_1 : 36; - uint64_t access_type : 2; + u64 type : 8; + u64 stride : 8; + u64 max_units : 10; + u64 __reserved_1 : 36; + u64 access_type : 2; }; }; union { - uint64_t table2; - uint64_t global_ctl; + u64 table2; + u64 global_ctl; }; union { - uint64_t table3; + u64 table3; struct { - uint64_t status_offset : 8; - uint64_t num_status : 16; - uint64_t __reserved_2 : 40; + u64 status_offset : 8; + u64 num_status : 16; + u64 __reserved_2 : 40; }; }; }; @@ -76,68 +86,32 @@ struct uncore_global_discovery { struct uncore_unit_discovery { union { - uint64_t table1; + u64 table1; struct { - uint64_t num_regs : 8; - uint64_t ctl_offset : 8; - uint64_t bit_width : 8; - uint64_t ctr_offset : 8; - uint64_t status_offset : 8; - uint64_t __reserved_1 : 22; - uint64_t access_type : 2; + u64 num_regs : 8; + u64 ctl_offset : 8; + u64 bit_width : 8; + u64 ctr_offset : 8; + u64 status_offset : 8; + u64 __reserved_1 : 22; + u64 access_type : 2; }; }; union { - uint64_t table2; - uint64_t box_ctl; + u64 table2; + u64 box_ctl; }; union { - uint64_t table3; + u64 table3; struct { - uint64_t box_type : 16; - uint64_t box_id : 16; - uint64_t __reserved_2 : 32; + u64 box_type : 16; + u64 box_id : 16; + u64 global_status_position : 16; + u64 __reserved_2 : 16; }; }; }; -typedef enum { - DEVICE_ID_CHA = 0, - DEVICE_ID_IIO = 1, - DEVICE_ID_IRP = 2, - DEVICE_ID_M2PCIe = 3, - DEVICE_ID_PCU = 4, - DEVICE_ID_5_UNKNOWN = 5, - DEVICE_ID_iMC = 6, - DEVICE_ID_M2M = 7, - DEVICE_ID_UPI = 8, - DEVICE_ID_M3UPI = 9, - DEVICE_ID_10_UNKNOWN = 10, - DEVICE_ID_MDF = 11, - DEVICE_ID_12_UNKNOWN = 12, - DEVICE_ID_13_UNKNOWN = 13, - DEVICE_ID_HBM = 14, - DEVICE_ID_MAX, -} uncore_discovery_box_types; - -static char* uncore_discovery_box_type_names[DEVICE_ID_MAX] = { - [DEVICE_ID_CHA] = "CBOX", - [DEVICE_ID_IIO] = "IIO", - [DEVICE_ID_IRP] = "IRP", - [DEVICE_ID_M2PCIe] = "PBOX", - [DEVICE_ID_PCU] = "WBOX", - [DEVICE_ID_5_UNKNOWN] = "UNKNOWN", - [DEVICE_ID_iMC] = "MBOX", - [DEVICE_ID_M2M] = "M2M", - [DEVICE_ID_UPI] = "QBOX", - [DEVICE_ID_M3UPI] = "RBOX", - [DEVICE_ID_10_UNKNOWN] = "UNKNOWN", - [DEVICE_ID_MDF] = "MDF", - [DEVICE_ID_12_UNKNOWN] = "UNKNOWN", - [DEVICE_ID_13_UNKNOWN] = "UNKNOWN", - [DEVICE_ID_HBM] = "HBM", -}; - typedef enum { ACCESS_TYPE_MSR = 0, ACCESS_TYPE_MMIO = 1, @@ -186,6 +160,11 @@ typedef enum { FAKE_UNC_GLOBAL_STATUS1, FAKE_UNC_GLOBAL_STATUS2, FAKE_UNC_GLOBAL_STATUS3, + FAKE_UNC_GLOBAL_STATUS4, + FAKE_UNC_GLOBAL_STATUS5, + FAKE_UNC_GLOBAL_STATUS6, + FAKE_UNC_GLOBAL_STATUS7, + FAKE_UNC_GLOBAL_STATUS8, FAKE_UNC_FILTER0, FAKE_UNC_CTR_FREERUN0, FAKE_UNC_CTR_FREERUN1, @@ -201,7 +180,7 @@ typedef struct { uint64_t ctr_offset; uint64_t status_offset; AccessTypes access_type; - uncore_discovery_box_types box_type; + int box_type; uint64_t box_ctl; uint32_t box_id; uint64_t filter_offset; @@ -210,7 +189,7 @@ typedef struct { uint64_t mmap_addr; uint64_t mmap_offset; size_t mmap_size; - void* io_addr; + void volatile* io_addr; } PerfmonDiscoveryUnit; typedef struct { @@ -236,7 +215,7 @@ typedef struct { } PerfmonDiscovery; -int perfmon_uncore_discovery(PerfmonDiscovery **perfmon); +int perfmon_uncore_discovery(int model, PerfmonDiscovery **perfmon); void perfmon_uncore_discovery_free(PerfmonDiscovery* perfmon); diff --git a/src/includes/pci_types.h b/src/includes/pci_types.h index e43e96327..7bb456f8d 100644 --- a/src/includes/pci_types.h +++ b/src/includes/pci_types.h @@ -69,6 +69,30 @@ typedef enum { PCI_R2PCIE_DEVICE13, PCI_R2PCIE_DEVICE14, PCI_R2PCIE_DEVICE15, + PCI_R2PCIE_DEVICE16, + PCI_R2PCIE_DEVICE17, + PCI_R2PCIE_DEVICE18, + PCI_R2PCIE_DEVICE19, + PCI_R2PCIE_DEVICE20, + PCI_R2PCIE_DEVICE21, + PCI_R2PCIE_DEVICE22, + PCI_R2PCIE_DEVICE23, + PCI_R2PCIE_DEVICE24, + PCI_R2PCIE_DEVICE25, + PCI_R2PCIE_DEVICE26, + PCI_R2PCIE_DEVICE27, + PCI_R2PCIE_DEVICE28, + PCI_R2PCIE_DEVICE29, + PCI_R2PCIE_DEVICE30, + PCI_R2PCIE_DEVICE31, + PCI_R2PCIE_DEVICE32, + PCI_R2PCIE_DEVICE33, + PCI_R2PCIE_DEVICE34, + PCI_R2PCIE_DEVICE35, + PCI_R2PCIE_DEVICE36, + PCI_R2PCIE_DEVICE37, + PCI_R2PCIE_DEVICE38, + PCI_R2PCIE_DEVICE39, PCI_IMC_DEVICE_0_CH_0, PCI_IMC_DEVICE_0_CH_1, PCI_IMC_DEVICE_0_CH_2, @@ -109,6 +133,34 @@ typedef enum { PCI_HA_DEVICE_29, PCI_HA_DEVICE_30, PCI_HA_DEVICE_31, + PCI_HA_DEVICE_32, + PCI_HA_DEVICE_33, + PCI_HA_DEVICE_34, + PCI_HA_DEVICE_35, + PCI_HA_DEVICE_36, + PCI_HA_DEVICE_37, + PCI_HA_DEVICE_38, + PCI_HA_DEVICE_39, + PCI_HA_DEVICE_40, + PCI_HA_DEVICE_41, + PCI_HA_DEVICE_42, + PCI_HA_DEVICE_43, + PCI_HA_DEVICE_44, + PCI_HA_DEVICE_45, + PCI_HA_DEVICE_46, + PCI_HA_DEVICE_47, + PCI_HA_DEVICE_48, + PCI_HA_DEVICE_49, + PCI_HA_DEVICE_50, + PCI_HA_DEVICE_51, + PCI_HA_DEVICE_52, + PCI_HA_DEVICE_53, + PCI_HA_DEVICE_54, + PCI_HA_DEVICE_55, + PCI_HA_DEVICE_56, + PCI_HA_DEVICE_57, + PCI_HA_DEVICE_58, + PCI_HA_DEVICE_59, PCI_QPI_DEVICE_PORT_0, PCI_QPI_DEVICE_PORT_1, PCI_QPI_DEVICE_PORT_2, @@ -121,7 +173,6 @@ typedef enum { PCI_QPI_MISC_DEVICE_PORT_1, PCI_QPI_MISC_DEVICE_PORT_2, PCI_QPI_MISC_DEVICE_PORT_3, - PCI_IRP_DEVICE, PCI_EDC0_UCLK_DEVICE, PCI_EDC0_DCLK_DEVICE, PCI_EDC1_UCLK_DEVICE, @@ -266,14 +317,82 @@ typedef enum { MSR_CBOX_DEVICE_C57, MSR_CBOX_DEVICE_C58, MSR_CBOX_DEVICE_C59, - MSR_PBOX_DEVICE, + MSR_CBOX_DEVICE_C60, + MSR_CBOX_DEVICE_C61, + MSR_CBOX_DEVICE_C62, + MSR_CBOX_DEVICE_C63, + MSR_CBOX_DEVICE_C64, + MSR_CBOX_DEVICE_C65, + MSR_CBOX_DEVICE_C66, + MSR_CBOX_DEVICE_C67, + MSR_CBOX_DEVICE_C68, + MSR_CBOX_DEVICE_C69, + MSR_CBOX_DEVICE_C70, + MSR_CBOX_DEVICE_C71, + MSR_CBOX_DEVICE_C72, + MSR_CBOX_DEVICE_C73, + MSR_CBOX_DEVICE_C74, + MSR_CBOX_DEVICE_C75, + MSR_CBOX_DEVICE_C76, + MSR_CBOX_DEVICE_C77, + MSR_CBOX_DEVICE_C78, + MSR_CBOX_DEVICE_C79, + MSR_CBOX_DEVICE_C80, + MSR_CBOX_DEVICE_C81, + MSR_CBOX_DEVICE_C82, + MSR_CBOX_DEVICE_C83, + MSR_CBOX_DEVICE_C84, + MSR_CBOX_DEVICE_C85, + MSR_CBOX_DEVICE_C86, + MSR_CBOX_DEVICE_C87, + MSR_CBOX_DEVICE_C88, + MSR_CBOX_DEVICE_C89, + MSR_CBOX_DEVICE_C90, + MSR_CBOX_DEVICE_C91, + MSR_CBOX_DEVICE_C92, + MSR_CBOX_DEVICE_C93, + MSR_CBOX_DEVICE_C94, + MSR_CBOX_DEVICE_C95, + MSR_CBOX_DEVICE_C96, + MSR_CBOX_DEVICE_C97, + MSR_CBOX_DEVICE_C98, + MSR_CBOX_DEVICE_C99, + MSR_CBOX_DEVICE_C100, + MSR_CBOX_DEVICE_C101, + MSR_CBOX_DEVICE_C102, + MSR_CBOX_DEVICE_C103, + MSR_CBOX_DEVICE_C104, + MSR_CBOX_DEVICE_C105, + MSR_CBOX_DEVICE_C106, + MSR_CBOX_DEVICE_C107, + MSR_CBOX_DEVICE_C108, + MSR_CBOX_DEVICE_C109, + MSR_CBOX_DEVICE_C110, + MSR_CBOX_DEVICE_C111, + MSR_CBOX_DEVICE_C112, + MSR_CBOX_DEVICE_C113, + MSR_CBOX_DEVICE_C114, + MSR_CBOX_DEVICE_C115, + MSR_CBOX_DEVICE_C116, + MSR_CBOX_DEVICE_C117, + MSR_CBOX_DEVICE_C118, + MSR_CBOX_DEVICE_C119, + MSR_CBOX_DEVICE_C120, + MSR_CBOX_DEVICE_C121, + MSR_CBOX_DEVICE_C122, + MSR_CBOX_DEVICE_C123, + MSR_CBOX_DEVICE_C124, + MSR_CBOX_DEVICE_C125, + MSR_CBOX_DEVICE_C126, + MSR_CBOX_DEVICE_C127, + MSR_CBOX_DEVICE_C128, + MSR_CBOX_DEVICE_C129, + MSR_PBOX_DEVICE_0, MSR_PBOX_DEVICE_1, MSR_PBOX_DEVICE_2, MSR_PBOX_DEVICE_3, MSR_PBOX_DEVICE_4, MSR_PBOX_DEVICE_5, - MSR_PCU_DEVICE, - MSR_IIO_DEVICE, MSR_MDF_DEVICE_0, MSR_MDF_DEVICE_1, MSR_MDF_DEVICE_2, @@ -365,11 +484,22 @@ typedef enum { MSR_M2IOSF_DEVICE_5, MSR_M2IOSF_DEVICE_6, MSR_M2IOSF_DEVICE_7, + MSR_PCU_DEVICE_0, + MSR_PCU_DEVICE_1, + MSR_PCU_DEVICE_2, + MSR_PCU_DEVICE_3, + MSR_PCU_DEVICE_4, + MSR_PCU_DEVICE_5, + MSR_PCU_DEVICE_6, + MSR_PCU_DEVICE_7, MAX_NUM_PCI_DEVICES } PciDeviceIndex; -#define MSR_PBOX_DEVICE_0 MSR_PBOX_DEVICE +#define MSR_PBOX_DEVICE MSR_PBOX_DEVICE_0 #define PCI_R2PCIE_DEVICE PCI_R2PCIE_DEVICE0 +#define MSR_IIO_DEVICE MSR_IIO_DEVICE_0 +#define PCI_IRP_DEVICE MSR_IRP_DEVICE_0 +#define MSR_PCU_DEVICE MSR_PCU_DEVICE_0 typedef struct { PciDeviceType type; diff --git a/src/includes/perfmon_graniterapids.h b/src/includes/perfmon_graniterapids.h new file mode 100644 index 000000000..258fd2123 --- /dev/null +++ b/src/includes/perfmon_graniterapids.h @@ -0,0 +1,630 @@ +/* + * ======================================================================================= + * + * Filename: perfmon_graniterapids.h + * + * Description: Header File of perfmon module for Intel Granite Rapids. + * + * Version: + * Released: + * + * Author: Thomas Gruber (tr), thomas.roehl@googlemail.com + * Project: likwid + * + * Copyright (C) 2015 RRZE, University Erlangen-Nuremberg + * + * This program is free software: you can redistribute it and/or modify it under + * the terms of the GNU General Public License as published by the Free Software + * Foundation, either version 3 of the License, or (at your option) any later + * version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT ANY + * WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A + * PARTICULAR PURPOSE. See the GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + * + * ======================================================================================= + */ + + +#include +#include + + +static int perfmon_numCountersGraniteRapids = NUM_COUNTERS_GRANITERAPIDS; +static int perfmon_numCoreCountersGraniteRapids = NUM_COUNTERS_CORE_GRANITERAPIDS; +static int perfmon_numArchEventsGraniteRapids = NUM_ARCH_EVENTS_GRANITERAPIDS; + +int perfmon_init_graniterapids(int cpu_id) +{ + int ret = 0; + lock_acquire((int*) &tile_lock[affinity_thread2core_lookup[cpu_id]], cpu_id); + lock_acquire((int*) &socket_lock[affinity_thread2socket_lookup[cpu_id]], cpu_id); + lock_acquire((int*) &die_lock[affinity_thread2die_lookup[cpu_id]], cpu_id); + +/* uint64_t misc_enable = 0x0;*/ +/* ret = HPMread(cpu_id, MSR_DEV, MSR_IA32_MISC_ENABLE, &misc_enable);*/ +/* if (ret == 0 && (testBit(misc_enable, 7) == 1) && (testBit(misc_enable, 12) == 0))*/ +/* {*/ +/* ret = HPMwrite(cpu_id, MSR_DEV, MSR_PEBS_ENABLE, 0x0ULL);*/ +/* if (ret != 0)*/ +/* {*/ +/* ERROR_PRINT(Cannot zero %s (0x%X), str(MSR_PEBS_ENABLE), MSR_PEBS_ENABLE);*/ +/* }*/ +/* ret = HPMwrite(cpu_id, MSR_DEV, MSR_PEBS_FRONTEND, 0x0ULL);*/ +/* if (ret != 0)*/ +/* {*/ +/* ERROR_PRINT(Cannot zero %s (0x%X), str(MSR_PEBS_FRONTEND), MSR_PEBS_FRONTEND);*/ +/* }*/ +/* }*/ + return 0; +} + +uint64_t gnr_fixed_setup(int thread_id, RegisterIndex index, PerfmonEvent *event, PerfmonCounter* data) +{ + return spr_fixed_setup(thread_id, index, event, data); +} + +uint64_t gnr_fixed_start(int thread_id, RegisterIndex index, PerfmonEvent *event, PerfmonCounter* data) +{ + return spr_fixed_start(thread_id, index, event, data); +} + +uint64_t gnr_pmc_setup(int thread_id, RegisterIndex index, PerfmonEvent *event, PerfmonCounter* data) +{ + return spr_pmc_setup(thread_id, index, event, data); +} + +uint64_t gnr_uncore_setup(int thread_id, RegisterIndex index, PerfmonEvent *event, PerfmonCounter* data) +{ + return spr_setup_uncore(thread_id, index, event); +} + +uint64_t gnr_uncore_fixed_setup(int thread_id, RegisterIndex index, PerfmonEvent *event, PerfmonCounter* data) +{ + return spr_setup_uncore_fixed(thread_id, index, event); +} + +uint64_t gnr_pmc_start(int thread_id, RegisterIndex index, PerfmonEvent* event, PerfmonCounter* data) +{ + return spr_pmc_start(thread_id, index, event, data); +} + +uint64_t gnr_power_start(int thread_id, RegisterIndex index, PerfmonEvent* event, PerfmonCounter* data) +{ + return spr_power_start(thread_id, index, event, data); +} + +uint64_t gnr_metrics_start(int thread_id, RegisterIndex index, PerfmonEvent* event, PerfmonCounter* data) +{ + return spr_metrics_start(thread_id, index, event, data); +} + +uint64_t gnr_uncore_start(int thread_id, RegisterIndex index, PerfmonEvent* event, PerfmonCounter* data) +{ + return spr_start_uncore(thread_id, index, event, data); +} + +uint64_t gnr_uncore_fixed_start(int thread_id, RegisterIndex index, PerfmonEvent* event, PerfmonCounter* data) +{ + return spr_start_uncore_fixed(thread_id, index, event, data); +} + +uint64_t gnr_fixed_stop(int thread_id, RegisterIndex index, PerfmonEvent* event, PerfmonCounter* data) +{ + return spr_fixed_stop(thread_id, index, event, data); +} + +uint64_t gnr_pmc_stop(int thread_id, RegisterIndex index, PerfmonEvent* event, PerfmonCounter* data) +{ + return spr_pmc_stop(thread_id, index, event, data); +} + +uint64_t gnr_power_stop(int thread_id, RegisterIndex index, PerfmonEvent* event, PerfmonCounter* data) +{ + return spr_power_stop(thread_id, index, event, data); +} + +uint64_t gnr_thermal_stop(int thread_id, RegisterIndex index, PerfmonEvent* event, PerfmonCounter* data) +{ + return spr_thermal_stop(thread_id, index, event, data); +} + +uint64_t gnr_voltage_stop(int thread_id, RegisterIndex index, PerfmonEvent* event, PerfmonCounter* data) +{ + return spr_voltage_stop(thread_id, index, event, data); +} + +uint64_t gnr_metrics_stop(int thread_id, RegisterIndex index, PerfmonEvent* event, PerfmonCounter* data) +{ + return spr_metrics_stop(thread_id, index, event, data); +} + +uint64_t gnr_uncore_stop(int thread_id, RegisterIndex index, PerfmonEvent* event, PerfmonCounter* data) +{ + return spr_stop_uncore(thread_id, index, event, data); +} + +uint64_t gnr_uncore_fixed_stop(int thread_id, RegisterIndex index, PerfmonEvent* event, PerfmonCounter* data) +{ + return spr_stop_uncore_fixed(thread_id, index, event, data); +} + +uint64_t gnr_fixed_read(int thread_id, RegisterIndex index, PerfmonEvent* event, PerfmonCounter* data) +{ + return spr_fixed_read(thread_id, index, event, data); +} + +uint64_t gnr_pmc_read(int thread_id, RegisterIndex index, PerfmonEvent* event, PerfmonCounter* data) +{ + return spr_pmc_read(thread_id, index, event, data); +} + +uint64_t gnr_power_read(int thread_id, RegisterIndex index, PerfmonEvent* event, PerfmonCounter* data) +{ + return spr_power_read(thread_id, index, event, data); +} + +uint64_t gnr_thermal_read(int thread_id, RegisterIndex index, PerfmonEvent* event, PerfmonCounter* data) +{ + return spr_thermal_read(thread_id, index, event, data); +} + +uint64_t gnr_voltage_read(int thread_id, RegisterIndex index, PerfmonEvent* event, PerfmonCounter* data) +{ + return spr_voltage_read(thread_id, index, event, data); +} + +uint64_t gnr_metrics_read(int thread_id, RegisterIndex index, PerfmonEvent* event, PerfmonCounter* data) +{ + return spr_metrics_read(thread_id, index, event, data); +} + +uint64_t gnr_uncore_read(int thread_id, RegisterIndex index, PerfmonEvent* event, PerfmonCounter* data) +{ + return spr_read_uncore(thread_id, index, event, data); +} + +uint64_t gnr_uncore_fixed_read(int thread_id, RegisterIndex index, PerfmonEvent* event, PerfmonCounter* data) +{ + return spr_read_uncore_fixed(thread_id, index, event, data); +} + +typedef enum { + PERFMON_LOCK_HWTHREAD = 0, + PERFMON_LOCK_SOCKET, + PERFMON_LOCK_CORE, + PERFMON_LOCK_NUMA, + PERFMON_LOCK_LLC, + PERFMON_LOCK_DIE, + PERFMON_LOCK_NODE, + MAX_PERFMON_LOCK +} PerfmonFuncLock; +#define MIN_PERFMON_LOCK PERFMON_LOCK_HWTHREAD + +typedef struct { + uint64_t (*setup)(int thread_id, RegisterIndex index, PerfmonEvent* event, PerfmonCounter* data); + uint64_t (*start)(int thread_id, RegisterIndex index, PerfmonEvent* event, PerfmonCounter* data); + uint64_t (*stop)(int thread_id, RegisterIndex index, PerfmonEvent* event, PerfmonCounter* data); + uint64_t (*read)(int thread_id, RegisterIndex index, PerfmonEvent* event, PerfmonCounter* data); + PerfmonFuncLock requiresLock; +} PerfmonFuncs; + +static PerfmonFuncs GnrUnitFuncs[NUM_UNITS] = { + [PMC] = {gnr_pmc_setup, gnr_pmc_start, gnr_pmc_stop, gnr_pmc_read, 0}, + [FIXED] = {gnr_fixed_setup, gnr_fixed_start, gnr_fixed_stop, gnr_fixed_read, 0}, + [POWER] = {NULL, gnr_power_start, gnr_power_stop, gnr_power_read, PERFMON_LOCK_SOCKET}, + [THERMAL] = {NULL, NULL, gnr_thermal_stop, gnr_thermal_read, 0}, + [VOLTAGE] = {NULL, NULL, gnr_voltage_stop, gnr_voltage_read, 0}, + [METRICS] = {NULL, gnr_metrics_start, gnr_metrics_stop, gnr_metrics_read, 0}, + [MBOX0 ... MBOX15] = {gnr_uncore_setup, gnr_uncore_start, gnr_uncore_stop, gnr_uncore_read, PERFMON_LOCK_SOCKET}, + [MBOX0FIX ... MBOX15FIX] = {gnr_uncore_fixed_setup, gnr_uncore_fixed_start, gnr_uncore_fixed_stop, gnr_uncore_fixed_read, PERFMON_LOCK_SOCKET}, + [UBOX] = {gnr_uncore_setup, gnr_uncore_start, gnr_uncore_stop, gnr_uncore_read, PERFMON_LOCK_SOCKET}, + [MDF0 ... MDF49] = {gnr_uncore_setup, gnr_uncore_start, gnr_uncore_stop, gnr_uncore_read, PERFMON_LOCK_SOCKET}, + [QBOX0 ... QBOX3] = {gnr_uncore_setup, gnr_uncore_start, gnr_uncore_stop, gnr_uncore_read, PERFMON_LOCK_SOCKET}, + [WBOX0 ... WBOX3] = {gnr_uncore_setup, gnr_uncore_start, gnr_uncore_stop, gnr_uncore_read, PERFMON_LOCK_SOCKET}, + [CBOX0 ... CBOX127] = {gnr_uncore_setup, gnr_uncore_start, gnr_uncore_stop, gnr_uncore_read, PERFMON_LOCK_SOCKET}, + [BBOX0 ... BBOX31] = {gnr_uncore_setup, gnr_uncore_start, gnr_uncore_stop, gnr_uncore_read, PERFMON_LOCK_SOCKET}, + [PBOX0 ... PBOX31] = {gnr_uncore_setup, gnr_uncore_start, gnr_uncore_stop, gnr_uncore_read, PERFMON_LOCK_SOCKET}, + [RBOX0 ... RBOX3] = {gnr_uncore_setup, gnr_uncore_start, gnr_uncore_stop, gnr_uncore_read, PERFMON_LOCK_SOCKET}, + [IRP0 ... IRP15] = {gnr_uncore_setup, gnr_uncore_start, gnr_uncore_stop, gnr_uncore_read, PERFMON_LOCK_SOCKET}, + [IBOX0 ... IBOX15] = {gnr_uncore_setup, gnr_uncore_start, gnr_uncore_stop, gnr_uncore_read, PERFMON_LOCK_SOCKET}, +}; + +int perfmon_setupCounterThread_graniterapids( + int thread_id, + PerfmonEventSet* eventSet) +{ + int err = 0; + int haveLock = 0; + uint64_t fixed_flags = 0x0ULL; + int cpu_id = groupSet->threads[thread_id].processorId; + + if (socket_lock[affinity_thread2socket_lookup[cpu_id]] == cpu_id) + { + haveLock = 1; + } + + if (MEASURE_CORE(eventSet)) + { + VERBOSEPRINTREG(cpu_id, MSR_PERF_GLOBAL_CTRL, 0x0ULL, FREEZE_PMC_AND_FIXED) + CHECK_MSR_WRITE_ERROR(HPMwrite(cpu_id, MSR_DEV, MSR_PERF_GLOBAL_CTRL, 0x0ULL)); + CHECK_MSR_WRITE_ERROR(HPMwrite(cpu_id, MSR_DEV, MSR_PERF_GLOBAL_OVF_CTRL, 0xC00000070000000F)); + } + if (haveLock && MEASURE_UNCORE(eventSet)) + { + VERBOSEPRINTPCIREG(cpu_id, MSR_UBOX_DEVICE, FAKE_UNC_GLOBAL_CTRL, LLU_CAST (1ULL<<0), FREEZE_UNCORE); + HPMwrite(cpu_id, MSR_UBOX_DEVICE, FAKE_UNC_GLOBAL_CTRL, (1ULL<<0)); + } + for (int i=0;i < eventSet->numberOfEvents;i++) + { + RegisterType type = eventSet->events[i].type; + if (!TESTTYPE(eventSet, type)) + { + continue; + } + RegisterIndex index = eventSet->events[i].index; + PerfmonEvent *event = &(eventSet->events[i].event); + PerfmonCounter* data = eventSet->events[i].threadCounter; + uint64_t reg = counter_map[index].configRegister; + eventSet->events[i].threadCounter[thread_id].init = TRUE; + + PerfmonFuncs *unitFuncs = &GnrUnitFuncs[type]; + if (unitFuncs && unitFuncs->setup != NULL) + { + haveLock = 0; + switch (unitFuncs->requiresLock) + { + case PERFMON_LOCK_HWTHREAD: + haveLock = 1; + break; + case PERFMON_LOCK_SOCKET: + haveLock = (socket_lock[affinity_thread2socket_lookup[cpu_id]] == cpu_id); + break; + } + if (haveLock) + { + uint64_t ret = unitFuncs->setup(thread_id, index, event, data); + if (type == FIXED) + { + fixed_flags |= ret; + } + } + } + } + if ((fixed_flags > 0x0ULL)) + { + VERBOSEPRINTREG(cpu_id, MSR_PERF_FIXED_CTR_CTRL, LLU_CAST fixed_flags, SETUP_FIXED) + CHECK_MSR_WRITE_ERROR(HPMwrite(cpu_id, MSR_DEV, MSR_PERF_FIXED_CTR_CTRL, fixed_flags)); + } + return 0; +} + +int perfmon_startCountersThread_graniterapids(int thread_id, PerfmonEventSet* eventSet) +{ + int haveLock = 0; + uint64_t flags = 0x0ULL; + uint64_t uflags = 0x0ULL; + uint64_t tmp = 0x0ULL; + int cpu_id = groupSet->threads[thread_id].processorId; + + if (socket_lock[affinity_thread2socket_lookup[cpu_id]] == cpu_id) + { + haveLock = 1; + } + + for (int i=0;i < eventSet->numberOfEvents;i++) + { + if (eventSet->events[i].threadCounter[thread_id].init == TRUE) + { + RegisterType type = eventSet->events[i].type; + if (!TESTTYPE(eventSet, type)) + { + continue; + } + tmp = 0x0ULL; + RegisterIndex index = eventSet->events[i].index; + PerfmonEvent *event = &(eventSet->events[i].event); + PerfmonCounter* data = eventSet->events[i].threadCounter; + uint64_t counter1 = counter_map[index].counterRegister; + + PciDeviceIndex dev = counter_map[index].device; + data[thread_id].startData = 0; + data[thread_id].counterData = 0; + + PerfmonFuncs *unitFuncs = &GnrUnitFuncs[type]; + if (unitFuncs && unitFuncs->start != NULL) + { + haveLock = 0; + switch (unitFuncs->requiresLock) + { + case PERFMON_LOCK_HWTHREAD: + haveLock = 1; + break; + case PERFMON_LOCK_SOCKET: + haveLock = (socket_lock[affinity_thread2socket_lookup[cpu_id]] == cpu_id); + break; + } + if (haveLock) + { + uint64_t ret = unitFuncs->start(thread_id, index, event, data); + if (type == FIXED || type == PMC) + { + flags |= ret; + } + } + } + data[thread_id].counterData = data[thread_id].startData; + } + } + if (haveLock && MEASURE_UNCORE(eventSet)) + { + for (int i = MSR_DEV + 1; i < MAX_NUM_PCI_DEVICES; i++) + { + if (TESTTYPE(eventSet, i) && box_map[i].device != MSR_DEV) + { + VERBOSEPRINTPCIREG(cpu_id, box_map[i].device, box_map[i].ctrlRegister, LLU_CAST 0x0ULL, UNFREEZE_UNIT); + HPMwrite(cpu_id, box_map[i].device, box_map[i].ctrlRegister, 0x0ULL); + } + } + VERBOSEPRINTPCIREG(cpu_id, MSR_UBOX_DEVICE, FAKE_UNC_GLOBAL_CTRL, LLU_CAST 0x0ULL, UNFREEZE_UNCORE); + HPMwrite(cpu_id, MSR_UBOX_DEVICE, FAKE_UNC_GLOBAL_CTRL, 0x0ULL); + } + if (MEASURE_CORE(eventSet)) + { + if (flags & (1ULL << 48)) + { + VERBOSEPRINTREG(cpu_id, MSR_PERF_METRICS, 0x0ULL, CLEAR_METRICS) + CHECK_MSR_WRITE_ERROR(HPMwrite(cpu_id, MSR_DEV, MSR_PERF_METRICS, 0x0ULL)); + } + VERBOSEPRINTREG(cpu_id, MSR_PERF_GLOBAL_OVF_CTRL, LLU_CAST (1ULL<<63)|(1ULL<<62)|flags, CLEAR_PMC_AND_FIXED_OVERFLOW) + CHECK_MSR_WRITE_ERROR(HPMwrite(cpu_id, MSR_DEV, MSR_PERF_GLOBAL_OVF_CTRL, (1ULL<<63)|(1ULL<<62)|flags)); + VERBOSEPRINTREG(cpu_id, MSR_PERF_GLOBAL_CTRL, LLU_CAST flags, UNFREEZE_PMC_AND_FIXED) + CHECK_MSR_WRITE_ERROR(HPMwrite(cpu_id, MSR_DEV, MSR_PERF_GLOBAL_CTRL, flags)); + } + return 0; +} + + +int perfmon_stopCountersThread_graniterapids(int thread_id, PerfmonEventSet* eventSet) +{ + int haveLock = 0; + int coffset = 0; + uint64_t counter_result = 0x0ULL; + uint64_t tmp = 0x0ULL; + int cpu_id = groupSet->threads[thread_id].processorId; + + if (socket_lock[affinity_thread2socket_lookup[cpu_id]] == cpu_id) + { + haveLock = 1; + } + + if (MEASURE_CORE(eventSet)) + { + VERBOSEPRINTREG(cpu_id, MSR_PERF_GLOBAL_CTRL, 0x0ULL, FREEZE_PMC_AND_FIXED) + CHECK_MSR_WRITE_ERROR(HPMwrite(cpu_id, MSR_DEV, MSR_PERF_GLOBAL_CTRL, 0x0ULL)); + } + if (haveLock && MEASURE_UNCORE(eventSet)) + { + for (int i = MSR_DEV + 1; i < MAX_NUM_PCI_DEVICES; i++) + { + if (TESTTYPE(eventSet, i) && box_map[i].device != MSR_DEV) + { + VERBOSEPRINTPCIREG(cpu_id, box_map[i].device, box_map[i].ctrlRegister, LLU_CAST (1ULL<<0), FREEZE_UNIT); + HPMwrite(cpu_id, box_map[i].device, box_map[i].ctrlRegister, (1ULL<<0)); + } + } + VERBOSEPRINTPCIREG(cpu_id, MSR_UBOX_DEVICE, FAKE_UNC_GLOBAL_CTRL, LLU_CAST (1ULL<<0), FREEZE_UNCORE); + HPMwrite(cpu_id, MSR_UBOX_DEVICE, FAKE_UNC_GLOBAL_CTRL, (1ULL<<0)); + } + + for (int i=0;i < eventSet->numberOfEvents;i++) + { + if (eventSet->events[i].threadCounter[thread_id].init == TRUE) + { + RegisterType type = eventSet->events[i].type; + if (!TESTTYPE(eventSet, type)) + { + continue; + } + tmp = 0x0ULL; + counter_result = 0x0ULL; + RegisterIndex index = eventSet->events[i].index; + PerfmonEvent *event = &(eventSet->events[i].event); + PciDeviceIndex dev = counter_map[index].device; + PerfmonCounter* data = eventSet->events[i].threadCounter; + + uint64_t counter1 = counter_map[index].counterRegister; + uint64_t* current = &(eventSet->events[i].threadCounter[thread_id].counterData); + int* overflows = &(eventSet->events[i].threadCounter[thread_id].overflows); + int ovf_offset = box_map[type].ovflOffset; + PerfmonFuncs *unitFuncs = &GnrUnitFuncs[type]; + if (unitFuncs && unitFuncs->stop != NULL) + { + haveLock = 0; + switch (unitFuncs->requiresLock) + { + case PERFMON_LOCK_HWTHREAD: + haveLock = 1; + break; + case PERFMON_LOCK_SOCKET: + haveLock = (socket_lock[affinity_thread2socket_lookup[cpu_id]] == cpu_id); + break; + } + if (haveLock) + { + unitFuncs->stop(thread_id, index, event, data); + } + } + } + } + return 0; +} + + + +int perfmon_readCountersThread_graniterapids(int thread_id, PerfmonEventSet* eventSet) +{ + int haveLock = 0; + int coffset = 0; + uint64_t flags = 0x0ULL; + uint64_t counter_result = 0x0ULL; + uint64_t tmp = 0x0ULL; + int cpu_id = groupSet->threads[thread_id].processorId; + + if (socket_lock[affinity_thread2socket_lookup[cpu_id]] == cpu_id) + { + haveLock = 1; + } + + if (MEASURE_CORE(eventSet)) + { + CHECK_MSR_READ_ERROR(HPMread(cpu_id, MSR_DEV, MSR_PERF_GLOBAL_CTRL, &flags)); + VERBOSEPRINTREG(cpu_id, MSR_PERF_GLOBAL_CTRL, LLU_CAST flags, SAFE_PMC_FLAGS) + CHECK_MSR_WRITE_ERROR(HPMwrite(cpu_id, MSR_DEV, MSR_PERF_GLOBAL_CTRL, 0x0ULL)); + VERBOSEPRINTREG(cpu_id, MSR_PERF_GLOBAL_CTRL, 0x0ULL, RESET_PMC_FLAGS) + } + if (haveLock && MEASURE_UNCORE(eventSet)) + { + for (int i = MSR_DEV + 1; i < MAX_NUM_PCI_DEVICES; i++) + { + if (TESTTYPE(eventSet, i) && box_map[i].device != MSR_DEV) + { + VERBOSEPRINTPCIREG(cpu_id, box_map[i].device, box_map[i].ctrlRegister, LLU_CAST (1ULL<<0), FREEZE_UNIT); + HPMwrite(cpu_id, box_map[i].device, box_map[i].ctrlRegister, (1ULL<<0)); + } + } + VERBOSEPRINTPCIREG(cpu_id, MSR_UBOX_DEVICE, FAKE_UNC_GLOBAL_CTRL, LLU_CAST (1ULL<<0), FREEZE_UNCORE); + HPMwrite(cpu_id, MSR_UBOX_DEVICE, FAKE_UNC_GLOBAL_CTRL, (1ULL<<0)); + } + for (int i=0;i < eventSet->numberOfEvents;i++) + { + if (eventSet->events[i].threadCounter[thread_id].init == TRUE) + { + RegisterType type = eventSet->events[i].type; + if (!TESTTYPE(eventSet, type)) + { + continue; + } + tmp = 0x0ULL; + counter_result = 0x0ULL; + RegisterIndex index = eventSet->events[i].index; + PerfmonEvent *event = &(eventSet->events[i].event); + PciDeviceIndex dev = counter_map[index].device; + PerfmonCounter* data = eventSet->events[i].threadCounter; + + uint64_t counter1 = counter_map[index].counterRegister; + uint64_t* current = &(eventSet->events[i].threadCounter[thread_id].counterData); + int* overflows = &(eventSet->events[i].threadCounter[thread_id].overflows); + int ovf_offset = box_map[type].ovflOffset; + PerfmonFuncs *unitFuncs = &GnrUnitFuncs[type]; + if (unitFuncs && unitFuncs->read != NULL) + { + haveLock = 0; + switch (unitFuncs->requiresLock) + { + case PERFMON_LOCK_HWTHREAD: + haveLock = 1; + break; + case PERFMON_LOCK_SOCKET: + haveLock = (socket_lock[affinity_thread2socket_lookup[cpu_id]] == cpu_id); + break; + } + if (haveLock) + { + unitFuncs->read(thread_id, index, event, data); + } + } + } + } + if (haveLock && MEASURE_UNCORE(eventSet)) + { + for (int i = MSR_DEV + 1; i < MAX_NUM_PCI_DEVICES; i++) + { + if (TESTTYPE(eventSet, i) && box_map[i].device != MSR_DEV) + { + VERBOSEPRINTPCIREG(cpu_id, box_map[i].device, box_map[i].ctrlRegister, LLU_CAST 0x0ULL, UNFREEZE_UNIT); + HPMwrite(cpu_id, box_map[i].device, box_map[i].ctrlRegister, 0x0ULL); + } + } + VERBOSEPRINTPCIREG(cpu_id, MSR_UBOX_DEVICE, FAKE_UNC_GLOBAL_CTRL, LLU_CAST 0x0ULL, UNFREEZE_UNCORE); + CHECK_MSR_WRITE_ERROR(HPMwrite(cpu_id, MSR_UBOX_DEVICE, FAKE_UNC_GLOBAL_CTRL, 0x0ULL)); + } + if (MEASURE_CORE(eventSet)) + { + VERBOSEPRINTREG(cpu_id, MSR_PERF_GLOBAL_CTRL, LLU_CAST flags, RESTORE_PMC_FLAGS) + CHECK_MSR_WRITE_ERROR(HPMwrite(cpu_id, MSR_DEV, MSR_PERF_GLOBAL_CTRL, flags)); + } + return 0; +} + + + + +int perfmon_finalizeCountersThread_graniterapids(int thread_id, PerfmonEventSet* eventSet) +{ + int haveLock = 0; + int haveTileLock = 0; + int clearPBS = 0; + uint64_t ovf_values_core = (1ULL<<63)|(1ULL<<62); + uint64_t ovf_values_uncore = 0x0ULL; + int cpu_id = groupSet->threads[thread_id].processorId; + + if (socket_lock[affinity_thread2socket_lookup[cpu_id]] == cpu_id) + { + haveLock = 1; + } + if (tile_lock[affinity_thread2core_lookup[cpu_id]] == cpu_id) + { + haveTileLock = 1; + } + for (int i=0;i < eventSet->numberOfEvents;i++) + { + RegisterType type = eventSet->events[i].type; + if (!TESTTYPE(eventSet, type)) + { + continue; + } + RegisterIndex index = eventSet->events[i].index; + PciDeviceIndex dev = counter_map[index].device; + uint64_t reg = counter_map[index].configRegister; + switch (type) + { + case FIXED: + ovf_values_core |= (1ULL<<(index+32)); + break; + default: + break; + } + if ((reg) && (((type == PMC)||(type == FIXED))||(type == METRICS)|| ((type >= UNCORE && type < NUM_UNITS) && (haveLock)))) + { + CHECK_MSR_READ_ERROR(HPMread(cpu_id, dev, reg, &ovf_values_uncore)); + VERBOSEPRINTPCIREG(cpu_id, dev, reg, ovf_values_uncore, SHOW_CTL); + ovf_values_uncore = 0x0ULL; + VERBOSEPRINTPCIREG(cpu_id, dev, reg, 0x0ULL, CLEAR_CTL); + CHECK_MSR_WRITE_ERROR(HPMwrite(cpu_id, dev, reg, 0x0ULL)); + if ((type >= SBOX0) && (type <= SBOX3)) + { + CHECK_MSR_WRITE_ERROR(HPMwrite(cpu_id, dev, reg, 0x0ULL)); + } + VERBOSEPRINTPCIREG(cpu_id, dev, counter_map[index].counterRegister, 0x0ULL, CLEAR_CTR); + CHECK_MSR_WRITE_ERROR(HPMwrite(cpu_id, dev, counter_map[index].counterRegister, 0x0ULL)); + if (box_map[type].filterRegister1 != 0x0) + { + VERBOSEPRINTPCIREG(cpu_id, dev, box_map[type].filterRegister1, 0x0ULL, CLEAR_FILTER); + CHECK_MSR_WRITE_ERROR(HPMwrite(cpu_id, dev, box_map[type].filterRegister1, 0x0ULL)); + } + } + eventSet->events[i].threadCounter[thread_id].init = FALSE; + } + if (MEASURE_CORE(eventSet)) + { + VERBOSEPRINTREG(cpu_id, MSR_PERF_GLOBAL_OVF_CTRL, LLU_CAST ovf_values_core, CLEAR_GLOBAL_OVF) + CHECK_MSR_WRITE_ERROR(HPMwrite(cpu_id, MSR_DEV, MSR_PERF_GLOBAL_OVF_CTRL, ovf_values_core)); + VERBOSEPRINTREG(cpu_id, MSR_PERF_GLOBAL_CTRL, LLU_CAST 0x0ULL, CLEAR_GLOBAL_CTRL) + CHECK_MSR_WRITE_ERROR(HPMwrite(cpu_id, MSR_DEV, MSR_PERF_GLOBAL_CTRL, 0x0ULL)); + } + return 0; +} diff --git a/src/includes/perfmon_graniterapids_counters.h b/src/includes/perfmon_graniterapids_counters.h new file mode 100644 index 000000000..d70d72671 --- /dev/null +++ b/src/includes/perfmon_graniterapids_counters.h @@ -0,0 +1,2033 @@ +/* + * ======================================================================================= + * + * Filename: perfmon_graniterapids_counters.h + * + * Description: Counter Header File of perfmon module for Intel Granite Rapids. + * + * Version: + * Released: + * + * Author: Thomas Gruber (tr), thomas.roehl@googlemail.com + * Project: likwid + * + * Copyright (C) 2015 RRZE, University Erlangen-Nuremberg + * + * This program is free software: you can redistribute it and/or modify it under + * the terms of the GNU General Public License as published by the Free Software + * Foundation, either version 3 of the License, or (at your option) any later + * version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT ANY + * WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A + * PARTICULAR PURPOSE. See the GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + * + * ======================================================================================= + */ + +#include + +#define NUM_COUNTERS_GRANITERAPIDS 1253 +#define NUM_COUNTERS_CORE_GRANITERAPIDS 18 +#define NUM_COUNTERS_UNCORE_GRANITERAPIDS 5 + + +#define GNR_VALID_OPTIONS_FIXED EVENT_OPTION_ANYTHREAD_MASK|EVENT_OPTION_COUNT_KERNEL_MASK +#define GNR_VALID_OPTIONS_PMC EVENT_OPTION_EDGE_MASK|EVENT_OPTION_COUNT_KERNEL_MASK|EVENT_OPTION_INVERT_MASK| \ + EVENT_OPTION_ANYTHREAD_MASK|EVENT_OPTION_IN_TRANS_MASK|EVENT_OPTION_THRESHOLD_MASK + +#define GNR_VALID_OPTIONS_CBOX EVENT_OPTION_EDGE_MASK|EVENT_OPTION_INVERT_MASK|\ + EVENT_OPTION_THRESHOLD_MASK|EVENT_OPTION_TID_MASK +#define GNR_VALID_OPTIONS_UNCORE EVENT_OPTION_EDGE_MASK|EVENT_OPTION_INVERT_MASK|\ + EVENT_OPTION_THRESHOLD_MASK + + +static RegisterMap graniterapids_counter_map[NUM_COUNTERS_GRANITERAPIDS] = { + /* Fixed Counters: instructions retired, cycles unhalted core */ + {"FIXC0", PMC0, FIXED, MSR_PERF_FIXED_CTR_CTRL, MSR_PERF_FIXED_CTR0, 0, MSR_DEV, GNR_VALID_OPTIONS_FIXED}, + {"FIXC1", PMC1, FIXED, MSR_PERF_FIXED_CTR_CTRL, MSR_PERF_FIXED_CTR1, 0, MSR_DEV, GNR_VALID_OPTIONS_FIXED}, + {"FIXC2", PMC2, FIXED, MSR_PERF_FIXED_CTR_CTRL, MSR_PERF_FIXED_CTR2, 0, MSR_DEV, GNR_VALID_OPTIONS_FIXED}, + {"FIXC3", PMC3, FIXED, MSR_PERF_FIXED_CTR_CTRL, MSR_PERF_FIXED_CTR3, 0, MSR_DEV, GNR_VALID_OPTIONS_FIXED}, + /* PMC Counters: 4 48bit wide */ + {"PMC0", PMC4, PMC, MSR_PERFEVTSEL0, MSR_PMC0, 0, MSR_DEV, GNR_VALID_OPTIONS_PMC}, + {"PMC1", PMC5, PMC, MSR_PERFEVTSEL1, MSR_PMC1, 0, MSR_DEV, GNR_VALID_OPTIONS_PMC}, + {"PMC2", PMC6, PMC, MSR_PERFEVTSEL2, MSR_PMC2, 0, MSR_DEV, GNR_VALID_OPTIONS_PMC|EVENT_OPTION_IN_TRANS_ABORT_MASK}, + {"PMC3", PMC7, PMC, MSR_PERFEVTSEL3, MSR_PMC3, 0, MSR_DEV, GNR_VALID_OPTIONS_PMC}, + /* Additional PMC Counters if HyperThreading is not active: 4 48bit wide */ + {"PMC4", PMC8, PMC, MSR_PERFEVTSEL4, MSR_PMC4, 0, MSR_DEV, GNR_VALID_OPTIONS_PMC}, + {"PMC5", PMC9, PMC, MSR_PERFEVTSEL5, MSR_PMC5, 0, MSR_DEV, GNR_VALID_OPTIONS_PMC}, + {"PMC6", PMC10, PMC, MSR_PERFEVTSEL6, MSR_PMC6, 0, MSR_DEV, GNR_VALID_OPTIONS_PMC|EVENT_OPTION_IN_TRANS_ABORT_MASK}, + {"PMC7", PMC11, PMC, MSR_PERFEVTSEL7, MSR_PMC7, 0, MSR_DEV, GNR_VALID_OPTIONS_PMC}, + /* Temperature Sensor*/ + {"TMP0", PMC12, THERMAL, 0, IA32_THERM_STATUS, 0, MSR_DEV, EVENT_OPTION_NONE_MASK}, + /* Vcore Status*/ + {"VTG0", PMC13, VOLTAGE, 0, MSR_PERF_STATUS, 0, MSR_DEV, EVENT_OPTION_NONE_MASK}, + /* Intel Performance Metrics */ + {"TMA0", PMC14, METRICS, 0, MSR_PERF_METRICS, 0, MSR_DEV, EVENT_OPTION_NONE_MASK}, + {"TMA1", PMC15, METRICS, 0, MSR_PERF_METRICS, 0, MSR_DEV, EVENT_OPTION_NONE_MASK}, + {"TMA2", PMC16, METRICS, 0, MSR_PERF_METRICS, 0, MSR_DEV, EVENT_OPTION_NONE_MASK}, + {"TMA3", PMC17, METRICS, 0, MSR_PERF_METRICS, 0, MSR_DEV, EVENT_OPTION_NONE_MASK}, + {"TMA4", PMC18, METRICS, 0, MSR_PERF_METRICS, 0, MSR_DEV, EVENT_OPTION_NONE_MASK}, + {"TMA5", PMC19, METRICS, 0, MSR_PERF_METRICS, 0, MSR_DEV, EVENT_OPTION_NONE_MASK}, + {"TMA6", PMC20, METRICS, 0, MSR_PERF_METRICS, 0, MSR_DEV, EVENT_OPTION_NONE_MASK}, + {"TMA7", PMC21, METRICS, 0, MSR_PERF_METRICS, 0, MSR_DEV, EVENT_OPTION_NONE_MASK}, + /* RAPL counters */ + {"PWR0", PMC22, POWER, 0, MSR_PKG_ENERGY_STATUS, 0, MSR_DEV, EVENT_OPTION_NONE_MASK}, + {"PWR1", PMC23, POWER, 0, MSR_PP0_ENERGY_STATUS, 0, MSR_DEV, EVENT_OPTION_NONE_MASK}, + {"PWR2", PMC24, POWER, 0, MSR_PP1_ENERGY_STATUS, 0, MSR_DEV, EVENT_OPTION_NONE_MASK}, + {"PWR3", PMC25, POWER, 0, MSR_DRAM_ENERGY_STATUS, 0, MSR_DEV, EVENT_OPTION_NONE_MASK}, + {"PWR4", PMC26, POWER, 0, MSR_PLATFORM_ENERGY_STATUS, 0, MSR_DEV, EVENT_OPTION_NONE_MASK}, + // Memory controllers + {"MBOX0C0", PMC27, MBOX0, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MMIO_IMC_DEVICE_0_CH_0, GNR_VALID_OPTIONS_UNCORE}, + {"MBOX0C1", PMC28, MBOX0, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MMIO_IMC_DEVICE_0_CH_0, GNR_VALID_OPTIONS_UNCORE}, + {"MBOX0C2", PMC29, MBOX0, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MMIO_IMC_DEVICE_0_CH_0, GNR_VALID_OPTIONS_UNCORE}, + {"MBOX0C3", PMC30, MBOX0, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MMIO_IMC_DEVICE_0_CH_0, GNR_VALID_OPTIONS_UNCORE}, + {"MBOX0FIX", PMC31, MBOX0FIX, FAKE_UNC_FIXED_CTRL, FAKE_UNC_FIXED_CTR, 0, MMIO_IMC_DEVICE_0_CH_0, EVENT_OPTION_NONE_MASK}, + {"MBOX1C0", PMC32, MBOX1, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MMIO_IMC_DEVICE_0_CH_1, GNR_VALID_OPTIONS_UNCORE}, + {"MBOX1C1", PMC33, MBOX1, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MMIO_IMC_DEVICE_0_CH_1, GNR_VALID_OPTIONS_UNCORE}, + {"MBOX1C2", PMC34, MBOX1, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MMIO_IMC_DEVICE_0_CH_1, GNR_VALID_OPTIONS_UNCORE}, + {"MBOX1C3", PMC35, MBOX1, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MMIO_IMC_DEVICE_0_CH_1, GNR_VALID_OPTIONS_UNCORE}, + {"MBOX1FIX", PMC36, MBOX1FIX, FAKE_UNC_FIXED_CTRL, FAKE_UNC_FIXED_CTR, 0, MMIO_IMC_DEVICE_0_CH_1, EVENT_OPTION_NONE_MASK}, + {"MBOX2C0", PMC37, MBOX2, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MMIO_IMC_DEVICE_0_CH_2, GNR_VALID_OPTIONS_UNCORE}, + {"MBOX2C1", PMC38, MBOX2, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MMIO_IMC_DEVICE_0_CH_2, GNR_VALID_OPTIONS_UNCORE}, + {"MBOX2C2", PMC39, MBOX2, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MMIO_IMC_DEVICE_0_CH_2, GNR_VALID_OPTIONS_UNCORE}, + {"MBOX2C3", PMC40, MBOX2, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MMIO_IMC_DEVICE_0_CH_2, GNR_VALID_OPTIONS_UNCORE}, + {"MBOX2FIX", PMC41, MBOX2FIX, FAKE_UNC_FIXED_CTRL, FAKE_UNC_FIXED_CTR, 0, MMIO_IMC_DEVICE_0_CH_2, EVENT_OPTION_NONE_MASK}, + {"MBOX3C0", PMC42, MBOX3, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MMIO_IMC_DEVICE_0_CH_3, GNR_VALID_OPTIONS_UNCORE}, + {"MBOX3C1", PMC43, MBOX3, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MMIO_IMC_DEVICE_0_CH_3, GNR_VALID_OPTIONS_UNCORE}, + {"MBOX3C2", PMC44, MBOX3, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MMIO_IMC_DEVICE_0_CH_3, GNR_VALID_OPTIONS_UNCORE}, + {"MBOX3C3", PMC45, MBOX3, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MMIO_IMC_DEVICE_0_CH_3, GNR_VALID_OPTIONS_UNCORE}, + {"MBOX3FIX", PMC46, MBOX3FIX, FAKE_UNC_FIXED_CTRL, FAKE_UNC_FIXED_CTR, 0, MMIO_IMC_DEVICE_0_CH_3, EVENT_OPTION_NONE_MASK}, + {"MBOX4C0", PMC47, MBOX4, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MMIO_IMC_DEVICE_0_CH_4, GNR_VALID_OPTIONS_UNCORE}, + {"MBOX4C1", PMC48, MBOX4, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MMIO_IMC_DEVICE_0_CH_4, GNR_VALID_OPTIONS_UNCORE}, + {"MBOX4C2", PMC49, MBOX4, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MMIO_IMC_DEVICE_0_CH_4, GNR_VALID_OPTIONS_UNCORE}, + {"MBOX4C3", PMC50, MBOX4, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MMIO_IMC_DEVICE_0_CH_4, GNR_VALID_OPTIONS_UNCORE}, + {"MBOX4FIX", PMC51, MBOX4FIX, FAKE_UNC_FIXED_CTRL, FAKE_UNC_FIXED_CTR, 0, MMIO_IMC_DEVICE_0_CH_4, EVENT_OPTION_NONE_MASK}, + {"MBOX5C0", PMC52, MBOX5, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MMIO_IMC_DEVICE_0_CH_5, GNR_VALID_OPTIONS_UNCORE}, + {"MBOX5C1", PMC53, MBOX5, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MMIO_IMC_DEVICE_0_CH_5, GNR_VALID_OPTIONS_UNCORE}, + {"MBOX5C2", PMC54, MBOX5, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MMIO_IMC_DEVICE_0_CH_5, GNR_VALID_OPTIONS_UNCORE}, + {"MBOX5C3", PMC55, MBOX5, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MMIO_IMC_DEVICE_0_CH_5, GNR_VALID_OPTIONS_UNCORE}, + {"MBOX5FIX", PMC56, MBOX5FIX, FAKE_UNC_FIXED_CTRL, FAKE_UNC_FIXED_CTR, 0, MMIO_IMC_DEVICE_0_CH_5, EVENT_OPTION_NONE_MASK}, + {"MBOX6C0", PMC57, MBOX6, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MMIO_IMC_DEVICE_0_CH_6, GNR_VALID_OPTIONS_UNCORE}, + {"MBOX6C1", PMC58, MBOX6, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MMIO_IMC_DEVICE_0_CH_6, GNR_VALID_OPTIONS_UNCORE}, + {"MBOX6C2", PMC59, MBOX6, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MMIO_IMC_DEVICE_0_CH_6, GNR_VALID_OPTIONS_UNCORE}, + {"MBOX6C3", PMC60, MBOX6, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MMIO_IMC_DEVICE_0_CH_6, GNR_VALID_OPTIONS_UNCORE}, + {"MBOX6FIX", PMC61, MBOX6FIX, FAKE_UNC_FIXED_CTRL, FAKE_UNC_FIXED_CTR, 0, MMIO_IMC_DEVICE_0_CH_6, EVENT_OPTION_NONE_MASK}, + {"MBOX7C0", PMC62, MBOX7, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MMIO_IMC_DEVICE_0_CH_7, GNR_VALID_OPTIONS_UNCORE}, + {"MBOX7C1", PMC63, MBOX7, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MMIO_IMC_DEVICE_0_CH_7, GNR_VALID_OPTIONS_UNCORE}, + {"MBOX7C2", PMC64, MBOX7, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MMIO_IMC_DEVICE_0_CH_7, GNR_VALID_OPTIONS_UNCORE}, + {"MBOX7C3", PMC65, MBOX7, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MMIO_IMC_DEVICE_0_CH_7, GNR_VALID_OPTIONS_UNCORE}, + {"MBOX7FIX", PMC66, MBOX7FIX, FAKE_UNC_FIXED_CTRL, FAKE_UNC_FIXED_CTR, 0, MMIO_IMC_DEVICE_0_CH_7, EVENT_OPTION_NONE_MASK}, + {"MBOX8C0", PMC67, MBOX8, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MMIO_IMC_DEVICE_1_CH_0, GNR_VALID_OPTIONS_UNCORE}, + {"MBOX8C1", PMC68, MBOX8, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MMIO_IMC_DEVICE_1_CH_0, GNR_VALID_OPTIONS_UNCORE}, + {"MBOX8C2", PMC69, MBOX8, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MMIO_IMC_DEVICE_1_CH_0, GNR_VALID_OPTIONS_UNCORE}, + {"MBOX8C3", PMC70, MBOX8, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MMIO_IMC_DEVICE_1_CH_0, GNR_VALID_OPTIONS_UNCORE}, + {"MBOX8FIX", PMC71, MBOX8FIX, FAKE_UNC_FIXED_CTRL, FAKE_UNC_FIXED_CTR, 0, MMIO_IMC_DEVICE_1_CH_0, EVENT_OPTION_NONE_MASK}, + {"MBOX9C0", PMC72, MBOX9, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MMIO_IMC_DEVICE_1_CH_1, GNR_VALID_OPTIONS_UNCORE}, + {"MBOX9C1", PMC73, MBOX9, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MMIO_IMC_DEVICE_1_CH_1, GNR_VALID_OPTIONS_UNCORE}, + {"MBOX9C2", PMC74, MBOX9, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MMIO_IMC_DEVICE_1_CH_1, GNR_VALID_OPTIONS_UNCORE}, + {"MBOX9C3", PMC75, MBOX9, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MMIO_IMC_DEVICE_1_CH_1, GNR_VALID_OPTIONS_UNCORE}, + {"MBOX9FIX", PMC76, MBOX9FIX, FAKE_UNC_FIXED_CTRL, FAKE_UNC_FIXED_CTR, 0, MMIO_IMC_DEVICE_1_CH_1, EVENT_OPTION_NONE_MASK}, + {"MBOX10C0", PMC77, MBOX10, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MMIO_IMC_DEVICE_1_CH_2, GNR_VALID_OPTIONS_UNCORE}, + {"MBOX10C1", PMC78, MBOX10, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MMIO_IMC_DEVICE_1_CH_2, GNR_VALID_OPTIONS_UNCORE}, + {"MBOX10C2", PMC79, MBOX10, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MMIO_IMC_DEVICE_1_CH_2, GNR_VALID_OPTIONS_UNCORE}, + {"MBOX10C3", PMC80, MBOX10, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MMIO_IMC_DEVICE_1_CH_2, GNR_VALID_OPTIONS_UNCORE}, + {"MBOX10FIX", PMC81, MBOX10FIX, FAKE_UNC_FIXED_CTRL, FAKE_UNC_FIXED_CTR, 0, MMIO_IMC_DEVICE_1_CH_2, EVENT_OPTION_NONE_MASK}, + {"MBOX11C0", PMC82, MBOX11, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MMIO_IMC_DEVICE_1_CH_3, GNR_VALID_OPTIONS_UNCORE}, + {"MBOX11C1", PMC83, MBOX11, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MMIO_IMC_DEVICE_1_CH_3, GNR_VALID_OPTIONS_UNCORE}, + {"MBOX11C2", PMC84, MBOX11, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MMIO_IMC_DEVICE_1_CH_3, GNR_VALID_OPTIONS_UNCORE}, + {"MBOX11C3", PMC85, MBOX11, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MMIO_IMC_DEVICE_1_CH_3, GNR_VALID_OPTIONS_UNCORE}, + {"MBOX11FIX", PMC86, MBOX11FIX, FAKE_UNC_FIXED_CTRL, FAKE_UNC_FIXED_CTR, 0, MMIO_IMC_DEVICE_1_CH_3, EVENT_OPTION_NONE_MASK}, + {"MBOX12C0", PMC87, MBOX12, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MMIO_IMC_DEVICE_1_CH_4, GNR_VALID_OPTIONS_UNCORE}, + {"MBOX12C1", PMC88, MBOX12, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MMIO_IMC_DEVICE_1_CH_4, GNR_VALID_OPTIONS_UNCORE}, + {"MBOX12C2", PMC89, MBOX12, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MMIO_IMC_DEVICE_1_CH_4, GNR_VALID_OPTIONS_UNCORE}, + {"MBOX12C3", PMC90, MBOX12, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MMIO_IMC_DEVICE_1_CH_4, GNR_VALID_OPTIONS_UNCORE}, + {"MBOX12FIX", PMC91, MBOX12FIX, FAKE_UNC_FIXED_CTRL, FAKE_UNC_FIXED_CTR, 0, MMIO_IMC_DEVICE_1_CH_4, EVENT_OPTION_NONE_MASK}, + {"MBOX13C0", PMC92, MBOX13, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MMIO_IMC_DEVICE_1_CH_5, GNR_VALID_OPTIONS_UNCORE}, + {"MBOX13C1", PMC93, MBOX13, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MMIO_IMC_DEVICE_1_CH_5, GNR_VALID_OPTIONS_UNCORE}, + {"MBOX13C2", PMC94, MBOX13, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MMIO_IMC_DEVICE_1_CH_5, GNR_VALID_OPTIONS_UNCORE}, + {"MBOX13C3", PMC95, MBOX13, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MMIO_IMC_DEVICE_1_CH_5, GNR_VALID_OPTIONS_UNCORE}, + {"MBOX13FIX", PMC96, MBOX13FIX, FAKE_UNC_FIXED_CTRL, FAKE_UNC_FIXED_CTR, 0, MMIO_IMC_DEVICE_1_CH_5, EVENT_OPTION_NONE_MASK}, + {"MBOX14C0", PMC97, MBOX14, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MMIO_IMC_DEVICE_1_CH_6, GNR_VALID_OPTIONS_UNCORE}, + {"MBOX14C1", PMC98, MBOX14, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MMIO_IMC_DEVICE_1_CH_6, GNR_VALID_OPTIONS_UNCORE}, + {"MBOX14C2", PMC99, MBOX14, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MMIO_IMC_DEVICE_1_CH_6, GNR_VALID_OPTIONS_UNCORE}, + {"MBOX14C3", PMC100, MBOX14, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MMIO_IMC_DEVICE_1_CH_6, GNR_VALID_OPTIONS_UNCORE}, + {"MBOX14FIX", PMC101, MBOX14FIX, FAKE_UNC_FIXED_CTRL, FAKE_UNC_FIXED_CTR, 0, MMIO_IMC_DEVICE_1_CH_6, EVENT_OPTION_NONE_MASK}, + {"MBOX15C0", PMC102, MBOX15, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MMIO_IMC_DEVICE_1_CH_7, GNR_VALID_OPTIONS_UNCORE}, + {"MBOX15C1", PMC103, MBOX15, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MMIO_IMC_DEVICE_1_CH_7, GNR_VALID_OPTIONS_UNCORE}, + {"MBOX15C2", PMC104, MBOX15, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MMIO_IMC_DEVICE_1_CH_7, GNR_VALID_OPTIONS_UNCORE}, + {"MBOX15C3", PMC105, MBOX15, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MMIO_IMC_DEVICE_1_CH_7, GNR_VALID_OPTIONS_UNCORE}, + {"MBOX15FIX", PMC106, MBOX15FIX, FAKE_UNC_FIXED_CTRL, FAKE_UNC_FIXED_CTR, 0, MMIO_IMC_DEVICE_1_CH_7, EVENT_OPTION_NONE_MASK}, + {"MDF0C0", PMC107, MDF0, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_MDF_DEVICE_0, GNR_VALID_OPTIONS_UNCORE}, + {"MDF0C1", PMC108, MDF0, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_MDF_DEVICE_0, GNR_VALID_OPTIONS_UNCORE}, + {"MDF0C2", PMC109, MDF0, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_MDF_DEVICE_0, GNR_VALID_OPTIONS_UNCORE}, + {"MDF0C3", PMC110, MDF0, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_MDF_DEVICE_0, GNR_VALID_OPTIONS_UNCORE}, + {"MDF1C0", PMC111, MDF1, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_MDF_DEVICE_1, GNR_VALID_OPTIONS_UNCORE}, + {"MDF1C1", PMC112, MDF1, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_MDF_DEVICE_1, GNR_VALID_OPTIONS_UNCORE}, + {"MDF1C2", PMC113, MDF1, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_MDF_DEVICE_1, GNR_VALID_OPTIONS_UNCORE}, + {"MDF1C3", PMC114, MDF1, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_MDF_DEVICE_1, GNR_VALID_OPTIONS_UNCORE}, + {"MDF2C0", PMC115, MDF2, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_MDF_DEVICE_2, GNR_VALID_OPTIONS_UNCORE}, + {"MDF2C1", PMC116, MDF2, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_MDF_DEVICE_2, GNR_VALID_OPTIONS_UNCORE}, + {"MDF2C2", PMC117, MDF2, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_MDF_DEVICE_2, GNR_VALID_OPTIONS_UNCORE}, + {"MDF2C3", PMC118, MDF2, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_MDF_DEVICE_2, GNR_VALID_OPTIONS_UNCORE}, + {"MDF3C0", PMC119, MDF3, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_MDF_DEVICE_3, GNR_VALID_OPTIONS_UNCORE}, + {"MDF3C1", PMC120, MDF3, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_MDF_DEVICE_3, GNR_VALID_OPTIONS_UNCORE}, + {"MDF3C2", PMC121, MDF3, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_MDF_DEVICE_3, GNR_VALID_OPTIONS_UNCORE}, + {"MDF3C3", PMC122, MDF3, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_MDF_DEVICE_3, GNR_VALID_OPTIONS_UNCORE}, + {"MDF4C0", PMC123, MDF4, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_MDF_DEVICE_4, GNR_VALID_OPTIONS_UNCORE}, + {"MDF4C1", PMC124, MDF4, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_MDF_DEVICE_4, GNR_VALID_OPTIONS_UNCORE}, + {"MDF4C2", PMC125, MDF4, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_MDF_DEVICE_4, GNR_VALID_OPTIONS_UNCORE}, + {"MDF4C3", PMC126, MDF4, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_MDF_DEVICE_4, GNR_VALID_OPTIONS_UNCORE}, + {"MDF5C0", PMC127, MDF5, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_MDF_DEVICE_5, GNR_VALID_OPTIONS_UNCORE}, + {"MDF5C1", PMC128, MDF5, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_MDF_DEVICE_5, GNR_VALID_OPTIONS_UNCORE}, + {"MDF5C2", PMC129, MDF5, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_MDF_DEVICE_5, GNR_VALID_OPTIONS_UNCORE}, + {"MDF5C3", PMC130, MDF5, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_MDF_DEVICE_5, GNR_VALID_OPTIONS_UNCORE}, + {"MDF6C0", PMC131, MDF6, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_MDF_DEVICE_6, GNR_VALID_OPTIONS_UNCORE}, + {"MDF6C1", PMC132, MDF6, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_MDF_DEVICE_6, GNR_VALID_OPTIONS_UNCORE}, + {"MDF6C2", PMC133, MDF6, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_MDF_DEVICE_6, GNR_VALID_OPTIONS_UNCORE}, + {"MDF6C3", PMC134, MDF6, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_MDF_DEVICE_6, GNR_VALID_OPTIONS_UNCORE}, + {"MDF7C0", PMC135, MDF7, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_MDF_DEVICE_7, GNR_VALID_OPTIONS_UNCORE}, + {"MDF7C1", PMC136, MDF7, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_MDF_DEVICE_7, GNR_VALID_OPTIONS_UNCORE}, + {"MDF7C2", PMC137, MDF7, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_MDF_DEVICE_7, GNR_VALID_OPTIONS_UNCORE}, + {"MDF7C3", PMC138, MDF7, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_MDF_DEVICE_7, GNR_VALID_OPTIONS_UNCORE}, + {"MDF8C0", PMC139, MDF8, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_MDF_DEVICE_8, GNR_VALID_OPTIONS_UNCORE}, + {"MDF8C1", PMC140, MDF8, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_MDF_DEVICE_8, GNR_VALID_OPTIONS_UNCORE}, + {"MDF8C2", PMC141, MDF8, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_MDF_DEVICE_8, GNR_VALID_OPTIONS_UNCORE}, + {"MDF8C3", PMC142, MDF8, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_MDF_DEVICE_8, GNR_VALID_OPTIONS_UNCORE}, + {"MDF9C0", PMC143, MDF9, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_MDF_DEVICE_9, GNR_VALID_OPTIONS_UNCORE}, + {"MDF9C1", PMC144, MDF9, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_MDF_DEVICE_9, GNR_VALID_OPTIONS_UNCORE}, + {"MDF9C2", PMC145, MDF9, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_MDF_DEVICE_9, GNR_VALID_OPTIONS_UNCORE}, + {"MDF9C3", PMC146, MDF9, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_MDF_DEVICE_9, GNR_VALID_OPTIONS_UNCORE}, + {"MDF10C0", PMC147, MDF10, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_MDF_DEVICE_10, GNR_VALID_OPTIONS_UNCORE}, + {"MDF10C1", PMC148, MDF10, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_MDF_DEVICE_10, GNR_VALID_OPTIONS_UNCORE}, + {"MDF10C2", PMC149, MDF10, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_MDF_DEVICE_10, GNR_VALID_OPTIONS_UNCORE}, + {"MDF10C3", PMC150, MDF10, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_MDF_DEVICE_10, GNR_VALID_OPTIONS_UNCORE}, + {"MDF11C0", PMC151, MDF11, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_MDF_DEVICE_11, GNR_VALID_OPTIONS_UNCORE}, + {"MDF11C1", PMC152, MDF11, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_MDF_DEVICE_11, GNR_VALID_OPTIONS_UNCORE}, + {"MDF11C2", PMC153, MDF11, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_MDF_DEVICE_11, GNR_VALID_OPTIONS_UNCORE}, + {"MDF11C3", PMC154, MDF11, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_MDF_DEVICE_11, GNR_VALID_OPTIONS_UNCORE}, + {"MDF12C0", PMC155, MDF12, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_MDF_DEVICE_12, GNR_VALID_OPTIONS_UNCORE}, + {"MDF12C1", PMC156, MDF12, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_MDF_DEVICE_12, GNR_VALID_OPTIONS_UNCORE}, + {"MDF12C2", PMC157, MDF12, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_MDF_DEVICE_12, GNR_VALID_OPTIONS_UNCORE}, + {"MDF12C3", PMC158, MDF12, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_MDF_DEVICE_12, GNR_VALID_OPTIONS_UNCORE}, + {"MDF13C0", PMC159, MDF13, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_MDF_DEVICE_13, GNR_VALID_OPTIONS_UNCORE}, + {"MDF13C1", PMC160, MDF13, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_MDF_DEVICE_13, GNR_VALID_OPTIONS_UNCORE}, + {"MDF13C2", PMC161, MDF13, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_MDF_DEVICE_13, GNR_VALID_OPTIONS_UNCORE}, + {"MDF13C3", PMC162, MDF13, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_MDF_DEVICE_13, GNR_VALID_OPTIONS_UNCORE}, + {"MDF14C0", PMC163, MDF14, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_MDF_DEVICE_14, GNR_VALID_OPTIONS_UNCORE}, + {"MDF14C1", PMC164, MDF14, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_MDF_DEVICE_14, GNR_VALID_OPTIONS_UNCORE}, + {"MDF14C2", PMC165, MDF14, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_MDF_DEVICE_14, GNR_VALID_OPTIONS_UNCORE}, + {"MDF14C3", PMC166, MDF14, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_MDF_DEVICE_14, GNR_VALID_OPTIONS_UNCORE}, + {"MDF15C0", PMC167, MDF15, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_MDF_DEVICE_15, GNR_VALID_OPTIONS_UNCORE}, + {"MDF15C1", PMC168, MDF15, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_MDF_DEVICE_15, GNR_VALID_OPTIONS_UNCORE}, + {"MDF15C2", PMC169, MDF15, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_MDF_DEVICE_15, GNR_VALID_OPTIONS_UNCORE}, + {"MDF15C3", PMC170, MDF15, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_MDF_DEVICE_15, GNR_VALID_OPTIONS_UNCORE}, + {"MDF16C0", PMC171, MDF16, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_MDF_DEVICE_16, GNR_VALID_OPTIONS_UNCORE}, + {"MDF16C1", PMC172, MDF16, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_MDF_DEVICE_16, GNR_VALID_OPTIONS_UNCORE}, + {"MDF16C2", PMC173, MDF16, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_MDF_DEVICE_16, GNR_VALID_OPTIONS_UNCORE}, + {"MDF16C3", PMC174, MDF16, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_MDF_DEVICE_16, GNR_VALID_OPTIONS_UNCORE}, + {"MDF17C0", PMC175, MDF17, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_MDF_DEVICE_17, GNR_VALID_OPTIONS_UNCORE}, + {"MDF17C1", PMC176, MDF17, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_MDF_DEVICE_17, GNR_VALID_OPTIONS_UNCORE}, + {"MDF17C2", PMC177, MDF17, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_MDF_DEVICE_17, GNR_VALID_OPTIONS_UNCORE}, + {"MDF17C3", PMC178, MDF17, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_MDF_DEVICE_17, GNR_VALID_OPTIONS_UNCORE}, + {"MDF18C0", PMC179, MDF18, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_MDF_DEVICE_18, GNR_VALID_OPTIONS_UNCORE}, + {"MDF18C1", PMC180, MDF18, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_MDF_DEVICE_18, GNR_VALID_OPTIONS_UNCORE}, + {"MDF18C2", PMC181, MDF18, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_MDF_DEVICE_18, GNR_VALID_OPTIONS_UNCORE}, + {"MDF18C3", PMC182, MDF18, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_MDF_DEVICE_18, GNR_VALID_OPTIONS_UNCORE}, + {"MDF19C0", PMC183, MDF19, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_MDF_DEVICE_19, GNR_VALID_OPTIONS_UNCORE}, + {"MDF19C1", PMC184, MDF19, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_MDF_DEVICE_19, GNR_VALID_OPTIONS_UNCORE}, + {"MDF19C2", PMC185, MDF19, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_MDF_DEVICE_19, GNR_VALID_OPTIONS_UNCORE}, + {"MDF19C3", PMC186, MDF19, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_MDF_DEVICE_19, GNR_VALID_OPTIONS_UNCORE}, + {"MDF20C0", PMC187, MDF20, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_MDF_DEVICE_20, GNR_VALID_OPTIONS_UNCORE}, + {"MDF20C1", PMC188, MDF20, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_MDF_DEVICE_20, GNR_VALID_OPTIONS_UNCORE}, + {"MDF20C2", PMC189, MDF20, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_MDF_DEVICE_20, GNR_VALID_OPTIONS_UNCORE}, + {"MDF20C3", PMC190, MDF20, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_MDF_DEVICE_20, GNR_VALID_OPTIONS_UNCORE}, + {"MDF21C0", PMC191, MDF21, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_MDF_DEVICE_21, GNR_VALID_OPTIONS_UNCORE}, + {"MDF21C1", PMC192, MDF21, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_MDF_DEVICE_21, GNR_VALID_OPTIONS_UNCORE}, + {"MDF21C2", PMC193, MDF21, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_MDF_DEVICE_21, GNR_VALID_OPTIONS_UNCORE}, + {"MDF21C3", PMC194, MDF21, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_MDF_DEVICE_21, GNR_VALID_OPTIONS_UNCORE}, + {"MDF22C0", PMC195, MDF22, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_MDF_DEVICE_22, GNR_VALID_OPTIONS_UNCORE}, + {"MDF22C1", PMC196, MDF22, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_MDF_DEVICE_22, GNR_VALID_OPTIONS_UNCORE}, + {"MDF22C2", PMC197, MDF22, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_MDF_DEVICE_22, GNR_VALID_OPTIONS_UNCORE}, + {"MDF22C3", PMC198, MDF22, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_MDF_DEVICE_22, GNR_VALID_OPTIONS_UNCORE}, + {"MDF23C0", PMC199, MDF23, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_MDF_DEVICE_23, GNR_VALID_OPTIONS_UNCORE}, + {"MDF23C1", PMC200, MDF23, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_MDF_DEVICE_23, GNR_VALID_OPTIONS_UNCORE}, + {"MDF23C2", PMC201, MDF23, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_MDF_DEVICE_23, GNR_VALID_OPTIONS_UNCORE}, + {"MDF23C3", PMC202, MDF23, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_MDF_DEVICE_23, GNR_VALID_OPTIONS_UNCORE}, + {"MDF24C0", PMC203, MDF24, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_MDF_DEVICE_24, GNR_VALID_OPTIONS_UNCORE}, + {"MDF24C1", PMC204, MDF24, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_MDF_DEVICE_24, GNR_VALID_OPTIONS_UNCORE}, + {"MDF24C2", PMC205, MDF24, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_MDF_DEVICE_24, GNR_VALID_OPTIONS_UNCORE}, + {"MDF24C3", PMC206, MDF24, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_MDF_DEVICE_24, GNR_VALID_OPTIONS_UNCORE}, + {"MDF25C0", PMC207, MDF25, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_MDF_DEVICE_25, GNR_VALID_OPTIONS_UNCORE}, + {"MDF25C1", PMC208, MDF25, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_MDF_DEVICE_25, GNR_VALID_OPTIONS_UNCORE}, + {"MDF25C2", PMC209, MDF25, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_MDF_DEVICE_25, GNR_VALID_OPTIONS_UNCORE}, + {"MDF25C3", PMC210, MDF25, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_MDF_DEVICE_25, GNR_VALID_OPTIONS_UNCORE}, + {"MDF26C0", PMC211, MDF26, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_MDF_DEVICE_26, GNR_VALID_OPTIONS_UNCORE}, + {"MDF26C1", PMC212, MDF26, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_MDF_DEVICE_26, GNR_VALID_OPTIONS_UNCORE}, + {"MDF26C2", PMC213, MDF26, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_MDF_DEVICE_26, GNR_VALID_OPTIONS_UNCORE}, + {"MDF26C3", PMC214, MDF26, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_MDF_DEVICE_26, GNR_VALID_OPTIONS_UNCORE}, + {"MDF27C0", PMC215, MDF27, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_MDF_DEVICE_27, GNR_VALID_OPTIONS_UNCORE}, + {"MDF27C1", PMC216, MDF27, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_MDF_DEVICE_27, GNR_VALID_OPTIONS_UNCORE}, + {"MDF27C2", PMC217, MDF27, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_MDF_DEVICE_27, GNR_VALID_OPTIONS_UNCORE}, + {"MDF27C3", PMC218, MDF27, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_MDF_DEVICE_27, GNR_VALID_OPTIONS_UNCORE}, + {"MDF28C0", PMC219, MDF28, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_MDF_DEVICE_28, GNR_VALID_OPTIONS_UNCORE}, + {"MDF28C1", PMC220, MDF28, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_MDF_DEVICE_28, GNR_VALID_OPTIONS_UNCORE}, + {"MDF28C2", PMC221, MDF28, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_MDF_DEVICE_28, GNR_VALID_OPTIONS_UNCORE}, + {"MDF28C3", PMC222, MDF28, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_MDF_DEVICE_28, GNR_VALID_OPTIONS_UNCORE}, + {"MDF29C0", PMC223, MDF29, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_MDF_DEVICE_29, GNR_VALID_OPTIONS_UNCORE}, + {"MDF29C1", PMC224, MDF29, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_MDF_DEVICE_29, GNR_VALID_OPTIONS_UNCORE}, + {"MDF29C2", PMC225, MDF29, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_MDF_DEVICE_29, GNR_VALID_OPTIONS_UNCORE}, + {"MDF29C3", PMC226, MDF29, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_MDF_DEVICE_29, GNR_VALID_OPTIONS_UNCORE}, + {"MDF30C0", PMC227, MDF30, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_MDF_DEVICE_30, GNR_VALID_OPTIONS_UNCORE}, + {"MDF30C1", PMC228, MDF30, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_MDF_DEVICE_30, GNR_VALID_OPTIONS_UNCORE}, + {"MDF30C2", PMC229, MDF30, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_MDF_DEVICE_30, GNR_VALID_OPTIONS_UNCORE}, + {"MDF30C3", PMC230, MDF30, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_MDF_DEVICE_30, GNR_VALID_OPTIONS_UNCORE}, + {"MDF31C0", PMC231, MDF31, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_MDF_DEVICE_31, GNR_VALID_OPTIONS_UNCORE}, + {"MDF31C1", PMC232, MDF31, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_MDF_DEVICE_31, GNR_VALID_OPTIONS_UNCORE}, + {"MDF31C2", PMC233, MDF31, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_MDF_DEVICE_31, GNR_VALID_OPTIONS_UNCORE}, + {"MDF31C3", PMC234, MDF31, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_MDF_DEVICE_31, GNR_VALID_OPTIONS_UNCORE}, + {"MDF32C0", PMC235, MDF32, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_MDF_DEVICE_32, GNR_VALID_OPTIONS_UNCORE}, + {"MDF32C1", PMC236, MDF32, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_MDF_DEVICE_32, GNR_VALID_OPTIONS_UNCORE}, + {"MDF32C2", PMC237, MDF32, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_MDF_DEVICE_32, GNR_VALID_OPTIONS_UNCORE}, + {"MDF32C3", PMC238, MDF32, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_MDF_DEVICE_32, GNR_VALID_OPTIONS_UNCORE}, + {"MDF33C0", PMC239, MDF33, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_MDF_DEVICE_33, GNR_VALID_OPTIONS_UNCORE}, + {"MDF33C1", PMC240, MDF33, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_MDF_DEVICE_33, GNR_VALID_OPTIONS_UNCORE}, + {"MDF33C2", PMC241, MDF33, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_MDF_DEVICE_33, GNR_VALID_OPTIONS_UNCORE}, + {"MDF33C3", PMC242, MDF33, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_MDF_DEVICE_33, GNR_VALID_OPTIONS_UNCORE}, + {"MDF34C0", PMC243, MDF34, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_MDF_DEVICE_34, GNR_VALID_OPTIONS_UNCORE}, + {"MDF34C1", PMC244, MDF34, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_MDF_DEVICE_34, GNR_VALID_OPTIONS_UNCORE}, + {"MDF34C2", PMC245, MDF34, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_MDF_DEVICE_34, GNR_VALID_OPTIONS_UNCORE}, + {"MDF34C3", PMC246, MDF34, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_MDF_DEVICE_34, GNR_VALID_OPTIONS_UNCORE}, + {"MDF35C0", PMC247, MDF35, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_MDF_DEVICE_35, GNR_VALID_OPTIONS_UNCORE}, + {"MDF35C1", PMC248, MDF35, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_MDF_DEVICE_35, GNR_VALID_OPTIONS_UNCORE}, + {"MDF35C2", PMC249, MDF35, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_MDF_DEVICE_35, GNR_VALID_OPTIONS_UNCORE}, + {"MDF35C3", PMC250, MDF35, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_MDF_DEVICE_35, GNR_VALID_OPTIONS_UNCORE}, + {"MDF36C0", PMC251, MDF36, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_MDF_DEVICE_36, GNR_VALID_OPTIONS_UNCORE}, + {"MDF36C1", PMC252, MDF36, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_MDF_DEVICE_36, GNR_VALID_OPTIONS_UNCORE}, + {"MDF36C2", PMC253, MDF36, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_MDF_DEVICE_36, GNR_VALID_OPTIONS_UNCORE}, + {"MDF36C3", PMC254, MDF36, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_MDF_DEVICE_36, GNR_VALID_OPTIONS_UNCORE}, + {"MDF37C0", PMC255, MDF37, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_MDF_DEVICE_37, GNR_VALID_OPTIONS_UNCORE}, + {"MDF37C1", PMC256, MDF37, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_MDF_DEVICE_37, GNR_VALID_OPTIONS_UNCORE}, + {"MDF37C2", PMC257, MDF37, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_MDF_DEVICE_37, GNR_VALID_OPTIONS_UNCORE}, + {"MDF37C3", PMC258, MDF37, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_MDF_DEVICE_37, GNR_VALID_OPTIONS_UNCORE}, + {"MDF38C0", PMC259, MDF38, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_MDF_DEVICE_38, GNR_VALID_OPTIONS_UNCORE}, + {"MDF38C1", PMC260, MDF38, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_MDF_DEVICE_38, GNR_VALID_OPTIONS_UNCORE}, + {"MDF38C2", PMC261, MDF38, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_MDF_DEVICE_38, GNR_VALID_OPTIONS_UNCORE}, + {"MDF38C3", PMC262, MDF38, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_MDF_DEVICE_38, GNR_VALID_OPTIONS_UNCORE}, + {"MDF39C0", PMC263, MDF39, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_MDF_DEVICE_39, GNR_VALID_OPTIONS_UNCORE}, + {"MDF39C1", PMC264, MDF39, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_MDF_DEVICE_39, GNR_VALID_OPTIONS_UNCORE}, + {"MDF39C2", PMC265, MDF39, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_MDF_DEVICE_39, GNR_VALID_OPTIONS_UNCORE}, + {"MDF39C3", PMC266, MDF39, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_MDF_DEVICE_39, GNR_VALID_OPTIONS_UNCORE}, + {"MDF40C0", PMC267, MDF40, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_MDF_DEVICE_40, GNR_VALID_OPTIONS_UNCORE}, + {"MDF40C1", PMC268, MDF40, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_MDF_DEVICE_40, GNR_VALID_OPTIONS_UNCORE}, + {"MDF40C2", PMC269, MDF40, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_MDF_DEVICE_40, GNR_VALID_OPTIONS_UNCORE}, + {"MDF40C3", PMC270, MDF40, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_MDF_DEVICE_40, GNR_VALID_OPTIONS_UNCORE}, + {"MDF41C0", PMC271, MDF41, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_MDF_DEVICE_41, GNR_VALID_OPTIONS_UNCORE}, + {"MDF41C1", PMC272, MDF41, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_MDF_DEVICE_41, GNR_VALID_OPTIONS_UNCORE}, + {"MDF41C2", PMC273, MDF41, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_MDF_DEVICE_41, GNR_VALID_OPTIONS_UNCORE}, + {"MDF41C3", PMC274, MDF41, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_MDF_DEVICE_41, GNR_VALID_OPTIONS_UNCORE}, + {"MDF42C0", PMC275, MDF42, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_MDF_DEVICE_42, GNR_VALID_OPTIONS_UNCORE}, + {"MDF42C1", PMC276, MDF42, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_MDF_DEVICE_42, GNR_VALID_OPTIONS_UNCORE}, + {"MDF42C2", PMC277, MDF42, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_MDF_DEVICE_42, GNR_VALID_OPTIONS_UNCORE}, + {"MDF42C3", PMC278, MDF42, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_MDF_DEVICE_42, GNR_VALID_OPTIONS_UNCORE}, + {"MDF43C0", PMC279, MDF43, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_MDF_DEVICE_43, GNR_VALID_OPTIONS_UNCORE}, + {"MDF43C1", PMC280, MDF43, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_MDF_DEVICE_43, GNR_VALID_OPTIONS_UNCORE}, + {"MDF43C2", PMC281, MDF43, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_MDF_DEVICE_43, GNR_VALID_OPTIONS_UNCORE}, + {"MDF43C3", PMC282, MDF43, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_MDF_DEVICE_43, GNR_VALID_OPTIONS_UNCORE}, + {"MDF44C0", PMC283, MDF44, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_MDF_DEVICE_44, GNR_VALID_OPTIONS_UNCORE}, + {"MDF44C1", PMC284, MDF44, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_MDF_DEVICE_44, GNR_VALID_OPTIONS_UNCORE}, + {"MDF44C2", PMC285, MDF44, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_MDF_DEVICE_44, GNR_VALID_OPTIONS_UNCORE}, + {"MDF44C3", PMC286, MDF44, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_MDF_DEVICE_44, GNR_VALID_OPTIONS_UNCORE}, + {"MDF45C0", PMC287, MDF45, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_MDF_DEVICE_45, GNR_VALID_OPTIONS_UNCORE}, + {"MDF45C1", PMC288, MDF45, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_MDF_DEVICE_45, GNR_VALID_OPTIONS_UNCORE}, + {"MDF45C2", PMC289, MDF45, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_MDF_DEVICE_45, GNR_VALID_OPTIONS_UNCORE}, + {"MDF45C3", PMC290, MDF45, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_MDF_DEVICE_45, GNR_VALID_OPTIONS_UNCORE}, + {"MDF46C0", PMC291, MDF46, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_MDF_DEVICE_46, GNR_VALID_OPTIONS_UNCORE}, + {"MDF46C1", PMC292, MDF46, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_MDF_DEVICE_46, GNR_VALID_OPTIONS_UNCORE}, + {"MDF46C2", PMC293, MDF46, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_MDF_DEVICE_46, GNR_VALID_OPTIONS_UNCORE}, + {"MDF46C3", PMC294, MDF46, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_MDF_DEVICE_46, GNR_VALID_OPTIONS_UNCORE}, + {"MDF47C0", PMC295, MDF47, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_MDF_DEVICE_47, GNR_VALID_OPTIONS_UNCORE}, + {"MDF47C1", PMC296, MDF47, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_MDF_DEVICE_47, GNR_VALID_OPTIONS_UNCORE}, + {"MDF47C2", PMC297, MDF47, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_MDF_DEVICE_47, GNR_VALID_OPTIONS_UNCORE}, + {"MDF47C3", PMC298, MDF47, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_MDF_DEVICE_47, GNR_VALID_OPTIONS_UNCORE}, + {"MDF48C0", PMC299, MDF48, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_MDF_DEVICE_48, GNR_VALID_OPTIONS_UNCORE}, + {"MDF48C1", PMC300, MDF48, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_MDF_DEVICE_48, GNR_VALID_OPTIONS_UNCORE}, + {"MDF48C2", PMC301, MDF48, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_MDF_DEVICE_48, GNR_VALID_OPTIONS_UNCORE}, + {"MDF48C3", PMC302, MDF48, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_MDF_DEVICE_48, GNR_VALID_OPTIONS_UNCORE}, + {"MDF49C0", PMC303, MDF49, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_MDF_DEVICE_49, GNR_VALID_OPTIONS_UNCORE}, + {"MDF49C1", PMC304, MDF49, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_MDF_DEVICE_49, GNR_VALID_OPTIONS_UNCORE}, + {"MDF49C2", PMC305, MDF49, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_MDF_DEVICE_49, GNR_VALID_OPTIONS_UNCORE}, + {"MDF49C3", PMC306, MDF49, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_MDF_DEVICE_49, GNR_VALID_OPTIONS_UNCORE}, + {"UBOX0", PMC307, UBOX, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_UBOX_DEVICE, GNR_VALID_OPTIONS_UNCORE}, + {"UBOX1", PMC308, UBOX, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_UBOX_DEVICE, GNR_VALID_OPTIONS_UNCORE}, + {"UPI0C0", PMC309, QBOX0, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, PCI_QPI_DEVICE_PORT_0, SPR_VALID_OPTIONS_UNCORE}, + {"UPI0C1", PMC310, QBOX0, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, PCI_QPI_DEVICE_PORT_0, SPR_VALID_OPTIONS_UNCORE}, + {"UPI0C2", PMC311, QBOX0, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, PCI_QPI_DEVICE_PORT_0, SPR_VALID_OPTIONS_UNCORE}, + {"UPI0C3", PMC312, QBOX0, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, PCI_QPI_DEVICE_PORT_0, SPR_VALID_OPTIONS_UNCORE}, + {"UPI1C0", PMC313, QBOX1, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, PCI_QPI_DEVICE_PORT_1, SPR_VALID_OPTIONS_UNCORE}, + {"UPI1C1", PMC314, QBOX1, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, PCI_QPI_DEVICE_PORT_1, SPR_VALID_OPTIONS_UNCORE}, + {"UPI1C2", PMC315, QBOX1, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, PCI_QPI_DEVICE_PORT_1, SPR_VALID_OPTIONS_UNCORE}, + {"UPI1C3", PMC316, QBOX1, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, PCI_QPI_DEVICE_PORT_1, SPR_VALID_OPTIONS_UNCORE}, + {"UPI2C0", PMC317, QBOX2, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, PCI_QPI_DEVICE_PORT_2, SPR_VALID_OPTIONS_UNCORE}, + {"UPI2C1", PMC318, QBOX2, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, PCI_QPI_DEVICE_PORT_2, SPR_VALID_OPTIONS_UNCORE}, + {"UPI2C2", PMC319, QBOX2, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, PCI_QPI_DEVICE_PORT_2, SPR_VALID_OPTIONS_UNCORE}, + {"UPI2C3", PMC320, QBOX2, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, PCI_QPI_DEVICE_PORT_2, SPR_VALID_OPTIONS_UNCORE}, + {"UPI3C0", PMC321, QBOX3, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, PCI_QPI_DEVICE_PORT_3, SPR_VALID_OPTIONS_UNCORE}, + {"UPI3C1", PMC322, QBOX3, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, PCI_QPI_DEVICE_PORT_3, SPR_VALID_OPTIONS_UNCORE}, + {"UPI3C2", PMC323, QBOX3, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, PCI_QPI_DEVICE_PORT_3, SPR_VALID_OPTIONS_UNCORE}, + {"UPI3C3", PMC324, QBOX3, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, PCI_QPI_DEVICE_PORT_3, SPR_VALID_OPTIONS_UNCORE}, + {"PCU0C0", PMC325, WBOX0, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_PCU_DEVICE_0, SPR_VALID_OPTIONS_UNCORE}, + {"PCU0C1", PMC326, WBOX0, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_PCU_DEVICE_0, SPR_VALID_OPTIONS_UNCORE}, + {"PCU0C2", PMC327, WBOX0, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_PCU_DEVICE_0, SPR_VALID_OPTIONS_UNCORE}, + {"PCU0C3", PMC328, WBOX0, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_PCU_DEVICE_0, SPR_VALID_OPTIONS_UNCORE}, + {"CBOX0C0", PMC329, CBOX0, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C0, GNR_VALID_OPTIONS_CBOX}, + {"CBOX0C1", PMC330, CBOX0, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C0, GNR_VALID_OPTIONS_CBOX}, + {"CBOX0C2", PMC331, CBOX0, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C0, GNR_VALID_OPTIONS_CBOX}, + {"CBOX0C3", PMC332, CBOX0, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C0, GNR_VALID_OPTIONS_CBOX}, + {"CBOX1C0", PMC333, CBOX1, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C1, GNR_VALID_OPTIONS_CBOX}, + {"CBOX1C1", PMC334, CBOX1, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C1, GNR_VALID_OPTIONS_CBOX}, + {"CBOX1C2", PMC335, CBOX1, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C1, GNR_VALID_OPTIONS_CBOX}, + {"CBOX1C3", PMC336, CBOX1, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C1, GNR_VALID_OPTIONS_CBOX}, + {"CBOX2C0", PMC337, CBOX2, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C2, GNR_VALID_OPTIONS_CBOX}, + {"CBOX2C1", PMC338, CBOX2, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C2, GNR_VALID_OPTIONS_CBOX}, + {"CBOX2C2", PMC339, CBOX2, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C2, GNR_VALID_OPTIONS_CBOX}, + {"CBOX2C3", PMC340, CBOX2, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C2, GNR_VALID_OPTIONS_CBOX}, + {"CBOX3C0", PMC341, CBOX3, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C3, GNR_VALID_OPTIONS_CBOX}, + {"CBOX3C1", PMC342, CBOX3, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C3, GNR_VALID_OPTIONS_CBOX}, + {"CBOX3C2", PMC343, CBOX3, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C3, GNR_VALID_OPTIONS_CBOX}, + {"CBOX3C3", PMC344, CBOX3, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C3, GNR_VALID_OPTIONS_CBOX}, + {"CBOX4C0", PMC345, CBOX4, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C4, GNR_VALID_OPTIONS_CBOX}, + {"CBOX4C1", PMC346, CBOX4, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C4, GNR_VALID_OPTIONS_CBOX}, + {"CBOX4C2", PMC347, CBOX4, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C4, GNR_VALID_OPTIONS_CBOX}, + {"CBOX4C3", PMC348, CBOX4, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C4, GNR_VALID_OPTIONS_CBOX}, + {"CBOX5C0", PMC349, CBOX5, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C5, GNR_VALID_OPTIONS_CBOX}, + {"CBOX5C1", PMC350, CBOX5, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C5, GNR_VALID_OPTIONS_CBOX}, + {"CBOX5C2", PMC351, CBOX5, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C5, GNR_VALID_OPTIONS_CBOX}, + {"CBOX5C3", PMC352, CBOX5, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C5, GNR_VALID_OPTIONS_CBOX}, + {"CBOX6C0", PMC353, CBOX6, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C6, GNR_VALID_OPTIONS_CBOX}, + {"CBOX6C1", PMC354, CBOX6, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C6, GNR_VALID_OPTIONS_CBOX}, + {"CBOX6C2", PMC355, CBOX6, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C6, GNR_VALID_OPTIONS_CBOX}, + {"CBOX6C3", PMC356, CBOX6, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C6, GNR_VALID_OPTIONS_CBOX}, + {"CBOX7C0", PMC357, CBOX7, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C7, GNR_VALID_OPTIONS_CBOX}, + {"CBOX7C1", PMC358, CBOX7, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C7, GNR_VALID_OPTIONS_CBOX}, + {"CBOX7C2", PMC359, CBOX7, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C7, GNR_VALID_OPTIONS_CBOX}, + {"CBOX7C3", PMC360, CBOX7, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C7, GNR_VALID_OPTIONS_CBOX}, + {"CBOX8C0", PMC361, CBOX8, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C8, GNR_VALID_OPTIONS_CBOX}, + {"CBOX8C1", PMC362, CBOX8, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C8, GNR_VALID_OPTIONS_CBOX}, + {"CBOX8C2", PMC363, CBOX8, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C8, GNR_VALID_OPTIONS_CBOX}, + {"CBOX8C3", PMC364, CBOX8, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C8, GNR_VALID_OPTIONS_CBOX}, + {"CBOX9C0", PMC365, CBOX9, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C9, GNR_VALID_OPTIONS_CBOX}, + {"CBOX9C1", PMC366, CBOX9, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C9, GNR_VALID_OPTIONS_CBOX}, + {"CBOX9C2", PMC367, CBOX9, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C9, GNR_VALID_OPTIONS_CBOX}, + {"CBOX9C3", PMC368, CBOX9, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C9, GNR_VALID_OPTIONS_CBOX}, + {"CBOX10C0", PMC369, CBOX10, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C10, GNR_VALID_OPTIONS_CBOX}, + {"CBOX10C1", PMC370, CBOX10, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C10, GNR_VALID_OPTIONS_CBOX}, + {"CBOX10C2", PMC371, CBOX10, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C10, GNR_VALID_OPTIONS_CBOX}, + {"CBOX10C3", PMC372, CBOX10, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C10, GNR_VALID_OPTIONS_CBOX}, + {"CBOX11C0", PMC373, CBOX11, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C11, GNR_VALID_OPTIONS_CBOX}, + {"CBOX11C1", PMC374, CBOX11, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C11, GNR_VALID_OPTIONS_CBOX}, + {"CBOX11C2", PMC375, CBOX11, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C11, GNR_VALID_OPTIONS_CBOX}, + {"CBOX11C3", PMC376, CBOX11, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C11, GNR_VALID_OPTIONS_CBOX}, + {"CBOX12C0", PMC377, CBOX12, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C12, GNR_VALID_OPTIONS_CBOX}, + {"CBOX12C1", PMC378, CBOX12, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C12, GNR_VALID_OPTIONS_CBOX}, + {"CBOX12C2", PMC379, CBOX12, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C12, GNR_VALID_OPTIONS_CBOX}, + {"CBOX12C3", PMC380, CBOX12, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C12, GNR_VALID_OPTIONS_CBOX}, + {"CBOX13C0", PMC381, CBOX13, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C13, GNR_VALID_OPTIONS_CBOX}, + {"CBOX13C1", PMC382, CBOX13, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C13, GNR_VALID_OPTIONS_CBOX}, + {"CBOX13C2", PMC383, CBOX13, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C13, GNR_VALID_OPTIONS_CBOX}, + {"CBOX13C3", PMC384, CBOX13, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C13, GNR_VALID_OPTIONS_CBOX}, + {"CBOX14C0", PMC385, CBOX14, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C14, GNR_VALID_OPTIONS_CBOX}, + {"CBOX14C1", PMC386, CBOX14, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C14, GNR_VALID_OPTIONS_CBOX}, + {"CBOX14C2", PMC387, CBOX14, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C14, GNR_VALID_OPTIONS_CBOX}, + {"CBOX14C3", PMC388, CBOX14, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C14, GNR_VALID_OPTIONS_CBOX}, + {"CBOX15C0", PMC389, CBOX15, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C15, GNR_VALID_OPTIONS_CBOX}, + {"CBOX15C1", PMC390, CBOX15, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C15, GNR_VALID_OPTIONS_CBOX}, + {"CBOX15C2", PMC391, CBOX15, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C15, GNR_VALID_OPTIONS_CBOX}, + {"CBOX15C3", PMC392, CBOX15, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C15, GNR_VALID_OPTIONS_CBOX}, + {"CBOX16C0", PMC393, CBOX16, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C16, GNR_VALID_OPTIONS_CBOX}, + {"CBOX16C1", PMC394, CBOX16, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C16, GNR_VALID_OPTIONS_CBOX}, + {"CBOX16C2", PMC395, CBOX16, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C16, GNR_VALID_OPTIONS_CBOX}, + {"CBOX16C3", PMC396, CBOX16, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C16, GNR_VALID_OPTIONS_CBOX}, + {"CBOX17C0", PMC397, CBOX17, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C17, GNR_VALID_OPTIONS_CBOX}, + {"CBOX17C1", PMC398, CBOX17, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C17, GNR_VALID_OPTIONS_CBOX}, + {"CBOX17C2", PMC399, CBOX17, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C17, GNR_VALID_OPTIONS_CBOX}, + {"CBOX17C3", PMC400, CBOX17, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C17, GNR_VALID_OPTIONS_CBOX}, + {"CBOX18C0", PMC401, CBOX18, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C18, GNR_VALID_OPTIONS_CBOX}, + {"CBOX18C1", PMC402, CBOX18, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C18, GNR_VALID_OPTIONS_CBOX}, + {"CBOX18C2", PMC403, CBOX18, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C18, GNR_VALID_OPTIONS_CBOX}, + {"CBOX18C3", PMC404, CBOX18, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C18, GNR_VALID_OPTIONS_CBOX}, + {"CBOX19C0", PMC405, CBOX19, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C19, GNR_VALID_OPTIONS_CBOX}, + {"CBOX19C1", PMC406, CBOX19, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C19, GNR_VALID_OPTIONS_CBOX}, + {"CBOX19C2", PMC407, CBOX19, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C19, GNR_VALID_OPTIONS_CBOX}, + {"CBOX19C3", PMC408, CBOX19, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C19, GNR_VALID_OPTIONS_CBOX}, + {"CBOX20C0", PMC409, CBOX20, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C20, GNR_VALID_OPTIONS_CBOX}, + {"CBOX20C1", PMC410, CBOX20, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C20, GNR_VALID_OPTIONS_CBOX}, + {"CBOX20C2", PMC411, CBOX20, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C20, GNR_VALID_OPTIONS_CBOX}, + {"CBOX20C3", PMC412, CBOX20, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C20, GNR_VALID_OPTIONS_CBOX}, + {"CBOX21C0", PMC413, CBOX21, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C21, GNR_VALID_OPTIONS_CBOX}, + {"CBOX21C1", PMC414, CBOX21, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C21, GNR_VALID_OPTIONS_CBOX}, + {"CBOX21C2", PMC415, CBOX21, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C21, GNR_VALID_OPTIONS_CBOX}, + {"CBOX21C3", PMC416, CBOX21, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C21, GNR_VALID_OPTIONS_CBOX}, + {"CBOX22C0", PMC417, CBOX22, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C22, GNR_VALID_OPTIONS_CBOX}, + {"CBOX22C1", PMC418, CBOX22, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C22, GNR_VALID_OPTIONS_CBOX}, + {"CBOX22C2", PMC419, CBOX22, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C22, GNR_VALID_OPTIONS_CBOX}, + {"CBOX22C3", PMC420, CBOX22, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C22, GNR_VALID_OPTIONS_CBOX}, + {"CBOX23C0", PMC421, CBOX23, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C23, GNR_VALID_OPTIONS_CBOX}, + {"CBOX23C1", PMC422, CBOX23, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C23, GNR_VALID_OPTIONS_CBOX}, + {"CBOX23C2", PMC423, CBOX23, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C23, GNR_VALID_OPTIONS_CBOX}, + {"CBOX23C3", PMC424, CBOX23, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C23, GNR_VALID_OPTIONS_CBOX}, + {"CBOX24C0", PMC425, CBOX24, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C24, GNR_VALID_OPTIONS_CBOX}, + {"CBOX24C1", PMC426, CBOX24, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C24, GNR_VALID_OPTIONS_CBOX}, + {"CBOX24C2", PMC427, CBOX24, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C24, GNR_VALID_OPTIONS_CBOX}, + {"CBOX24C3", PMC428, CBOX24, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C24, GNR_VALID_OPTIONS_CBOX}, + {"CBOX25C0", PMC429, CBOX25, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C25, GNR_VALID_OPTIONS_CBOX}, + {"CBOX25C1", PMC430, CBOX25, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C25, GNR_VALID_OPTIONS_CBOX}, + {"CBOX25C2", PMC431, CBOX25, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C25, GNR_VALID_OPTIONS_CBOX}, + {"CBOX25C3", PMC432, CBOX25, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C25, GNR_VALID_OPTIONS_CBOX}, + {"CBOX26C0", PMC433, CBOX26, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C26, GNR_VALID_OPTIONS_CBOX}, + {"CBOX26C1", PMC434, CBOX26, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C26, GNR_VALID_OPTIONS_CBOX}, + {"CBOX26C2", PMC435, CBOX26, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C26, GNR_VALID_OPTIONS_CBOX}, + {"CBOX26C3", PMC436, CBOX26, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C26, GNR_VALID_OPTIONS_CBOX}, + {"CBOX27C0", PMC437, CBOX27, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C27, GNR_VALID_OPTIONS_CBOX}, + {"CBOX27C1", PMC438, CBOX27, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C27, GNR_VALID_OPTIONS_CBOX}, + {"CBOX27C2", PMC439, CBOX27, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C27, GNR_VALID_OPTIONS_CBOX}, + {"CBOX27C3", PMC440, CBOX27, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C27, GNR_VALID_OPTIONS_CBOX}, + {"CBOX28C0", PMC441, CBOX28, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C28, GNR_VALID_OPTIONS_CBOX}, + {"CBOX28C1", PMC442, CBOX28, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C28, GNR_VALID_OPTIONS_CBOX}, + {"CBOX28C2", PMC443, CBOX28, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C28, GNR_VALID_OPTIONS_CBOX}, + {"CBOX28C3", PMC444, CBOX28, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C28, GNR_VALID_OPTIONS_CBOX}, + {"CBOX29C0", PMC445, CBOX29, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C29, GNR_VALID_OPTIONS_CBOX}, + {"CBOX29C1", PMC446, CBOX29, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C29, GNR_VALID_OPTIONS_CBOX}, + {"CBOX29C2", PMC447, CBOX29, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C29, GNR_VALID_OPTIONS_CBOX}, + {"CBOX29C3", PMC448, CBOX29, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C29, GNR_VALID_OPTIONS_CBOX}, + {"CBOX30C0", PMC449, CBOX30, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C30, GNR_VALID_OPTIONS_CBOX}, + {"CBOX30C1", PMC450, CBOX30, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C30, GNR_VALID_OPTIONS_CBOX}, + {"CBOX30C2", PMC451, CBOX30, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C30, GNR_VALID_OPTIONS_CBOX}, + {"CBOX30C3", PMC452, CBOX30, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C30, GNR_VALID_OPTIONS_CBOX}, + {"CBOX31C0", PMC453, CBOX31, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C31, GNR_VALID_OPTIONS_CBOX}, + {"CBOX31C1", PMC454, CBOX31, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C31, GNR_VALID_OPTIONS_CBOX}, + {"CBOX31C2", PMC455, CBOX31, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C31, GNR_VALID_OPTIONS_CBOX}, + {"CBOX31C3", PMC456, CBOX31, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C31, GNR_VALID_OPTIONS_CBOX}, + {"CBOX32C0", PMC457, CBOX32, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C32, GNR_VALID_OPTIONS_CBOX}, + {"CBOX32C1", PMC458, CBOX32, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C32, GNR_VALID_OPTIONS_CBOX}, + {"CBOX32C2", PMC459, CBOX32, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C32, GNR_VALID_OPTIONS_CBOX}, + {"CBOX32C3", PMC460, CBOX32, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C32, GNR_VALID_OPTIONS_CBOX}, + {"CBOX33C0", PMC461, CBOX33, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C33, GNR_VALID_OPTIONS_CBOX}, + {"CBOX33C1", PMC462, CBOX33, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C33, GNR_VALID_OPTIONS_CBOX}, + {"CBOX33C2", PMC463, CBOX33, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C33, GNR_VALID_OPTIONS_CBOX}, + {"CBOX33C3", PMC464, CBOX33, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C33, GNR_VALID_OPTIONS_CBOX}, + {"CBOX34C0", PMC465, CBOX34, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C34, GNR_VALID_OPTIONS_CBOX}, + {"CBOX34C1", PMC466, CBOX34, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C34, GNR_VALID_OPTIONS_CBOX}, + {"CBOX34C2", PMC467, CBOX34, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C34, GNR_VALID_OPTIONS_CBOX}, + {"CBOX34C3", PMC468, CBOX34, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C34, GNR_VALID_OPTIONS_CBOX}, + {"CBOX35C0", PMC469, CBOX35, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C35, GNR_VALID_OPTIONS_CBOX}, + {"CBOX35C1", PMC470, CBOX35, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C35, GNR_VALID_OPTIONS_CBOX}, + {"CBOX35C2", PMC471, CBOX35, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C35, GNR_VALID_OPTIONS_CBOX}, + {"CBOX35C3", PMC472, CBOX35, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C35, GNR_VALID_OPTIONS_CBOX}, + {"CBOX36C0", PMC473, CBOX36, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C36, GNR_VALID_OPTIONS_CBOX}, + {"CBOX36C1", PMC474, CBOX36, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C36, GNR_VALID_OPTIONS_CBOX}, + {"CBOX36C2", PMC475, CBOX36, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C36, GNR_VALID_OPTIONS_CBOX}, + {"CBOX36C3", PMC476, CBOX36, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C36, GNR_VALID_OPTIONS_CBOX}, + {"CBOX37C0", PMC477, CBOX37, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C37, GNR_VALID_OPTIONS_CBOX}, + {"CBOX37C1", PMC478, CBOX37, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C37, GNR_VALID_OPTIONS_CBOX}, + {"CBOX37C2", PMC479, CBOX37, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C37, GNR_VALID_OPTIONS_CBOX}, + {"CBOX37C3", PMC480, CBOX37, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C37, GNR_VALID_OPTIONS_CBOX}, + {"CBOX38C0", PMC481, CBOX38, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C38, GNR_VALID_OPTIONS_CBOX}, + {"CBOX38C1", PMC482, CBOX38, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C38, GNR_VALID_OPTIONS_CBOX}, + {"CBOX38C2", PMC483, CBOX38, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C38, GNR_VALID_OPTIONS_CBOX}, + {"CBOX38C3", PMC484, CBOX38, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C38, GNR_VALID_OPTIONS_CBOX}, + {"CBOX39C0", PMC485, CBOX39, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C39, GNR_VALID_OPTIONS_CBOX}, + {"CBOX39C1", PMC486, CBOX39, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C39, GNR_VALID_OPTIONS_CBOX}, + {"CBOX39C2", PMC487, CBOX39, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C39, GNR_VALID_OPTIONS_CBOX}, + {"CBOX39C3", PMC488, CBOX39, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C39, GNR_VALID_OPTIONS_CBOX}, + {"CBOX40C0", PMC489, CBOX40, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C40, GNR_VALID_OPTIONS_CBOX}, + {"CBOX40C1", PMC490, CBOX40, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C40, GNR_VALID_OPTIONS_CBOX}, + {"CBOX40C2", PMC491, CBOX40, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C40, GNR_VALID_OPTIONS_CBOX}, + {"CBOX40C3", PMC492, CBOX40, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C40, GNR_VALID_OPTIONS_CBOX}, + {"CBOX41C0", PMC493, CBOX41, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C41, GNR_VALID_OPTIONS_CBOX}, + {"CBOX41C1", PMC494, CBOX41, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C41, GNR_VALID_OPTIONS_CBOX}, + {"CBOX41C2", PMC495, CBOX41, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C41, GNR_VALID_OPTIONS_CBOX}, + {"CBOX41C3", PMC496, CBOX41, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C41, GNR_VALID_OPTIONS_CBOX}, + {"CBOX42C0", PMC497, CBOX42, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C42, GNR_VALID_OPTIONS_CBOX}, + {"CBOX42C1", PMC498, CBOX42, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C42, GNR_VALID_OPTIONS_CBOX}, + {"CBOX42C2", PMC499, CBOX42, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C42, GNR_VALID_OPTIONS_CBOX}, + {"CBOX42C3", PMC500, CBOX42, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C42, GNR_VALID_OPTIONS_CBOX}, + {"CBOX43C0", PMC501, CBOX43, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C43, GNR_VALID_OPTIONS_CBOX}, + {"CBOX43C1", PMC502, CBOX43, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C43, GNR_VALID_OPTIONS_CBOX}, + {"CBOX43C2", PMC503, CBOX43, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C43, GNR_VALID_OPTIONS_CBOX}, + {"CBOX43C3", PMC504, CBOX43, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C43, GNR_VALID_OPTIONS_CBOX}, + {"CBOX44C0", PMC505, CBOX44, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C44, GNR_VALID_OPTIONS_CBOX}, + {"CBOX44C1", PMC506, CBOX44, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C44, GNR_VALID_OPTIONS_CBOX}, + {"CBOX44C2", PMC507, CBOX44, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C44, GNR_VALID_OPTIONS_CBOX}, + {"CBOX44C3", PMC508, CBOX44, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C44, GNR_VALID_OPTIONS_CBOX}, + {"CBOX45C0", PMC509, CBOX45, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C45, GNR_VALID_OPTIONS_CBOX}, + {"CBOX45C1", PMC510, CBOX45, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C45, GNR_VALID_OPTIONS_CBOX}, + {"CBOX45C2", PMC511, CBOX45, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C45, GNR_VALID_OPTIONS_CBOX}, + {"CBOX45C3", PMC512, CBOX45, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C45, GNR_VALID_OPTIONS_CBOX}, + {"CBOX46C0", PMC513, CBOX46, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C46, GNR_VALID_OPTIONS_CBOX}, + {"CBOX46C1", PMC514, CBOX46, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C46, GNR_VALID_OPTIONS_CBOX}, + {"CBOX46C2", PMC515, CBOX46, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C46, GNR_VALID_OPTIONS_CBOX}, + {"CBOX46C3", PMC516, CBOX46, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C46, GNR_VALID_OPTIONS_CBOX}, + {"CBOX47C0", PMC517, CBOX47, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C47, GNR_VALID_OPTIONS_CBOX}, + {"CBOX47C1", PMC518, CBOX47, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C47, GNR_VALID_OPTIONS_CBOX}, + {"CBOX47C2", PMC519, CBOX47, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C47, GNR_VALID_OPTIONS_CBOX}, + {"CBOX47C3", PMC520, CBOX47, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C47, GNR_VALID_OPTIONS_CBOX}, + {"CBOX48C0", PMC521, CBOX48, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C48, GNR_VALID_OPTIONS_CBOX}, + {"CBOX48C1", PMC522, CBOX48, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C48, GNR_VALID_OPTIONS_CBOX}, + {"CBOX48C2", PMC523, CBOX48, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C48, GNR_VALID_OPTIONS_CBOX}, + {"CBOX48C3", PMC524, CBOX48, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C48, GNR_VALID_OPTIONS_CBOX}, + {"CBOX49C0", PMC525, CBOX49, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C49, GNR_VALID_OPTIONS_CBOX}, + {"CBOX49C1", PMC526, CBOX49, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C49, GNR_VALID_OPTIONS_CBOX}, + {"CBOX49C2", PMC527, CBOX49, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C49, GNR_VALID_OPTIONS_CBOX}, + {"CBOX49C3", PMC528, CBOX49, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C49, GNR_VALID_OPTIONS_CBOX}, + {"CBOX50C0", PMC529, CBOX50, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C50, GNR_VALID_OPTIONS_CBOX}, + {"CBOX50C1", PMC530, CBOX50, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C50, GNR_VALID_OPTIONS_CBOX}, + {"CBOX50C2", PMC531, CBOX50, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C50, GNR_VALID_OPTIONS_CBOX}, + {"CBOX50C3", PMC532, CBOX50, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C50, GNR_VALID_OPTIONS_CBOX}, + {"CBOX51C0", PMC533, CBOX51, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C51, GNR_VALID_OPTIONS_CBOX}, + {"CBOX51C1", PMC534, CBOX51, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C51, GNR_VALID_OPTIONS_CBOX}, + {"CBOX51C2", PMC535, CBOX51, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C51, GNR_VALID_OPTIONS_CBOX}, + {"CBOX51C3", PMC536, CBOX51, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C51, GNR_VALID_OPTIONS_CBOX}, + {"CBOX52C0", PMC537, CBOX52, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C52, GNR_VALID_OPTIONS_CBOX}, + {"CBOX52C1", PMC538, CBOX52, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C52, GNR_VALID_OPTIONS_CBOX}, + {"CBOX52C2", PMC539, CBOX52, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C52, GNR_VALID_OPTIONS_CBOX}, + {"CBOX52C3", PMC540, CBOX52, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C52, GNR_VALID_OPTIONS_CBOX}, + {"CBOX53C0", PMC541, CBOX53, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C53, GNR_VALID_OPTIONS_CBOX}, + {"CBOX53C1", PMC542, CBOX53, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C53, GNR_VALID_OPTIONS_CBOX}, + {"CBOX53C2", PMC543, CBOX53, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C53, GNR_VALID_OPTIONS_CBOX}, + {"CBOX53C3", PMC544, CBOX53, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C53, GNR_VALID_OPTIONS_CBOX}, + {"CBOX54C0", PMC545, CBOX54, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C54, GNR_VALID_OPTIONS_CBOX}, + {"CBOX54C1", PMC546, CBOX54, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C54, GNR_VALID_OPTIONS_CBOX}, + {"CBOX54C2", PMC547, CBOX54, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C54, GNR_VALID_OPTIONS_CBOX}, + {"CBOX54C3", PMC548, CBOX54, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C54, GNR_VALID_OPTIONS_CBOX}, + {"CBOX55C0", PMC549, CBOX55, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C55, GNR_VALID_OPTIONS_CBOX}, + {"CBOX55C1", PMC550, CBOX55, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C55, GNR_VALID_OPTIONS_CBOX}, + {"CBOX55C2", PMC551, CBOX55, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C55, GNR_VALID_OPTIONS_CBOX}, + {"CBOX55C3", PMC552, CBOX55, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C55, GNR_VALID_OPTIONS_CBOX}, + {"CBOX56C0", PMC553, CBOX56, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C56, GNR_VALID_OPTIONS_CBOX}, + {"CBOX56C1", PMC554, CBOX56, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C56, GNR_VALID_OPTIONS_CBOX}, + {"CBOX56C2", PMC555, CBOX56, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C56, GNR_VALID_OPTIONS_CBOX}, + {"CBOX56C3", PMC556, CBOX56, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C56, GNR_VALID_OPTIONS_CBOX}, + {"CBOX57C0", PMC557, CBOX57, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C57, GNR_VALID_OPTIONS_CBOX}, + {"CBOX57C1", PMC558, CBOX57, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C57, GNR_VALID_OPTIONS_CBOX}, + {"CBOX57C2", PMC559, CBOX57, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C57, GNR_VALID_OPTIONS_CBOX}, + {"CBOX57C3", PMC560, CBOX57, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C57, GNR_VALID_OPTIONS_CBOX}, + {"CBOX58C0", PMC561, CBOX58, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C58, GNR_VALID_OPTIONS_CBOX}, + {"CBOX58C1", PMC562, CBOX58, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C58, GNR_VALID_OPTIONS_CBOX}, + {"CBOX58C2", PMC563, CBOX58, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C58, GNR_VALID_OPTIONS_CBOX}, + {"CBOX58C3", PMC564, CBOX58, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C58, GNR_VALID_OPTIONS_CBOX}, + {"CBOX59C0", PMC565, CBOX59, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C59, GNR_VALID_OPTIONS_CBOX}, + {"CBOX59C1", PMC566, CBOX59, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C59, GNR_VALID_OPTIONS_CBOX}, + {"CBOX59C2", PMC567, CBOX59, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C59, GNR_VALID_OPTIONS_CBOX}, + {"CBOX59C3", PMC568, CBOX59, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C59, GNR_VALID_OPTIONS_CBOX}, + {"CBOX60C0", PMC569, CBOX60, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C60, GNR_VALID_OPTIONS_CBOX}, + {"CBOX60C1", PMC570, CBOX60, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C60, GNR_VALID_OPTIONS_CBOX}, + {"CBOX60C2", PMC571, CBOX60, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C60, GNR_VALID_OPTIONS_CBOX}, + {"CBOX60C3", PMC572, CBOX60, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C60, GNR_VALID_OPTIONS_CBOX}, + {"CBOX61C0", PMC573, CBOX61, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C61, GNR_VALID_OPTIONS_CBOX}, + {"CBOX61C1", PMC574, CBOX61, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C61, GNR_VALID_OPTIONS_CBOX}, + {"CBOX61C2", PMC575, CBOX61, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C61, GNR_VALID_OPTIONS_CBOX}, + {"CBOX61C3", PMC576, CBOX61, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C61, GNR_VALID_OPTIONS_CBOX}, + {"CBOX62C0", PMC577, CBOX62, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C62, GNR_VALID_OPTIONS_CBOX}, + {"CBOX62C1", PMC578, CBOX62, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C62, GNR_VALID_OPTIONS_CBOX}, + {"CBOX62C2", PMC579, CBOX62, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C62, GNR_VALID_OPTIONS_CBOX}, + {"CBOX62C3", PMC580, CBOX62, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C62, GNR_VALID_OPTIONS_CBOX}, + {"CBOX63C0", PMC581, CBOX63, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C63, GNR_VALID_OPTIONS_CBOX}, + {"CBOX63C1", PMC582, CBOX63, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C63, GNR_VALID_OPTIONS_CBOX}, + {"CBOX63C2", PMC583, CBOX63, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C63, GNR_VALID_OPTIONS_CBOX}, + {"CBOX63C3", PMC584, CBOX63, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C63, GNR_VALID_OPTIONS_CBOX}, + {"CBOX64C0", PMC585, CBOX64, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C64, GNR_VALID_OPTIONS_CBOX}, + {"CBOX64C1", PMC586, CBOX64, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C64, GNR_VALID_OPTIONS_CBOX}, + {"CBOX64C2", PMC587, CBOX64, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C64, GNR_VALID_OPTIONS_CBOX}, + {"CBOX64C3", PMC588, CBOX64, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C64, GNR_VALID_OPTIONS_CBOX}, + {"CBOX65C0", PMC589, CBOX65, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C65, GNR_VALID_OPTIONS_CBOX}, + {"CBOX65C1", PMC590, CBOX65, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C65, GNR_VALID_OPTIONS_CBOX}, + {"CBOX65C2", PMC591, CBOX65, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C65, GNR_VALID_OPTIONS_CBOX}, + {"CBOX65C3", PMC592, CBOX65, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C65, GNR_VALID_OPTIONS_CBOX}, + {"CBOX66C0", PMC593, CBOX66, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C66, GNR_VALID_OPTIONS_CBOX}, + {"CBOX66C1", PMC594, CBOX66, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C66, GNR_VALID_OPTIONS_CBOX}, + {"CBOX66C2", PMC595, CBOX66, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C66, GNR_VALID_OPTIONS_CBOX}, + {"CBOX66C3", PMC596, CBOX66, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C66, GNR_VALID_OPTIONS_CBOX}, + {"CBOX67C0", PMC597, CBOX67, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C67, GNR_VALID_OPTIONS_CBOX}, + {"CBOX67C1", PMC598, CBOX67, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C67, GNR_VALID_OPTIONS_CBOX}, + {"CBOX67C2", PMC599, CBOX67, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C67, GNR_VALID_OPTIONS_CBOX}, + {"CBOX67C3", PMC600, CBOX67, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C67, GNR_VALID_OPTIONS_CBOX}, + {"CBOX68C0", PMC601, CBOX68, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C68, GNR_VALID_OPTIONS_CBOX}, + {"CBOX68C1", PMC602, CBOX68, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C68, GNR_VALID_OPTIONS_CBOX}, + {"CBOX68C2", PMC603, CBOX68, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C68, GNR_VALID_OPTIONS_CBOX}, + {"CBOX68C3", PMC604, CBOX68, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C68, GNR_VALID_OPTIONS_CBOX}, + {"CBOX69C0", PMC605, CBOX69, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C69, GNR_VALID_OPTIONS_CBOX}, + {"CBOX69C1", PMC606, CBOX69, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C69, GNR_VALID_OPTIONS_CBOX}, + {"CBOX69C2", PMC607, CBOX69, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C69, GNR_VALID_OPTIONS_CBOX}, + {"CBOX69C3", PMC608, CBOX69, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C69, GNR_VALID_OPTIONS_CBOX}, + {"CBOX70C0", PMC609, CBOX70, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C70, GNR_VALID_OPTIONS_CBOX}, + {"CBOX70C1", PMC610, CBOX70, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C70, GNR_VALID_OPTIONS_CBOX}, + {"CBOX70C2", PMC611, CBOX70, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C70, GNR_VALID_OPTIONS_CBOX}, + {"CBOX70C3", PMC612, CBOX70, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C70, GNR_VALID_OPTIONS_CBOX}, + {"CBOX71C0", PMC613, CBOX71, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C71, GNR_VALID_OPTIONS_CBOX}, + {"CBOX71C1", PMC614, CBOX71, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C71, GNR_VALID_OPTIONS_CBOX}, + {"CBOX71C2", PMC615, CBOX71, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C71, GNR_VALID_OPTIONS_CBOX}, + {"CBOX71C3", PMC616, CBOX71, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C71, GNR_VALID_OPTIONS_CBOX}, + {"CBOX72C0", PMC617, CBOX72, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C72, GNR_VALID_OPTIONS_CBOX}, + {"CBOX72C1", PMC618, CBOX72, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C72, GNR_VALID_OPTIONS_CBOX}, + {"CBOX72C2", PMC619, CBOX72, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C72, GNR_VALID_OPTIONS_CBOX}, + {"CBOX72C3", PMC620, CBOX72, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C72, GNR_VALID_OPTIONS_CBOX}, + {"CBOX73C0", PMC621, CBOX73, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C73, GNR_VALID_OPTIONS_CBOX}, + {"CBOX73C1", PMC622, CBOX73, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C73, GNR_VALID_OPTIONS_CBOX}, + {"CBOX73C2", PMC623, CBOX73, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C73, GNR_VALID_OPTIONS_CBOX}, + {"CBOX73C3", PMC624, CBOX73, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C73, GNR_VALID_OPTIONS_CBOX}, + {"CBOX74C0", PMC625, CBOX74, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C74, GNR_VALID_OPTIONS_CBOX}, + {"CBOX74C1", PMC626, CBOX74, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C74, GNR_VALID_OPTIONS_CBOX}, + {"CBOX74C2", PMC627, CBOX74, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C74, GNR_VALID_OPTIONS_CBOX}, + {"CBOX74C3", PMC628, CBOX74, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C74, GNR_VALID_OPTIONS_CBOX}, + {"CBOX75C0", PMC629, CBOX75, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C75, GNR_VALID_OPTIONS_CBOX}, + {"CBOX75C1", PMC630, CBOX75, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C75, GNR_VALID_OPTIONS_CBOX}, + {"CBOX75C2", PMC631, CBOX75, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C75, GNR_VALID_OPTIONS_CBOX}, + {"CBOX75C3", PMC632, CBOX75, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C75, GNR_VALID_OPTIONS_CBOX}, + {"CBOX76C0", PMC633, CBOX76, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C76, GNR_VALID_OPTIONS_CBOX}, + {"CBOX76C1", PMC634, CBOX76, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C76, GNR_VALID_OPTIONS_CBOX}, + {"CBOX76C2", PMC635, CBOX76, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C76, GNR_VALID_OPTIONS_CBOX}, + {"CBOX76C3", PMC636, CBOX76, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C76, GNR_VALID_OPTIONS_CBOX}, + {"CBOX77C0", PMC637, CBOX77, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C77, GNR_VALID_OPTIONS_CBOX}, + {"CBOX77C1", PMC638, CBOX77, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C77, GNR_VALID_OPTIONS_CBOX}, + {"CBOX77C2", PMC639, CBOX77, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C77, GNR_VALID_OPTIONS_CBOX}, + {"CBOX77C3", PMC640, CBOX77, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C77, GNR_VALID_OPTIONS_CBOX}, + {"CBOX78C0", PMC641, CBOX78, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C78, GNR_VALID_OPTIONS_CBOX}, + {"CBOX78C1", PMC642, CBOX78, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C78, GNR_VALID_OPTIONS_CBOX}, + {"CBOX78C2", PMC643, CBOX78, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C78, GNR_VALID_OPTIONS_CBOX}, + {"CBOX78C3", PMC644, CBOX78, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C78, GNR_VALID_OPTIONS_CBOX}, + {"CBOX79C0", PMC645, CBOX79, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C79, GNR_VALID_OPTIONS_CBOX}, + {"CBOX79C1", PMC646, CBOX79, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C79, GNR_VALID_OPTIONS_CBOX}, + {"CBOX79C2", PMC647, CBOX79, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C79, GNR_VALID_OPTIONS_CBOX}, + {"CBOX79C3", PMC648, CBOX79, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C79, GNR_VALID_OPTIONS_CBOX}, + {"CBOX80C0", PMC649, CBOX80, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C80, GNR_VALID_OPTIONS_CBOX}, + {"CBOX80C1", PMC650, CBOX80, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C80, GNR_VALID_OPTIONS_CBOX}, + {"CBOX80C2", PMC651, CBOX80, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C80, GNR_VALID_OPTIONS_CBOX}, + {"CBOX80C3", PMC652, CBOX80, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C80, GNR_VALID_OPTIONS_CBOX}, + {"CBOX81C0", PMC653, CBOX81, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C81, GNR_VALID_OPTIONS_CBOX}, + {"CBOX81C1", PMC654, CBOX81, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C81, GNR_VALID_OPTIONS_CBOX}, + {"CBOX81C2", PMC655, CBOX81, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C81, GNR_VALID_OPTIONS_CBOX}, + {"CBOX81C3", PMC656, CBOX81, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C81, GNR_VALID_OPTIONS_CBOX}, + {"CBOX82C0", PMC657, CBOX82, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C82, GNR_VALID_OPTIONS_CBOX}, + {"CBOX82C1", PMC658, CBOX82, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C82, GNR_VALID_OPTIONS_CBOX}, + {"CBOX82C2", PMC659, CBOX82, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C82, GNR_VALID_OPTIONS_CBOX}, + {"CBOX82C3", PMC660, CBOX82, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C82, GNR_VALID_OPTIONS_CBOX}, + {"CBOX83C0", PMC661, CBOX83, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C83, GNR_VALID_OPTIONS_CBOX}, + {"CBOX83C1", PMC662, CBOX83, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C83, GNR_VALID_OPTIONS_CBOX}, + {"CBOX83C2", PMC663, CBOX83, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C83, GNR_VALID_OPTIONS_CBOX}, + {"CBOX83C3", PMC664, CBOX83, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C83, GNR_VALID_OPTIONS_CBOX}, + {"CBOX84C0", PMC665, CBOX84, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C84, GNR_VALID_OPTIONS_CBOX}, + {"CBOX84C1", PMC666, CBOX84, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C84, GNR_VALID_OPTIONS_CBOX}, + {"CBOX84C2", PMC667, CBOX84, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C84, GNR_VALID_OPTIONS_CBOX}, + {"CBOX84C3", PMC668, CBOX84, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C84, GNR_VALID_OPTIONS_CBOX}, + {"CBOX85C0", PMC669, CBOX85, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C85, GNR_VALID_OPTIONS_CBOX}, + {"CBOX85C1", PMC670, CBOX85, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C85, GNR_VALID_OPTIONS_CBOX}, + {"CBOX85C2", PMC671, CBOX85, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C85, GNR_VALID_OPTIONS_CBOX}, + {"CBOX85C3", PMC672, CBOX85, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C85, GNR_VALID_OPTIONS_CBOX}, + {"CBOX86C0", PMC673, CBOX86, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C86, GNR_VALID_OPTIONS_CBOX}, + {"CBOX86C1", PMC674, CBOX86, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C86, GNR_VALID_OPTIONS_CBOX}, + {"CBOX86C2", PMC675, CBOX86, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C86, GNR_VALID_OPTIONS_CBOX}, + {"CBOX86C3", PMC676, CBOX86, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C86, GNR_VALID_OPTIONS_CBOX}, + {"CBOX87C0", PMC677, CBOX87, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C87, GNR_VALID_OPTIONS_CBOX}, + {"CBOX87C1", PMC678, CBOX87, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C87, GNR_VALID_OPTIONS_CBOX}, + {"CBOX87C2", PMC679, CBOX87, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C87, GNR_VALID_OPTIONS_CBOX}, + {"CBOX87C3", PMC680, CBOX87, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C87, GNR_VALID_OPTIONS_CBOX}, + {"CBOX88C0", PMC681, CBOX88, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C88, GNR_VALID_OPTIONS_CBOX}, + {"CBOX88C1", PMC682, CBOX88, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C88, GNR_VALID_OPTIONS_CBOX}, + {"CBOX88C2", PMC683, CBOX88, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C88, GNR_VALID_OPTIONS_CBOX}, + {"CBOX88C3", PMC684, CBOX88, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C88, GNR_VALID_OPTIONS_CBOX}, + {"CBOX89C0", PMC685, CBOX89, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C89, GNR_VALID_OPTIONS_CBOX}, + {"CBOX89C1", PMC686, CBOX89, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C89, GNR_VALID_OPTIONS_CBOX}, + {"CBOX89C2", PMC687, CBOX89, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C89, GNR_VALID_OPTIONS_CBOX}, + {"CBOX89C3", PMC688, CBOX89, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C89, GNR_VALID_OPTIONS_CBOX}, + {"CBOX90C0", PMC689, CBOX90, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C90, GNR_VALID_OPTIONS_CBOX}, + {"CBOX90C1", PMC690, CBOX90, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C90, GNR_VALID_OPTIONS_CBOX}, + {"CBOX90C2", PMC691, CBOX90, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C90, GNR_VALID_OPTIONS_CBOX}, + {"CBOX90C3", PMC692, CBOX90, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C90, GNR_VALID_OPTIONS_CBOX}, + {"CBOX91C0", PMC693, CBOX91, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C91, GNR_VALID_OPTIONS_CBOX}, + {"CBOX91C1", PMC694, CBOX91, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C91, GNR_VALID_OPTIONS_CBOX}, + {"CBOX91C2", PMC695, CBOX91, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C91, GNR_VALID_OPTIONS_CBOX}, + {"CBOX91C3", PMC696, CBOX91, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C91, GNR_VALID_OPTIONS_CBOX}, + {"CBOX92C0", PMC697, CBOX92, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C92, GNR_VALID_OPTIONS_CBOX}, + {"CBOX92C1", PMC698, CBOX92, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C92, GNR_VALID_OPTIONS_CBOX}, + {"CBOX92C2", PMC699, CBOX92, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C92, GNR_VALID_OPTIONS_CBOX}, + {"CBOX92C3", PMC700, CBOX92, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C92, GNR_VALID_OPTIONS_CBOX}, + {"CBOX93C0", PMC701, CBOX93, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C93, GNR_VALID_OPTIONS_CBOX}, + {"CBOX93C1", PMC702, CBOX93, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C93, GNR_VALID_OPTIONS_CBOX}, + {"CBOX93C2", PMC703, CBOX93, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C93, GNR_VALID_OPTIONS_CBOX}, + {"CBOX93C3", PMC704, CBOX93, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C93, GNR_VALID_OPTIONS_CBOX}, + {"CBOX94C0", PMC705, CBOX94, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C94, GNR_VALID_OPTIONS_CBOX}, + {"CBOX94C1", PMC706, CBOX94, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C94, GNR_VALID_OPTIONS_CBOX}, + {"CBOX94C2", PMC707, CBOX94, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C94, GNR_VALID_OPTIONS_CBOX}, + {"CBOX94C3", PMC708, CBOX94, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C94, GNR_VALID_OPTIONS_CBOX}, + {"CBOX95C0", PMC709, CBOX95, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C95, GNR_VALID_OPTIONS_CBOX}, + {"CBOX95C1", PMC710, CBOX95, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C95, GNR_VALID_OPTIONS_CBOX}, + {"CBOX95C2", PMC711, CBOX95, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C95, GNR_VALID_OPTIONS_CBOX}, + {"CBOX95C3", PMC712, CBOX95, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C95, GNR_VALID_OPTIONS_CBOX}, + {"CBOX96C0", PMC713, CBOX96, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C96, GNR_VALID_OPTIONS_CBOX}, + {"CBOX96C1", PMC714, CBOX96, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C96, GNR_VALID_OPTIONS_CBOX}, + {"CBOX96C2", PMC715, CBOX96, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C96, GNR_VALID_OPTIONS_CBOX}, + {"CBOX96C3", PMC716, CBOX96, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C96, GNR_VALID_OPTIONS_CBOX}, + {"CBOX97C0", PMC717, CBOX97, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C97, GNR_VALID_OPTIONS_CBOX}, + {"CBOX97C1", PMC718, CBOX97, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C97, GNR_VALID_OPTIONS_CBOX}, + {"CBOX97C2", PMC719, CBOX97, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C97, GNR_VALID_OPTIONS_CBOX}, + {"CBOX97C3", PMC720, CBOX97, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C97, GNR_VALID_OPTIONS_CBOX}, + {"CBOX98C0", PMC721, CBOX98, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C98, GNR_VALID_OPTIONS_CBOX}, + {"CBOX98C1", PMC722, CBOX98, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C98, GNR_VALID_OPTIONS_CBOX}, + {"CBOX98C2", PMC723, CBOX98, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C98, GNR_VALID_OPTIONS_CBOX}, + {"CBOX98C3", PMC724, CBOX98, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C98, GNR_VALID_OPTIONS_CBOX}, + {"CBOX99C0", PMC725, CBOX99, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C99, GNR_VALID_OPTIONS_CBOX}, + {"CBOX99C1", PMC726, CBOX99, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C99, GNR_VALID_OPTIONS_CBOX}, + {"CBOX99C2", PMC727, CBOX99, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C99, GNR_VALID_OPTIONS_CBOX}, + {"CBOX99C3", PMC728, CBOX99, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C99, GNR_VALID_OPTIONS_CBOX}, + {"CBOX100C0", PMC729, CBOX100, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C100, GNR_VALID_OPTIONS_CBOX}, + {"CBOX100C1", PMC730, CBOX100, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C100, GNR_VALID_OPTIONS_CBOX}, + {"CBOX100C2", PMC731, CBOX100, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C100, GNR_VALID_OPTIONS_CBOX}, + {"CBOX100C3", PMC732, CBOX100, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C100, GNR_VALID_OPTIONS_CBOX}, + {"CBOX101C0", PMC733, CBOX101, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C101, GNR_VALID_OPTIONS_CBOX}, + {"CBOX101C1", PMC734, CBOX101, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C101, GNR_VALID_OPTIONS_CBOX}, + {"CBOX101C2", PMC735, CBOX101, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C101, GNR_VALID_OPTIONS_CBOX}, + {"CBOX101C3", PMC736, CBOX101, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C101, GNR_VALID_OPTIONS_CBOX}, + {"CBOX102C0", PMC737, CBOX102, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C102, GNR_VALID_OPTIONS_CBOX}, + {"CBOX102C1", PMC738, CBOX102, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C102, GNR_VALID_OPTIONS_CBOX}, + {"CBOX102C2", PMC739, CBOX102, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C102, GNR_VALID_OPTIONS_CBOX}, + {"CBOX102C3", PMC740, CBOX102, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C102, GNR_VALID_OPTIONS_CBOX}, + {"CBOX103C0", PMC741, CBOX103, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C103, GNR_VALID_OPTIONS_CBOX}, + {"CBOX103C1", PMC742, CBOX103, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C103, GNR_VALID_OPTIONS_CBOX}, + {"CBOX103C2", PMC743, CBOX103, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C103, GNR_VALID_OPTIONS_CBOX}, + {"CBOX103C3", PMC744, CBOX103, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C103, GNR_VALID_OPTIONS_CBOX}, + {"CBOX104C0", PMC745, CBOX104, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C104, GNR_VALID_OPTIONS_CBOX}, + {"CBOX104C1", PMC746, CBOX104, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C104, GNR_VALID_OPTIONS_CBOX}, + {"CBOX104C2", PMC747, CBOX104, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C104, GNR_VALID_OPTIONS_CBOX}, + {"CBOX104C3", PMC748, CBOX104, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C104, GNR_VALID_OPTIONS_CBOX}, + {"CBOX105C0", PMC749, CBOX105, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C105, GNR_VALID_OPTIONS_CBOX}, + {"CBOX105C1", PMC750, CBOX105, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C105, GNR_VALID_OPTIONS_CBOX}, + {"CBOX105C2", PMC751, CBOX105, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C105, GNR_VALID_OPTIONS_CBOX}, + {"CBOX105C3", PMC752, CBOX105, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C105, GNR_VALID_OPTIONS_CBOX}, + {"CBOX106C0", PMC753, CBOX106, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C106, GNR_VALID_OPTIONS_CBOX}, + {"CBOX106C1", PMC754, CBOX106, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C106, GNR_VALID_OPTIONS_CBOX}, + {"CBOX106C2", PMC755, CBOX106, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C106, GNR_VALID_OPTIONS_CBOX}, + {"CBOX106C3", PMC756, CBOX106, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C106, GNR_VALID_OPTIONS_CBOX}, + {"CBOX107C0", PMC757, CBOX107, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C107, GNR_VALID_OPTIONS_CBOX}, + {"CBOX107C1", PMC758, CBOX107, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C107, GNR_VALID_OPTIONS_CBOX}, + {"CBOX107C2", PMC759, CBOX107, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C107, GNR_VALID_OPTIONS_CBOX}, + {"CBOX107C3", PMC760, CBOX107, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C107, GNR_VALID_OPTIONS_CBOX}, + {"CBOX108C0", PMC761, CBOX108, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C108, GNR_VALID_OPTIONS_CBOX}, + {"CBOX108C1", PMC762, CBOX108, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C108, GNR_VALID_OPTIONS_CBOX}, + {"CBOX108C2", PMC763, CBOX108, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C108, GNR_VALID_OPTIONS_CBOX}, + {"CBOX108C3", PMC764, CBOX108, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C108, GNR_VALID_OPTIONS_CBOX}, + {"CBOX109C0", PMC765, CBOX109, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C109, GNR_VALID_OPTIONS_CBOX}, + {"CBOX109C1", PMC766, CBOX109, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C109, GNR_VALID_OPTIONS_CBOX}, + {"CBOX109C2", PMC767, CBOX109, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C109, GNR_VALID_OPTIONS_CBOX}, + {"CBOX109C3", PMC768, CBOX109, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C109, GNR_VALID_OPTIONS_CBOX}, + {"CBOX110C0", PMC769, CBOX110, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C110, GNR_VALID_OPTIONS_CBOX}, + {"CBOX110C1", PMC770, CBOX110, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C110, GNR_VALID_OPTIONS_CBOX}, + {"CBOX110C2", PMC771, CBOX110, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C110, GNR_VALID_OPTIONS_CBOX}, + {"CBOX110C3", PMC772, CBOX110, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C110, GNR_VALID_OPTIONS_CBOX}, + {"CBOX111C0", PMC773, CBOX111, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C111, GNR_VALID_OPTIONS_CBOX}, + {"CBOX111C1", PMC774, CBOX111, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C111, GNR_VALID_OPTIONS_CBOX}, + {"CBOX111C2", PMC775, CBOX111, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C111, GNR_VALID_OPTIONS_CBOX}, + {"CBOX111C3", PMC776, CBOX111, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C111, GNR_VALID_OPTIONS_CBOX}, + {"CBOX112C0", PMC777, CBOX112, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C112, GNR_VALID_OPTIONS_CBOX}, + {"CBOX112C1", PMC778, CBOX112, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C112, GNR_VALID_OPTIONS_CBOX}, + {"CBOX112C2", PMC779, CBOX112, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C112, GNR_VALID_OPTIONS_CBOX}, + {"CBOX112C3", PMC780, CBOX112, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C112, GNR_VALID_OPTIONS_CBOX}, + {"CBOX113C0", PMC781, CBOX113, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C113, GNR_VALID_OPTIONS_CBOX}, + {"CBOX113C1", PMC782, CBOX113, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C113, GNR_VALID_OPTIONS_CBOX}, + {"CBOX113C2", PMC783, CBOX113, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C113, GNR_VALID_OPTIONS_CBOX}, + {"CBOX113C3", PMC784, CBOX113, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C113, GNR_VALID_OPTIONS_CBOX}, + {"CBOX114C0", PMC785, CBOX114, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C114, GNR_VALID_OPTIONS_CBOX}, + {"CBOX114C1", PMC786, CBOX114, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C114, GNR_VALID_OPTIONS_CBOX}, + {"CBOX114C2", PMC787, CBOX114, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C114, GNR_VALID_OPTIONS_CBOX}, + {"CBOX114C3", PMC788, CBOX114, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C114, GNR_VALID_OPTIONS_CBOX}, + {"CBOX115C0", PMC789, CBOX115, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C115, GNR_VALID_OPTIONS_CBOX}, + {"CBOX115C1", PMC790, CBOX115, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C115, GNR_VALID_OPTIONS_CBOX}, + {"CBOX115C2", PMC791, CBOX115, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C115, GNR_VALID_OPTIONS_CBOX}, + {"CBOX115C3", PMC792, CBOX115, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C115, GNR_VALID_OPTIONS_CBOX}, + {"CBOX116C0", PMC793, CBOX116, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C116, GNR_VALID_OPTIONS_CBOX}, + {"CBOX116C1", PMC794, CBOX116, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C116, GNR_VALID_OPTIONS_CBOX}, + {"CBOX116C2", PMC795, CBOX116, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C116, GNR_VALID_OPTIONS_CBOX}, + {"CBOX116C3", PMC796, CBOX116, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C116, GNR_VALID_OPTIONS_CBOX}, + {"CBOX117C0", PMC797, CBOX117, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C117, GNR_VALID_OPTIONS_CBOX}, + {"CBOX117C1", PMC798, CBOX117, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C117, GNR_VALID_OPTIONS_CBOX}, + {"CBOX117C2", PMC799, CBOX117, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C117, GNR_VALID_OPTIONS_CBOX}, + {"CBOX117C3", PMC800, CBOX117, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C117, GNR_VALID_OPTIONS_CBOX}, + {"CBOX118C0", PMC801, CBOX118, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C118, GNR_VALID_OPTIONS_CBOX}, + {"CBOX118C1", PMC802, CBOX118, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C118, GNR_VALID_OPTIONS_CBOX}, + {"CBOX118C2", PMC803, CBOX118, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C118, GNR_VALID_OPTIONS_CBOX}, + {"CBOX118C3", PMC804, CBOX118, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C118, GNR_VALID_OPTIONS_CBOX}, + {"CBOX119C0", PMC805, CBOX119, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C119, GNR_VALID_OPTIONS_CBOX}, + {"CBOX119C1", PMC806, CBOX119, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C119, GNR_VALID_OPTIONS_CBOX}, + {"CBOX119C2", PMC807, CBOX119, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C119, GNR_VALID_OPTIONS_CBOX}, + {"CBOX119C3", PMC808, CBOX119, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C119, GNR_VALID_OPTIONS_CBOX}, + {"CBOX120C0", PMC809, CBOX120, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C120, GNR_VALID_OPTIONS_CBOX}, + {"CBOX120C1", PMC810, CBOX120, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C120, GNR_VALID_OPTIONS_CBOX}, + {"CBOX120C2", PMC811, CBOX120, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C120, GNR_VALID_OPTIONS_CBOX}, + {"CBOX120C3", PMC812, CBOX120, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C120, GNR_VALID_OPTIONS_CBOX}, + {"CBOX121C0", PMC813, CBOX121, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C121, GNR_VALID_OPTIONS_CBOX}, + {"CBOX121C1", PMC814, CBOX121, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C121, GNR_VALID_OPTIONS_CBOX}, + {"CBOX121C2", PMC815, CBOX121, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C121, GNR_VALID_OPTIONS_CBOX}, + {"CBOX121C3", PMC816, CBOX121, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C121, GNR_VALID_OPTIONS_CBOX}, + {"CBOX122C0", PMC817, CBOX122, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C122, GNR_VALID_OPTIONS_CBOX}, + {"CBOX122C1", PMC818, CBOX122, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C122, GNR_VALID_OPTIONS_CBOX}, + {"CBOX122C2", PMC819, CBOX122, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C122, GNR_VALID_OPTIONS_CBOX}, + {"CBOX122C3", PMC820, CBOX122, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C122, GNR_VALID_OPTIONS_CBOX}, + {"CBOX123C0", PMC821, CBOX123, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C123, GNR_VALID_OPTIONS_CBOX}, + {"CBOX123C1", PMC822, CBOX123, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C123, GNR_VALID_OPTIONS_CBOX}, + {"CBOX123C2", PMC823, CBOX123, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C123, GNR_VALID_OPTIONS_CBOX}, + {"CBOX123C3", PMC824, CBOX123, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C123, GNR_VALID_OPTIONS_CBOX}, + {"CBOX124C0", PMC825, CBOX124, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C124, GNR_VALID_OPTIONS_CBOX}, + {"CBOX124C1", PMC826, CBOX124, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C124, GNR_VALID_OPTIONS_CBOX}, + {"CBOX124C2", PMC827, CBOX124, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C124, GNR_VALID_OPTIONS_CBOX}, + {"CBOX124C3", PMC828, CBOX124, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C124, GNR_VALID_OPTIONS_CBOX}, + {"CBOX125C0", PMC829, CBOX125, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C125, GNR_VALID_OPTIONS_CBOX}, + {"CBOX125C1", PMC830, CBOX125, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C125, GNR_VALID_OPTIONS_CBOX}, + {"CBOX125C2", PMC831, CBOX125, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C125, GNR_VALID_OPTIONS_CBOX}, + {"CBOX125C3", PMC832, CBOX125, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C125, GNR_VALID_OPTIONS_CBOX}, + {"CBOX126C0", PMC833, CBOX126, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C126, GNR_VALID_OPTIONS_CBOX}, + {"CBOX126C1", PMC834, CBOX126, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C126, GNR_VALID_OPTIONS_CBOX}, + {"CBOX126C2", PMC835, CBOX126, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C126, GNR_VALID_OPTIONS_CBOX}, + {"CBOX126C3", PMC836, CBOX126, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C126, GNR_VALID_OPTIONS_CBOX}, + {"CBOX127C0", PMC837, CBOX127, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_CBOX_DEVICE_C127, GNR_VALID_OPTIONS_CBOX}, + {"CBOX127C1", PMC838, CBOX127, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_CBOX_DEVICE_C127, GNR_VALID_OPTIONS_CBOX}, + {"CBOX127C2", PMC839, CBOX127, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_CBOX_DEVICE_C127, GNR_VALID_OPTIONS_CBOX}, + {"CBOX127C3", PMC840, CBOX127, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_CBOX_DEVICE_C127, GNR_VALID_OPTIONS_CBOX}, + {"M2M0C0", PMC841, BBOX0, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, PCI_HA_DEVICE_0, GNR_VALID_OPTIONS_UNCORE}, + {"M2M0C1", PMC842, BBOX0, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, PCI_HA_DEVICE_0, GNR_VALID_OPTIONS_UNCORE}, + {"M2M0C2", PMC843, BBOX0, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, PCI_HA_DEVICE_0, GNR_VALID_OPTIONS_UNCORE}, + {"M2M0C3", PMC844, BBOX0, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, PCI_HA_DEVICE_0, GNR_VALID_OPTIONS_UNCORE}, + {"M2M1C0", PMC845, BBOX1, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, PCI_HA_DEVICE_1, GNR_VALID_OPTIONS_UNCORE}, + {"M2M1C1", PMC846, BBOX1, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, PCI_HA_DEVICE_1, GNR_VALID_OPTIONS_UNCORE}, + {"M2M1C2", PMC847, BBOX1, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, PCI_HA_DEVICE_1, GNR_VALID_OPTIONS_UNCORE}, + {"M2M1C3", PMC848, BBOX1, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, PCI_HA_DEVICE_1, GNR_VALID_OPTIONS_UNCORE}, + {"M2M2C0", PMC849, BBOX2, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, PCI_HA_DEVICE_2, GNR_VALID_OPTIONS_UNCORE}, + {"M2M2C1", PMC850, BBOX2, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, PCI_HA_DEVICE_2, GNR_VALID_OPTIONS_UNCORE}, + {"M2M2C2", PMC851, BBOX2, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, PCI_HA_DEVICE_2, GNR_VALID_OPTIONS_UNCORE}, + {"M2M2C3", PMC852, BBOX2, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, PCI_HA_DEVICE_2, GNR_VALID_OPTIONS_UNCORE}, + {"M2M3C0", PMC853, BBOX3, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, PCI_HA_DEVICE_3, GNR_VALID_OPTIONS_UNCORE}, + {"M2M3C1", PMC854, BBOX3, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, PCI_HA_DEVICE_3, GNR_VALID_OPTIONS_UNCORE}, + {"M2M3C2", PMC855, BBOX3, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, PCI_HA_DEVICE_3, GNR_VALID_OPTIONS_UNCORE}, + {"M2M3C3", PMC856, BBOX3, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, PCI_HA_DEVICE_3, GNR_VALID_OPTIONS_UNCORE}, + {"M2M4C0", PMC857, BBOX4, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, PCI_HA_DEVICE_4, GNR_VALID_OPTIONS_UNCORE}, + {"M2M4C1", PMC858, BBOX4, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, PCI_HA_DEVICE_4, GNR_VALID_OPTIONS_UNCORE}, + {"M2M4C2", PMC859, BBOX4, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, PCI_HA_DEVICE_4, GNR_VALID_OPTIONS_UNCORE}, + {"M2M4C3", PMC860, BBOX4, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, PCI_HA_DEVICE_4, GNR_VALID_OPTIONS_UNCORE}, + {"M2M5C0", PMC861, BBOX5, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, PCI_HA_DEVICE_5, GNR_VALID_OPTIONS_UNCORE}, + {"M2M5C1", PMC862, BBOX5, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, PCI_HA_DEVICE_5, GNR_VALID_OPTIONS_UNCORE}, + {"M2M5C2", PMC863, BBOX5, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, PCI_HA_DEVICE_5, GNR_VALID_OPTIONS_UNCORE}, + {"M2M5C3", PMC864, BBOX5, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, PCI_HA_DEVICE_5, GNR_VALID_OPTIONS_UNCORE}, + {"M2M6C0", PMC865, BBOX6, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, PCI_HA_DEVICE_6, GNR_VALID_OPTIONS_UNCORE}, + {"M2M6C1", PMC866, BBOX6, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, PCI_HA_DEVICE_6, GNR_VALID_OPTIONS_UNCORE}, + {"M2M6C2", PMC867, BBOX6, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, PCI_HA_DEVICE_6, GNR_VALID_OPTIONS_UNCORE}, + {"M2M6C3", PMC868, BBOX6, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, PCI_HA_DEVICE_6, GNR_VALID_OPTIONS_UNCORE}, + {"M2M7C0", PMC869, BBOX7, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, PCI_HA_DEVICE_7, GNR_VALID_OPTIONS_UNCORE}, + {"M2M7C1", PMC870, BBOX7, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, PCI_HA_DEVICE_7, GNR_VALID_OPTIONS_UNCORE}, + {"M2M7C2", PMC871, BBOX7, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, PCI_HA_DEVICE_7, GNR_VALID_OPTIONS_UNCORE}, + {"M2M7C3", PMC872, BBOX7, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, PCI_HA_DEVICE_7, GNR_VALID_OPTIONS_UNCORE}, + {"M2M8C0", PMC873, BBOX8, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, PCI_HA_DEVICE_8, GNR_VALID_OPTIONS_UNCORE}, + {"M2M8C1", PMC874, BBOX8, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, PCI_HA_DEVICE_8, GNR_VALID_OPTIONS_UNCORE}, + {"M2M8C2", PMC875, BBOX8, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, PCI_HA_DEVICE_8, GNR_VALID_OPTIONS_UNCORE}, + {"M2M8C3", PMC876, BBOX8, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, PCI_HA_DEVICE_8, GNR_VALID_OPTIONS_UNCORE}, + {"M2M9C0", PMC877, BBOX9, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, PCI_HA_DEVICE_9, GNR_VALID_OPTIONS_UNCORE}, + {"M2M9C1", PMC878, BBOX9, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, PCI_HA_DEVICE_9, GNR_VALID_OPTIONS_UNCORE}, + {"M2M9C2", PMC879, BBOX9, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, PCI_HA_DEVICE_9, GNR_VALID_OPTIONS_UNCORE}, + {"M2M9C3", PMC880, BBOX9, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, PCI_HA_DEVICE_9, GNR_VALID_OPTIONS_UNCORE}, + {"M2M10C0", PMC881, BBOX10, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, PCI_HA_DEVICE_10, GNR_VALID_OPTIONS_UNCORE}, + {"M2M10C1", PMC882, BBOX10, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, PCI_HA_DEVICE_10, GNR_VALID_OPTIONS_UNCORE}, + {"M2M10C2", PMC883, BBOX10, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, PCI_HA_DEVICE_10, GNR_VALID_OPTIONS_UNCORE}, + {"M2M10C3", PMC884, BBOX10, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, PCI_HA_DEVICE_10, GNR_VALID_OPTIONS_UNCORE}, + {"M2M11C0", PMC885, BBOX11, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, PCI_HA_DEVICE_11, GNR_VALID_OPTIONS_UNCORE}, + {"M2M11C1", PMC886, BBOX11, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, PCI_HA_DEVICE_11, GNR_VALID_OPTIONS_UNCORE}, + {"M2M11C2", PMC887, BBOX11, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, PCI_HA_DEVICE_11, GNR_VALID_OPTIONS_UNCORE}, + {"M2M11C3", PMC888, BBOX11, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, PCI_HA_DEVICE_11, GNR_VALID_OPTIONS_UNCORE}, + {"M2M12C0", PMC889, BBOX12, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, PCI_HA_DEVICE_12, GNR_VALID_OPTIONS_UNCORE}, + {"M2M12C1", PMC890, BBOX12, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, PCI_HA_DEVICE_12, GNR_VALID_OPTIONS_UNCORE}, + {"M2M12C2", PMC891, BBOX12, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, PCI_HA_DEVICE_12, GNR_VALID_OPTIONS_UNCORE}, + {"M2M12C3", PMC892, BBOX12, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, PCI_HA_DEVICE_12, GNR_VALID_OPTIONS_UNCORE}, + {"M2M13C0", PMC893, BBOX13, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, PCI_HA_DEVICE_13, GNR_VALID_OPTIONS_UNCORE}, + {"M2M13C1", PMC894, BBOX13, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, PCI_HA_DEVICE_13, GNR_VALID_OPTIONS_UNCORE}, + {"M2M13C2", PMC895, BBOX13, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, PCI_HA_DEVICE_13, GNR_VALID_OPTIONS_UNCORE}, + {"M2M13C3", PMC896, BBOX13, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, PCI_HA_DEVICE_13, GNR_VALID_OPTIONS_UNCORE}, + {"M2M14C0", PMC897, BBOX14, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, PCI_HA_DEVICE_14, GNR_VALID_OPTIONS_UNCORE}, + {"M2M14C1", PMC898, BBOX14, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, PCI_HA_DEVICE_14, GNR_VALID_OPTIONS_UNCORE}, + {"M2M14C2", PMC899, BBOX14, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, PCI_HA_DEVICE_14, GNR_VALID_OPTIONS_UNCORE}, + {"M2M14C3", PMC900, BBOX14, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, PCI_HA_DEVICE_14, GNR_VALID_OPTIONS_UNCORE}, + {"M2M15C0", PMC901, BBOX15, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, PCI_HA_DEVICE_15, GNR_VALID_OPTIONS_UNCORE}, + {"M2M15C1", PMC902, BBOX15, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, PCI_HA_DEVICE_15, GNR_VALID_OPTIONS_UNCORE}, + {"M2M15C2", PMC903, BBOX15, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, PCI_HA_DEVICE_15, GNR_VALID_OPTIONS_UNCORE}, + {"M2M15C3", PMC904, BBOX15, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, PCI_HA_DEVICE_15, GNR_VALID_OPTIONS_UNCORE}, + {"M2M16C0", PMC905, BBOX16, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, PCI_HA_DEVICE_16, GNR_VALID_OPTIONS_UNCORE}, + {"M2M16C1", PMC906, BBOX16, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, PCI_HA_DEVICE_16, GNR_VALID_OPTIONS_UNCORE}, + {"M2M16C2", PMC907, BBOX16, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, PCI_HA_DEVICE_16, GNR_VALID_OPTIONS_UNCORE}, + {"M2M16C3", PMC908, BBOX16, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, PCI_HA_DEVICE_16, GNR_VALID_OPTIONS_UNCORE}, + {"M2M17C0", PMC909, BBOX17, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, PCI_HA_DEVICE_17, GNR_VALID_OPTIONS_UNCORE}, + {"M2M17C1", PMC910, BBOX17, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, PCI_HA_DEVICE_17, GNR_VALID_OPTIONS_UNCORE}, + {"M2M17C2", PMC911, BBOX17, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, PCI_HA_DEVICE_17, GNR_VALID_OPTIONS_UNCORE}, + {"M2M17C3", PMC912, BBOX17, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, PCI_HA_DEVICE_17, GNR_VALID_OPTIONS_UNCORE}, + {"M2M18C0", PMC913, BBOX18, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, PCI_HA_DEVICE_18, GNR_VALID_OPTIONS_UNCORE}, + {"M2M18C1", PMC914, BBOX18, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, PCI_HA_DEVICE_18, GNR_VALID_OPTIONS_UNCORE}, + {"M2M18C2", PMC915, BBOX18, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, PCI_HA_DEVICE_18, GNR_VALID_OPTIONS_UNCORE}, + {"M2M18C3", PMC916, BBOX18, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, PCI_HA_DEVICE_18, GNR_VALID_OPTIONS_UNCORE}, + {"M2M19C0", PMC917, BBOX19, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, PCI_HA_DEVICE_19, GNR_VALID_OPTIONS_UNCORE}, + {"M2M19C1", PMC918, BBOX19, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, PCI_HA_DEVICE_19, GNR_VALID_OPTIONS_UNCORE}, + {"M2M19C2", PMC919, BBOX19, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, PCI_HA_DEVICE_19, GNR_VALID_OPTIONS_UNCORE}, + {"M2M19C3", PMC920, BBOX19, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, PCI_HA_DEVICE_19, GNR_VALID_OPTIONS_UNCORE}, + {"M2M20C0", PMC921, BBOX20, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, PCI_HA_DEVICE_20, GNR_VALID_OPTIONS_UNCORE}, + {"M2M20C1", PMC922, BBOX20, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, PCI_HA_DEVICE_20, GNR_VALID_OPTIONS_UNCORE}, + {"M2M20C2", PMC923, BBOX20, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, PCI_HA_DEVICE_20, GNR_VALID_OPTIONS_UNCORE}, + {"M2M20C3", PMC924, BBOX20, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, PCI_HA_DEVICE_20, GNR_VALID_OPTIONS_UNCORE}, + {"M2M21C0", PMC925, BBOX21, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, PCI_HA_DEVICE_21, GNR_VALID_OPTIONS_UNCORE}, + {"M2M21C1", PMC926, BBOX21, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, PCI_HA_DEVICE_21, GNR_VALID_OPTIONS_UNCORE}, + {"M2M21C2", PMC927, BBOX21, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, PCI_HA_DEVICE_21, GNR_VALID_OPTIONS_UNCORE}, + {"M2M21C3", PMC928, BBOX21, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, PCI_HA_DEVICE_21, GNR_VALID_OPTIONS_UNCORE}, + {"M2M22C0", PMC929, BBOX22, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, PCI_HA_DEVICE_22, GNR_VALID_OPTIONS_UNCORE}, + {"M2M22C1", PMC930, BBOX22, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, PCI_HA_DEVICE_22, GNR_VALID_OPTIONS_UNCORE}, + {"M2M22C2", PMC931, BBOX22, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, PCI_HA_DEVICE_22, GNR_VALID_OPTIONS_UNCORE}, + {"M2M22C3", PMC932, BBOX22, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, PCI_HA_DEVICE_22, GNR_VALID_OPTIONS_UNCORE}, + {"M2M23C0", PMC933, BBOX23, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, PCI_HA_DEVICE_23, GNR_VALID_OPTIONS_UNCORE}, + {"M2M23C1", PMC934, BBOX23, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, PCI_HA_DEVICE_23, GNR_VALID_OPTIONS_UNCORE}, + {"M2M23C2", PMC935, BBOX23, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, PCI_HA_DEVICE_23, GNR_VALID_OPTIONS_UNCORE}, + {"M2M23C3", PMC936, BBOX23, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, PCI_HA_DEVICE_23, GNR_VALID_OPTIONS_UNCORE}, + {"M2M24C0", PMC937, BBOX24, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, PCI_HA_DEVICE_24, GNR_VALID_OPTIONS_UNCORE}, + {"M2M24C1", PMC938, BBOX24, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, PCI_HA_DEVICE_24, GNR_VALID_OPTIONS_UNCORE}, + {"M2M24C2", PMC939, BBOX24, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, PCI_HA_DEVICE_24, GNR_VALID_OPTIONS_UNCORE}, + {"M2M24C3", PMC940, BBOX24, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, PCI_HA_DEVICE_24, GNR_VALID_OPTIONS_UNCORE}, + {"M2M25C0", PMC941, BBOX25, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, PCI_HA_DEVICE_25, GNR_VALID_OPTIONS_UNCORE}, + {"M2M25C1", PMC942, BBOX25, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, PCI_HA_DEVICE_25, GNR_VALID_OPTIONS_UNCORE}, + {"M2M25C2", PMC943, BBOX25, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, PCI_HA_DEVICE_25, GNR_VALID_OPTIONS_UNCORE}, + {"M2M25C3", PMC944, BBOX25, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, PCI_HA_DEVICE_25, GNR_VALID_OPTIONS_UNCORE}, + {"M2M26C0", PMC945, BBOX26, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, PCI_HA_DEVICE_26, GNR_VALID_OPTIONS_UNCORE}, + {"M2M26C1", PMC946, BBOX26, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, PCI_HA_DEVICE_26, GNR_VALID_OPTIONS_UNCORE}, + {"M2M26C2", PMC947, BBOX26, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, PCI_HA_DEVICE_26, GNR_VALID_OPTIONS_UNCORE}, + {"M2M26C3", PMC948, BBOX26, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, PCI_HA_DEVICE_26, GNR_VALID_OPTIONS_UNCORE}, + {"M2M27C0", PMC949, BBOX27, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, PCI_HA_DEVICE_27, GNR_VALID_OPTIONS_UNCORE}, + {"M2M27C1", PMC950, BBOX27, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, PCI_HA_DEVICE_27, GNR_VALID_OPTIONS_UNCORE}, + {"M2M27C2", PMC951, BBOX27, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, PCI_HA_DEVICE_27, GNR_VALID_OPTIONS_UNCORE}, + {"M2M27C3", PMC952, BBOX27, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, PCI_HA_DEVICE_27, GNR_VALID_OPTIONS_UNCORE}, + {"M2M28C0", PMC953, BBOX28, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, PCI_HA_DEVICE_28, GNR_VALID_OPTIONS_UNCORE}, + {"M2M28C1", PMC954, BBOX28, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, PCI_HA_DEVICE_28, GNR_VALID_OPTIONS_UNCORE}, + {"M2M28C2", PMC955, BBOX28, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, PCI_HA_DEVICE_28, GNR_VALID_OPTIONS_UNCORE}, + {"M2M28C3", PMC956, BBOX28, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, PCI_HA_DEVICE_28, GNR_VALID_OPTIONS_UNCORE}, + {"M2M29C0", PMC957, BBOX29, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, PCI_HA_DEVICE_29, GNR_VALID_OPTIONS_UNCORE}, + {"M2M29C1", PMC958, BBOX29, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, PCI_HA_DEVICE_29, GNR_VALID_OPTIONS_UNCORE}, + {"M2M29C2", PMC959, BBOX29, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, PCI_HA_DEVICE_29, GNR_VALID_OPTIONS_UNCORE}, + {"M2M29C3", PMC960, BBOX29, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, PCI_HA_DEVICE_29, GNR_VALID_OPTIONS_UNCORE}, + {"M2M30C0", PMC961, BBOX30, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, PCI_HA_DEVICE_30, GNR_VALID_OPTIONS_UNCORE}, + {"M2M30C1", PMC962, BBOX30, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, PCI_HA_DEVICE_30, GNR_VALID_OPTIONS_UNCORE}, + {"M2M30C2", PMC963, BBOX30, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, PCI_HA_DEVICE_30, GNR_VALID_OPTIONS_UNCORE}, + {"M2M30C3", PMC964, BBOX30, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, PCI_HA_DEVICE_30, GNR_VALID_OPTIONS_UNCORE}, + {"M2M31C0", PMC965, BBOX31, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, PCI_HA_DEVICE_31, GNR_VALID_OPTIONS_UNCORE}, + {"M2M31C1", PMC966, BBOX31, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, PCI_HA_DEVICE_31, GNR_VALID_OPTIONS_UNCORE}, + {"M2M31C2", PMC967, BBOX31, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, PCI_HA_DEVICE_31, GNR_VALID_OPTIONS_UNCORE}, + {"M2M31C3", PMC968, BBOX31, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, PCI_HA_DEVICE_31, GNR_VALID_OPTIONS_UNCORE}, + {"RBOX0C0", PMC969, RBOX0, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, PCI_R3QPI_DEVICE_LINK_0, GNR_VALID_OPTIONS_UNCORE}, + {"RBOX0C1", PMC970, RBOX0, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, PCI_R3QPI_DEVICE_LINK_0, GNR_VALID_OPTIONS_UNCORE}, + {"RBOX0C2", PMC971, RBOX0, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, PCI_R3QPI_DEVICE_LINK_0, GNR_VALID_OPTIONS_UNCORE}, + {"RBOX0C3", PMC972, RBOX0, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, PCI_R3QPI_DEVICE_LINK_0, GNR_VALID_OPTIONS_UNCORE}, + {"RBOX1C0", PMC973, RBOX1, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, PCI_R3QPI_DEVICE_LINK_1, GNR_VALID_OPTIONS_UNCORE}, + {"RBOX1C1", PMC974, RBOX1, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, PCI_R3QPI_DEVICE_LINK_1, GNR_VALID_OPTIONS_UNCORE}, + {"RBOX1C2", PMC975, RBOX1, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, PCI_R3QPI_DEVICE_LINK_1, GNR_VALID_OPTIONS_UNCORE}, + {"RBOX1C3", PMC976, RBOX1, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, PCI_R3QPI_DEVICE_LINK_1, GNR_VALID_OPTIONS_UNCORE}, + {"RBOX2C0", PMC977, RBOX2, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, PCI_R3QPI_DEVICE_LINK_2, GNR_VALID_OPTIONS_UNCORE}, + {"RBOX2C1", PMC978, RBOX2, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, PCI_R3QPI_DEVICE_LINK_2, GNR_VALID_OPTIONS_UNCORE}, + {"RBOX2C2", PMC979, RBOX2, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, PCI_R3QPI_DEVICE_LINK_2, GNR_VALID_OPTIONS_UNCORE}, + {"RBOX2C3", PMC980, RBOX2, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, PCI_R3QPI_DEVICE_LINK_2, GNR_VALID_OPTIONS_UNCORE}, + {"RBOX3C0", PMC981, RBOX3, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, PCI_R3QPI_DEVICE_LINK_3, GNR_VALID_OPTIONS_UNCORE}, + {"RBOX3C1", PMC982, RBOX3, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, PCI_R3QPI_DEVICE_LINK_3, GNR_VALID_OPTIONS_UNCORE}, + {"RBOX3C2", PMC983, RBOX3, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, PCI_R3QPI_DEVICE_LINK_3, GNR_VALID_OPTIONS_UNCORE}, + {"RBOX3C3", PMC984, RBOX3, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, PCI_R3QPI_DEVICE_LINK_3, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX0C0", PMC985, PBOX0, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, PCI_R2PCIE_DEVICE0, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX0C1", PMC986, PBOX0, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, PCI_R2PCIE_DEVICE0, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX0C2", PMC987, PBOX0, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, PCI_R2PCIE_DEVICE0, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX0C3", PMC988, PBOX0, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, PCI_R2PCIE_DEVICE0, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX1C0", PMC989, PBOX1, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, PCI_R2PCIE_DEVICE1, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX1C1", PMC990, PBOX1, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, PCI_R2PCIE_DEVICE1, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX1C2", PMC991, PBOX1, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, PCI_R2PCIE_DEVICE1, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX1C3", PMC992, PBOX1, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, PCI_R2PCIE_DEVICE1, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX2C0", PMC993, PBOX2, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, PCI_R2PCIE_DEVICE2, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX2C1", PMC994, PBOX2, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, PCI_R2PCIE_DEVICE2, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX2C2", PMC995, PBOX2, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, PCI_R2PCIE_DEVICE2, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX2C3", PMC996, PBOX2, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, PCI_R2PCIE_DEVICE2, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX3C0", PMC997, PBOX3, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, PCI_R2PCIE_DEVICE3, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX3C1", PMC998, PBOX3, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, PCI_R2PCIE_DEVICE3, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX3C2", PMC999, PBOX3, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, PCI_R2PCIE_DEVICE3, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX3C3", PMC1000, PBOX3, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, PCI_R2PCIE_DEVICE3, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX4C0", PMC1001, PBOX4, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, PCI_R2PCIE_DEVICE4, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX4C1", PMC1002, PBOX4, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, PCI_R2PCIE_DEVICE4, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX4C2", PMC1003, PBOX4, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, PCI_R2PCIE_DEVICE4, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX4C3", PMC1004, PBOX4, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, PCI_R2PCIE_DEVICE4, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX5C0", PMC1005, PBOX5, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, PCI_R2PCIE_DEVICE5, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX5C1", PMC1006, PBOX5, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, PCI_R2PCIE_DEVICE5, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX5C2", PMC1007, PBOX5, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, PCI_R2PCIE_DEVICE5, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX5C3", PMC1008, PBOX5, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, PCI_R2PCIE_DEVICE5, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX6C0", PMC1009, PBOX6, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, PCI_R2PCIE_DEVICE6, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX6C1", PMC1010, PBOX6, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, PCI_R2PCIE_DEVICE6, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX6C2", PMC1011, PBOX6, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, PCI_R2PCIE_DEVICE6, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX6C3", PMC1012, PBOX6, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, PCI_R2PCIE_DEVICE6, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX7C0", PMC1013, PBOX7, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, PCI_R2PCIE_DEVICE7, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX7C1", PMC1014, PBOX7, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, PCI_R2PCIE_DEVICE7, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX7C2", PMC1015, PBOX7, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, PCI_R2PCIE_DEVICE7, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX7C3", PMC1016, PBOX7, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, PCI_R2PCIE_DEVICE7, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX8C0", PMC1017, PBOX8, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, PCI_R2PCIE_DEVICE8, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX8C1", PMC1018, PBOX8, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, PCI_R2PCIE_DEVICE8, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX8C2", PMC1019, PBOX8, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, PCI_R2PCIE_DEVICE8, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX8C3", PMC1020, PBOX8, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, PCI_R2PCIE_DEVICE8, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX9C0", PMC1021, PBOX9, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, PCI_R2PCIE_DEVICE9, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX9C1", PMC1022, PBOX9, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, PCI_R2PCIE_DEVICE9, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX9C2", PMC1023, PBOX9, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, PCI_R2PCIE_DEVICE9, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX9C3", PMC1024, PBOX9, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, PCI_R2PCIE_DEVICE9, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX10C0", PMC1025, PBOX10, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, PCI_R2PCIE_DEVICE10, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX10C1", PMC1026, PBOX10, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, PCI_R2PCIE_DEVICE10, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX10C2", PMC1027, PBOX10, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, PCI_R2PCIE_DEVICE10, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX10C3", PMC1028, PBOX10, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, PCI_R2PCIE_DEVICE10, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX11C0", PMC1029, PBOX11, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, PCI_R2PCIE_DEVICE11, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX11C1", PMC1030, PBOX11, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, PCI_R2PCIE_DEVICE11, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX11C2", PMC1031, PBOX11, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, PCI_R2PCIE_DEVICE11, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX11C3", PMC1032, PBOX11, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, PCI_R2PCIE_DEVICE11, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX12C0", PMC1033, PBOX12, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, PCI_R2PCIE_DEVICE12, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX12C1", PMC1034, PBOX12, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, PCI_R2PCIE_DEVICE12, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX12C2", PMC1035, PBOX12, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, PCI_R2PCIE_DEVICE12, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX12C3", PMC1036, PBOX12, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, PCI_R2PCIE_DEVICE12, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX13C0", PMC1037, PBOX13, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, PCI_R2PCIE_DEVICE13, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX13C1", PMC1038, PBOX13, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, PCI_R2PCIE_DEVICE13, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX13C2", PMC1039, PBOX13, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, PCI_R2PCIE_DEVICE13, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX13C3", PMC1040, PBOX13, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, PCI_R2PCIE_DEVICE13, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX14C0", PMC1041, PBOX14, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, PCI_R2PCIE_DEVICE14, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX14C1", PMC1042, PBOX14, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, PCI_R2PCIE_DEVICE14, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX14C2", PMC1043, PBOX14, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, PCI_R2PCIE_DEVICE14, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX14C3", PMC1044, PBOX14, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, PCI_R2PCIE_DEVICE14, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX15C0", PMC1045, PBOX15, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, PCI_R2PCIE_DEVICE15, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX15C1", PMC1046, PBOX15, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, PCI_R2PCIE_DEVICE15, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX15C2", PMC1047, PBOX15, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, PCI_R2PCIE_DEVICE15, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX15C3", PMC1048, PBOX15, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, PCI_R2PCIE_DEVICE15, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX16C0", PMC1049, PBOX16, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, PCI_R2PCIE_DEVICE16, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX16C1", PMC1050, PBOX16, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, PCI_R2PCIE_DEVICE16, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX16C2", PMC1051, PBOX16, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, PCI_R2PCIE_DEVICE16, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX16C3", PMC1052, PBOX16, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, PCI_R2PCIE_DEVICE16, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX17C0", PMC1053, PBOX17, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, PCI_R2PCIE_DEVICE17, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX17C1", PMC1054, PBOX17, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, PCI_R2PCIE_DEVICE17, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX17C2", PMC1055, PBOX17, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, PCI_R2PCIE_DEVICE17, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX17C3", PMC1056, PBOX17, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, PCI_R2PCIE_DEVICE17, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX18C0", PMC1057, PBOX18, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, PCI_R2PCIE_DEVICE18, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX18C1", PMC1058, PBOX18, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, PCI_R2PCIE_DEVICE18, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX18C2", PMC1059, PBOX18, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, PCI_R2PCIE_DEVICE18, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX18C3", PMC1060, PBOX18, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, PCI_R2PCIE_DEVICE18, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX19C0", PMC1061, PBOX19, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, PCI_R2PCIE_DEVICE19, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX19C1", PMC1062, PBOX19, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, PCI_R2PCIE_DEVICE19, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX19C2", PMC1063, PBOX19, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, PCI_R2PCIE_DEVICE19, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX19C3", PMC1064, PBOX19, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, PCI_R2PCIE_DEVICE19, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX20C0", PMC1065, PBOX20, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, PCI_R2PCIE_DEVICE20, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX20C1", PMC1066, PBOX20, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, PCI_R2PCIE_DEVICE20, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX20C2", PMC1067, PBOX20, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, PCI_R2PCIE_DEVICE20, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX20C3", PMC1068, PBOX20, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, PCI_R2PCIE_DEVICE20, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX21C0", PMC1069, PBOX21, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, PCI_R2PCIE_DEVICE21, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX21C1", PMC1070, PBOX21, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, PCI_R2PCIE_DEVICE21, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX21C2", PMC1071, PBOX21, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, PCI_R2PCIE_DEVICE21, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX21C3", PMC1072, PBOX21, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, PCI_R2PCIE_DEVICE21, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX22C0", PMC1073, PBOX22, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, PCI_R2PCIE_DEVICE22, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX22C1", PMC1074, PBOX22, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, PCI_R2PCIE_DEVICE22, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX22C2", PMC1075, PBOX22, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, PCI_R2PCIE_DEVICE22, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX22C3", PMC1076, PBOX22, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, PCI_R2PCIE_DEVICE22, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX23C0", PMC1077, PBOX23, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, PCI_R2PCIE_DEVICE23, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX23C1", PMC1078, PBOX23, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, PCI_R2PCIE_DEVICE23, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX23C2", PMC1079, PBOX23, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, PCI_R2PCIE_DEVICE23, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX23C3", PMC1080, PBOX23, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, PCI_R2PCIE_DEVICE23, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX24C0", PMC1081, PBOX24, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, PCI_R2PCIE_DEVICE24, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX24C1", PMC1082, PBOX24, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, PCI_R2PCIE_DEVICE24, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX24C2", PMC1083, PBOX24, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, PCI_R2PCIE_DEVICE24, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX24C3", PMC1084, PBOX24, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, PCI_R2PCIE_DEVICE24, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX25C0", PMC1085, PBOX25, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, PCI_R2PCIE_DEVICE25, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX25C1", PMC1086, PBOX25, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, PCI_R2PCIE_DEVICE25, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX25C2", PMC1087, PBOX25, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, PCI_R2PCIE_DEVICE25, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX25C3", PMC1088, PBOX25, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, PCI_R2PCIE_DEVICE25, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX26C0", PMC1089, PBOX26, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, PCI_R2PCIE_DEVICE26, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX26C1", PMC1090, PBOX26, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, PCI_R2PCIE_DEVICE26, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX26C2", PMC1091, PBOX26, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, PCI_R2PCIE_DEVICE26, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX26C3", PMC1092, PBOX26, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, PCI_R2PCIE_DEVICE26, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX27C0", PMC1093, PBOX27, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, PCI_R2PCIE_DEVICE27, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX27C1", PMC1094, PBOX27, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, PCI_R2PCIE_DEVICE27, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX27C2", PMC1095, PBOX27, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, PCI_R2PCIE_DEVICE27, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX27C3", PMC1096, PBOX27, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, PCI_R2PCIE_DEVICE27, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX28C0", PMC1097, PBOX28, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, PCI_R2PCIE_DEVICE28, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX28C1", PMC1098, PBOX28, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, PCI_R2PCIE_DEVICE28, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX28C2", PMC1099, PBOX28, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, PCI_R2PCIE_DEVICE28, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX28C3", PMC1100, PBOX28, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, PCI_R2PCIE_DEVICE28, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX29C0", PMC1101, PBOX29, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, PCI_R2PCIE_DEVICE29, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX29C1", PMC1102, PBOX29, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, PCI_R2PCIE_DEVICE29, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX29C2", PMC1103, PBOX29, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, PCI_R2PCIE_DEVICE29, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX29C3", PMC1104, PBOX29, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, PCI_R2PCIE_DEVICE29, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX30C0", PMC1105, PBOX30, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, PCI_R2PCIE_DEVICE30, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX30C1", PMC1106, PBOX30, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, PCI_R2PCIE_DEVICE30, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX30C2", PMC1107, PBOX30, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, PCI_R2PCIE_DEVICE30, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX30C3", PMC1108, PBOX30, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, PCI_R2PCIE_DEVICE30, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX31C0", PMC1109, PBOX31, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, PCI_R2PCIE_DEVICE31, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX31C1", PMC1110, PBOX31, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, PCI_R2PCIE_DEVICE31, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX31C2", PMC1111, PBOX31, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, PCI_R2PCIE_DEVICE31, GNR_VALID_OPTIONS_UNCORE}, + {"PBOX31C3", PMC1112, PBOX31, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, PCI_R2PCIE_DEVICE31, GNR_VALID_OPTIONS_UNCORE}, + {"PCU1C0", PMC1113, WBOX1, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_PCU_DEVICE_1, SPR_VALID_OPTIONS_UNCORE}, + {"PCU1C1", PMC1114, WBOX1, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_PCU_DEVICE_1, SPR_VALID_OPTIONS_UNCORE}, + {"PCU1C2", PMC1115, WBOX1, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_PCU_DEVICE_1, SPR_VALID_OPTIONS_UNCORE}, + {"PCU1C3", PMC1116, WBOX1, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_PCU_DEVICE_1, SPR_VALID_OPTIONS_UNCORE}, + {"PCU2C0", PMC1117, WBOX2, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_PCU_DEVICE_2, SPR_VALID_OPTIONS_UNCORE}, + {"PCU2C1", PMC1118, WBOX2, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_PCU_DEVICE_2, SPR_VALID_OPTIONS_UNCORE}, + {"PCU2C2", PMC1119, WBOX2, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_PCU_DEVICE_2, SPR_VALID_OPTIONS_UNCORE}, + {"PCU2C3", PMC1120, WBOX2, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_PCU_DEVICE_2, SPR_VALID_OPTIONS_UNCORE}, + {"PCU3C0", PMC1121, WBOX3, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_PCU_DEVICE_3, SPR_VALID_OPTIONS_UNCORE}, + {"PCU3C1", PMC1122, WBOX3, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_PCU_DEVICE_3, SPR_VALID_OPTIONS_UNCORE}, + {"PCU3C2", PMC1123, WBOX3, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_PCU_DEVICE_3, SPR_VALID_OPTIONS_UNCORE}, + {"PCU3C3", PMC1124, WBOX3, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_PCU_DEVICE_3, SPR_VALID_OPTIONS_UNCORE}, + {"IRP0C0", PMC1125, IRP0, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_IRP_DEVICE_0, GNR_VALID_OPTIONS_UNCORE}, + {"IRP0C1", PMC1126, IRP0, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_IRP_DEVICE_0, GNR_VALID_OPTIONS_UNCORE}, + {"IRP0C2", PMC1127, IRP0, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_IRP_DEVICE_0, GNR_VALID_OPTIONS_UNCORE}, + {"IRP0C3", PMC1128, IRP0, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_IRP_DEVICE_0, GNR_VALID_OPTIONS_UNCORE}, + {"IRP1C0", PMC1129, IRP1, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_IRP_DEVICE_1, GNR_VALID_OPTIONS_UNCORE}, + {"IRP1C1", PMC1130, IRP1, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_IRP_DEVICE_1, GNR_VALID_OPTIONS_UNCORE}, + {"IRP1C2", PMC1131, IRP1, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_IRP_DEVICE_1, GNR_VALID_OPTIONS_UNCORE}, + {"IRP1C3", PMC1132, IRP1, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_IRP_DEVICE_1, GNR_VALID_OPTIONS_UNCORE}, + {"IRP2C0", PMC1133, IRP2, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_IRP_DEVICE_2, GNR_VALID_OPTIONS_UNCORE}, + {"IRP2C1", PMC1134, IRP2, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_IRP_DEVICE_2, GNR_VALID_OPTIONS_UNCORE}, + {"IRP2C2", PMC1135, IRP2, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_IRP_DEVICE_2, GNR_VALID_OPTIONS_UNCORE}, + {"IRP2C3", PMC1136, IRP2, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_IRP_DEVICE_2, GNR_VALID_OPTIONS_UNCORE}, + {"IRP3C0", PMC1137, IRP3, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_IRP_DEVICE_3, GNR_VALID_OPTIONS_UNCORE}, + {"IRP3C1", PMC1138, IRP3, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_IRP_DEVICE_3, GNR_VALID_OPTIONS_UNCORE}, + {"IRP3C2", PMC1139, IRP3, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_IRP_DEVICE_3, GNR_VALID_OPTIONS_UNCORE}, + {"IRP3C3", PMC1140, IRP3, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_IRP_DEVICE_3, GNR_VALID_OPTIONS_UNCORE}, + {"IRP4C0", PMC1141, IRP4, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_IRP_DEVICE_4, GNR_VALID_OPTIONS_UNCORE}, + {"IRP4C1", PMC1142, IRP4, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_IRP_DEVICE_4, GNR_VALID_OPTIONS_UNCORE}, + {"IRP4C2", PMC1143, IRP4, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_IRP_DEVICE_4, GNR_VALID_OPTIONS_UNCORE}, + {"IRP4C3", PMC1144, IRP4, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_IRP_DEVICE_4, GNR_VALID_OPTIONS_UNCORE}, + {"IRP5C0", PMC1145, IRP5, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_IRP_DEVICE_5, GNR_VALID_OPTIONS_UNCORE}, + {"IRP5C1", PMC1146, IRP5, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_IRP_DEVICE_5, GNR_VALID_OPTIONS_UNCORE}, + {"IRP5C2", PMC1147, IRP5, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_IRP_DEVICE_5, GNR_VALID_OPTIONS_UNCORE}, + {"IRP5C3", PMC1148, IRP5, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_IRP_DEVICE_5, GNR_VALID_OPTIONS_UNCORE}, + {"IRP6C0", PMC1149, IRP6, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_IRP_DEVICE_6, GNR_VALID_OPTIONS_UNCORE}, + {"IRP6C1", PMC1150, IRP6, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_IRP_DEVICE_6, GNR_VALID_OPTIONS_UNCORE}, + {"IRP6C2", PMC1151, IRP6, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_IRP_DEVICE_6, GNR_VALID_OPTIONS_UNCORE}, + {"IRP6C3", PMC1152, IRP6, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_IRP_DEVICE_6, GNR_VALID_OPTIONS_UNCORE}, + {"IRP7C0", PMC1153, IRP7, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_IRP_DEVICE_7, GNR_VALID_OPTIONS_UNCORE}, + {"IRP7C1", PMC1154, IRP7, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_IRP_DEVICE_7, GNR_VALID_OPTIONS_UNCORE}, + {"IRP7C2", PMC1155, IRP7, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_IRP_DEVICE_7, GNR_VALID_OPTIONS_UNCORE}, + {"IRP7C3", PMC1156, IRP7, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_IRP_DEVICE_7, GNR_VALID_OPTIONS_UNCORE}, + {"IRP8C0", PMC1157, IRP8, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_IRP_DEVICE_8, GNR_VALID_OPTIONS_UNCORE}, + {"IRP8C1", PMC1158, IRP8, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_IRP_DEVICE_8, GNR_VALID_OPTIONS_UNCORE}, + {"IRP8C2", PMC1159, IRP8, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_IRP_DEVICE_8, GNR_VALID_OPTIONS_UNCORE}, + {"IRP8C3", PMC1160, IRP8, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_IRP_DEVICE_8, GNR_VALID_OPTIONS_UNCORE}, + {"IRP9C0", PMC1161, IRP9, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_IRP_DEVICE_9, GNR_VALID_OPTIONS_UNCORE}, + {"IRP9C1", PMC1162, IRP9, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_IRP_DEVICE_9, GNR_VALID_OPTIONS_UNCORE}, + {"IRP9C2", PMC1163, IRP9, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_IRP_DEVICE_9, GNR_VALID_OPTIONS_UNCORE}, + {"IRP9C3", PMC1164, IRP9, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_IRP_DEVICE_9, GNR_VALID_OPTIONS_UNCORE}, + {"IRP10C0", PMC1165, IRP10, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_IRP_DEVICE_10, GNR_VALID_OPTIONS_UNCORE}, + {"IRP10C1", PMC1166, IRP10, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_IRP_DEVICE_10, GNR_VALID_OPTIONS_UNCORE}, + {"IRP10C2", PMC1167, IRP10, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_IRP_DEVICE_10, GNR_VALID_OPTIONS_UNCORE}, + {"IRP10C3", PMC1168, IRP10, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_IRP_DEVICE_10, GNR_VALID_OPTIONS_UNCORE}, + {"IRP11C0", PMC1169, IRP11, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_IRP_DEVICE_11, GNR_VALID_OPTIONS_UNCORE}, + {"IRP11C1", PMC1170, IRP11, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_IRP_DEVICE_11, GNR_VALID_OPTIONS_UNCORE}, + {"IRP11C2", PMC1171, IRP11, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_IRP_DEVICE_11, GNR_VALID_OPTIONS_UNCORE}, + {"IRP11C3", PMC1172, IRP11, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_IRP_DEVICE_11, GNR_VALID_OPTIONS_UNCORE}, + {"IRP12C0", PMC1173, IRP12, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_IRP_DEVICE_12, GNR_VALID_OPTIONS_UNCORE}, + {"IRP12C1", PMC1174, IRP12, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_IRP_DEVICE_12, GNR_VALID_OPTIONS_UNCORE}, + {"IRP12C2", PMC1175, IRP12, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_IRP_DEVICE_12, GNR_VALID_OPTIONS_UNCORE}, + {"IRP12C3", PMC1176, IRP12, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_IRP_DEVICE_12, GNR_VALID_OPTIONS_UNCORE}, + {"IRP13C0", PMC1177, IRP13, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_IRP_DEVICE_13, GNR_VALID_OPTIONS_UNCORE}, + {"IRP13C1", PMC1178, IRP13, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_IRP_DEVICE_13, GNR_VALID_OPTIONS_UNCORE}, + {"IRP13C2", PMC1179, IRP13, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_IRP_DEVICE_13, GNR_VALID_OPTIONS_UNCORE}, + {"IRP13C3", PMC1180, IRP13, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_IRP_DEVICE_13, GNR_VALID_OPTIONS_UNCORE}, + {"IRP14C0", PMC1181, IRP14, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_IRP_DEVICE_14, GNR_VALID_OPTIONS_UNCORE}, + {"IRP14C1", PMC1182, IRP14, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_IRP_DEVICE_14, GNR_VALID_OPTIONS_UNCORE}, + {"IRP14C2", PMC1183, IRP14, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_IRP_DEVICE_14, GNR_VALID_OPTIONS_UNCORE}, + {"IRP14C3", PMC1184, IRP14, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_IRP_DEVICE_14, GNR_VALID_OPTIONS_UNCORE}, + {"IRP15C0", PMC1185, IRP15, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_IRP_DEVICE_15, GNR_VALID_OPTIONS_UNCORE}, + {"IRP15C1", PMC1186, IRP15, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_IRP_DEVICE_15, GNR_VALID_OPTIONS_UNCORE}, + {"IRP15C2", PMC1187, IRP15, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_IRP_DEVICE_15, GNR_VALID_OPTIONS_UNCORE}, + {"IRP15C3", PMC1188, IRP15, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_IRP_DEVICE_15, GNR_VALID_OPTIONS_UNCORE}, + {"IBOX0C0", PMC1189, IBOX0, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_IIO_DEVICE_0, GNR_VALID_OPTIONS_UNCORE}, + {"IBOX0C1", PMC1190, IBOX0, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_IIO_DEVICE_0, GNR_VALID_OPTIONS_UNCORE}, + {"IBOX0C2", PMC1191, IBOX0, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_IIO_DEVICE_0, GNR_VALID_OPTIONS_UNCORE}, + {"IBOX0C3", PMC1192, IBOX0, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_IIO_DEVICE_0, GNR_VALID_OPTIONS_UNCORE}, + {"IBOX1C0", PMC1193, IBOX1, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_IIO_DEVICE_1, GNR_VALID_OPTIONS_UNCORE}, + {"IBOX1C1", PMC1194, IBOX1, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_IIO_DEVICE_1, GNR_VALID_OPTIONS_UNCORE}, + {"IBOX1C2", PMC1195, IBOX1, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_IIO_DEVICE_1, GNR_VALID_OPTIONS_UNCORE}, + {"IBOX1C3", PMC1196, IBOX1, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_IIO_DEVICE_1, GNR_VALID_OPTIONS_UNCORE}, + {"IBOX2C0", PMC1197, IBOX2, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_IIO_DEVICE_2, GNR_VALID_OPTIONS_UNCORE}, + {"IBOX2C1", PMC1198, IBOX2, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_IIO_DEVICE_2, GNR_VALID_OPTIONS_UNCORE}, + {"IBOX2C2", PMC1199, IBOX2, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_IIO_DEVICE_2, GNR_VALID_OPTIONS_UNCORE}, + {"IBOX2C3", PMC1200, IBOX2, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_IIO_DEVICE_2, GNR_VALID_OPTIONS_UNCORE}, + {"IBOX3C0", PMC1201, IBOX3, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_IIO_DEVICE_3, GNR_VALID_OPTIONS_UNCORE}, + {"IBOX3C1", PMC1202, IBOX3, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_IIO_DEVICE_3, GNR_VALID_OPTIONS_UNCORE}, + {"IBOX3C2", PMC1203, IBOX3, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_IIO_DEVICE_3, GNR_VALID_OPTIONS_UNCORE}, + {"IBOX3C3", PMC1204, IBOX3, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_IIO_DEVICE_3, GNR_VALID_OPTIONS_UNCORE}, + {"IBOX4C0", PMC1205, IBOX4, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_IIO_DEVICE_4, GNR_VALID_OPTIONS_UNCORE}, + {"IBOX4C1", PMC1206, IBOX4, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_IIO_DEVICE_4, GNR_VALID_OPTIONS_UNCORE}, + {"IBOX4C2", PMC1207, IBOX4, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_IIO_DEVICE_4, GNR_VALID_OPTIONS_UNCORE}, + {"IBOX4C3", PMC1208, IBOX4, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_IIO_DEVICE_4, GNR_VALID_OPTIONS_UNCORE}, + {"IBOX5C0", PMC1209, IBOX5, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_IIO_DEVICE_5, GNR_VALID_OPTIONS_UNCORE}, + {"IBOX5C1", PMC1210, IBOX5, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_IIO_DEVICE_5, GNR_VALID_OPTIONS_UNCORE}, + {"IBOX5C2", PMC1211, IBOX5, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_IIO_DEVICE_5, GNR_VALID_OPTIONS_UNCORE}, + {"IBOX5C3", PMC1212, IBOX5, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_IIO_DEVICE_5, GNR_VALID_OPTIONS_UNCORE}, + {"IBOX6C0", PMC1213, IBOX6, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_IIO_DEVICE_6, GNR_VALID_OPTIONS_UNCORE}, + {"IBOX6C1", PMC1214, IBOX6, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_IIO_DEVICE_6, GNR_VALID_OPTIONS_UNCORE}, + {"IBOX6C2", PMC1215, IBOX6, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_IIO_DEVICE_6, GNR_VALID_OPTIONS_UNCORE}, + {"IBOX6C3", PMC1216, IBOX6, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_IIO_DEVICE_6, GNR_VALID_OPTIONS_UNCORE}, + {"IBOX7C0", PMC1217, IBOX7, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_IIO_DEVICE_7, GNR_VALID_OPTIONS_UNCORE}, + {"IBOX7C1", PMC1218, IBOX7, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_IIO_DEVICE_7, GNR_VALID_OPTIONS_UNCORE}, + {"IBOX7C2", PMC1219, IBOX7, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_IIO_DEVICE_7, GNR_VALID_OPTIONS_UNCORE}, + {"IBOX7C3", PMC1220, IBOX7, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_IIO_DEVICE_7, GNR_VALID_OPTIONS_UNCORE}, + {"IBOX8C0", PMC1221, IBOX8, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_IIO_DEVICE_8, GNR_VALID_OPTIONS_UNCORE}, + {"IBOX8C1", PMC1222, IBOX8, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_IIO_DEVICE_8, GNR_VALID_OPTIONS_UNCORE}, + {"IBOX8C2", PMC1223, IBOX8, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_IIO_DEVICE_8, GNR_VALID_OPTIONS_UNCORE}, + {"IBOX8C3", PMC1224, IBOX8, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_IIO_DEVICE_8, GNR_VALID_OPTIONS_UNCORE}, + {"IBOX9C0", PMC1225, IBOX9, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_IIO_DEVICE_9, GNR_VALID_OPTIONS_UNCORE}, + {"IBOX9C1", PMC1226, IBOX9, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_IIO_DEVICE_9, GNR_VALID_OPTIONS_UNCORE}, + {"IBOX9C2", PMC1227, IBOX9, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_IIO_DEVICE_9, GNR_VALID_OPTIONS_UNCORE}, + {"IBOX9C3", PMC1228, IBOX9, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_IIO_DEVICE_9, GNR_VALID_OPTIONS_UNCORE}, + {"IBOX10C0", PMC1229, IBOX10, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_IIO_DEVICE_10, GNR_VALID_OPTIONS_UNCORE}, + {"IBOX10C1", PMC1230, IBOX10, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_IIO_DEVICE_10, GNR_VALID_OPTIONS_UNCORE}, + {"IBOX10C2", PMC1231, IBOX10, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_IIO_DEVICE_10, GNR_VALID_OPTIONS_UNCORE}, + {"IBOX10C3", PMC1232, IBOX10, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_IIO_DEVICE_10, GNR_VALID_OPTIONS_UNCORE}, + {"IBOX11C0", PMC1233, IBOX11, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_IIO_DEVICE_11, GNR_VALID_OPTIONS_UNCORE}, + {"IBOX11C1", PMC1234, IBOX11, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_IIO_DEVICE_11, GNR_VALID_OPTIONS_UNCORE}, + {"IBOX11C2", PMC1235, IBOX11, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_IIO_DEVICE_11, GNR_VALID_OPTIONS_UNCORE}, + {"IBOX11C3", PMC1236, IBOX11, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_IIO_DEVICE_11, GNR_VALID_OPTIONS_UNCORE}, + {"IBOX12C0", PMC1237, IBOX12, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_IIO_DEVICE_12, GNR_VALID_OPTIONS_UNCORE}, + {"IBOX12C1", PMC1238, IBOX12, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_IIO_DEVICE_12, GNR_VALID_OPTIONS_UNCORE}, + {"IBOX12C2", PMC1239, IBOX12, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_IIO_DEVICE_12, GNR_VALID_OPTIONS_UNCORE}, + {"IBOX12C3", PMC1240, IBOX12, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_IIO_DEVICE_12, GNR_VALID_OPTIONS_UNCORE}, + {"IBOX13C0", PMC1241, IBOX13, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_IIO_DEVICE_13, GNR_VALID_OPTIONS_UNCORE}, + {"IBOX13C1", PMC1242, IBOX13, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_IIO_DEVICE_13, GNR_VALID_OPTIONS_UNCORE}, + {"IBOX13C2", PMC1243, IBOX13, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_IIO_DEVICE_13, GNR_VALID_OPTIONS_UNCORE}, + {"IBOX13C3", PMC1244, IBOX13, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_IIO_DEVICE_13, GNR_VALID_OPTIONS_UNCORE}, + {"IBOX14C0", PMC1245, IBOX14, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_IIO_DEVICE_14, GNR_VALID_OPTIONS_UNCORE}, + {"IBOX14C1", PMC1246, IBOX14, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_IIO_DEVICE_14, GNR_VALID_OPTIONS_UNCORE}, + {"IBOX14C2", PMC1247, IBOX14, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_IIO_DEVICE_14, GNR_VALID_OPTIONS_UNCORE}, + {"IBOX14C3", PMC1248, IBOX14, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_IIO_DEVICE_14, GNR_VALID_OPTIONS_UNCORE}, + {"IBOX15C0", PMC1249, IBOX15, FAKE_UNC_CTRL0, FAKE_UNC_CTR0, 0, MSR_IIO_DEVICE_15, GNR_VALID_OPTIONS_UNCORE}, + {"IBOX15C1", PMC1250, IBOX15, FAKE_UNC_CTRL1, FAKE_UNC_CTR1, 0, MSR_IIO_DEVICE_15, GNR_VALID_OPTIONS_UNCORE}, + {"IBOX15C2", PMC1251, IBOX15, FAKE_UNC_CTRL2, FAKE_UNC_CTR2, 0, MSR_IIO_DEVICE_15, GNR_VALID_OPTIONS_UNCORE}, + {"IBOX15C3", PMC1252, IBOX15, FAKE_UNC_CTRL3, FAKE_UNC_CTR3, 0, MSR_IIO_DEVICE_15, GNR_VALID_OPTIONS_UNCORE}, +}; + + +static BoxMap graniterapids_box_map[NUM_UNITS] = { + [FIXED] = {MSR_PERF_GLOBAL_CTRL, MSR_V4_PERF_GLOBAL_STATUS, MSR_V4_PERF_GLOBAL_STATUS_RESET, 0, 0, 0, 48}, + [PMC] = {MSR_PERF_GLOBAL_CTRL, MSR_V4_PERF_GLOBAL_STATUS, MSR_V4_PERF_GLOBAL_STATUS_RESET, 0, 0, 0, 48}, + [THERMAL] = {0, 0, 0, 0, 0, 0, 8}, + [POWER] = {0, 0, 0, 0, 0, 0, 32}, + [VOLTAGE] = {0, 0, 0, 0, 0, 0, 16}, + [METRICS] = {0, MSR_V4_PERF_GLOBAL_STATUS, MSR_V4_PERF_GLOBAL_STATUS, 48, 0, 0, 8}, + [UBOX] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_UBOX_DEVICE, 48}, + [WBOX0] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_PCU_DEVICE_0, 48}, + [WBOX1] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_PCU_DEVICE_1, 48}, + [WBOX2] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_PCU_DEVICE_2, 48}, + [WBOX3] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_PCU_DEVICE_3, 48}, + [MBOX0] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MMIO_IMC_DEVICE_0_CH_0, 48}, + [MBOX1] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MMIO_IMC_DEVICE_0_CH_1, 48}, + [MBOX2] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MMIO_IMC_DEVICE_0_CH_2, 48}, + [MBOX3] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MMIO_IMC_DEVICE_0_CH_3, 48}, + [MBOX4] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MMIO_IMC_DEVICE_0_CH_4, 48}, + [MBOX5] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MMIO_IMC_DEVICE_0_CH_5, 48}, + [MBOX6] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MMIO_IMC_DEVICE_0_CH_6, 48}, + [MBOX7] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MMIO_IMC_DEVICE_0_CH_7, 48}, + [MBOX8] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MMIO_IMC_DEVICE_1_CH_0, 48}, + [MBOX9] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MMIO_IMC_DEVICE_1_CH_1, 48}, + [MBOX10] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MMIO_IMC_DEVICE_1_CH_2, 48}, + [MBOX11] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MMIO_IMC_DEVICE_1_CH_3, 48}, + [MBOX12] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MMIO_IMC_DEVICE_1_CH_4, 48}, + [MBOX13] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MMIO_IMC_DEVICE_1_CH_5, 48}, + [MBOX14] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MMIO_IMC_DEVICE_1_CH_6, 48}, + [MBOX15] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MMIO_IMC_DEVICE_1_CH_7, 48}, + [MDF0] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_MDF_DEVICE_0, 48}, + [MDF1] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_MDF_DEVICE_1, 48}, + [MDF2] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_MDF_DEVICE_2, 48}, + [MDF3] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_MDF_DEVICE_3, 48}, + [MDF4] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_MDF_DEVICE_4, 48}, + [MDF5] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_MDF_DEVICE_5, 48}, + [MDF6] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_MDF_DEVICE_6, 48}, + [MDF7] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_MDF_DEVICE_7, 48}, + [MDF8] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_MDF_DEVICE_8, 48}, + [MDF9] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_MDF_DEVICE_9, 48}, + [MDF10] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_MDF_DEVICE_10, 48}, + [MDF11] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_MDF_DEVICE_11, 48}, + [MDF12] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_MDF_DEVICE_12, 48}, + [MDF13] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_MDF_DEVICE_13, 48}, + [MDF14] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_MDF_DEVICE_14, 48}, + [MDF15] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_MDF_DEVICE_15, 48}, + [MDF16] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_MDF_DEVICE_16, 48}, + [MDF17] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_MDF_DEVICE_17, 48}, + [MDF18] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_MDF_DEVICE_18, 48}, + [MDF19] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_MDF_DEVICE_19, 48}, + [MDF20] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_MDF_DEVICE_20, 48}, + [MDF21] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_MDF_DEVICE_21, 48}, + [MDF22] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_MDF_DEVICE_22, 48}, + [MDF23] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_MDF_DEVICE_23, 48}, + [MDF24] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_MDF_DEVICE_24, 48}, + [MDF25] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_MDF_DEVICE_25, 48}, + [MDF26] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_MDF_DEVICE_26, 48}, + [MDF27] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_MDF_DEVICE_27, 48}, + [MDF28] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_MDF_DEVICE_28, 48}, + [MDF29] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_MDF_DEVICE_29, 48}, + [MDF30] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_MDF_DEVICE_30, 48}, + [MDF31] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_MDF_DEVICE_31, 48}, + [MDF32] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_MDF_DEVICE_32, 48}, + [MDF33] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_MDF_DEVICE_33, 48}, + [MDF34] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_MDF_DEVICE_34, 48}, + [MDF35] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_MDF_DEVICE_35, 48}, + [MDF36] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_MDF_DEVICE_36, 48}, + [MDF37] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_MDF_DEVICE_37, 48}, + [MDF38] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_MDF_DEVICE_38, 48}, + [MDF39] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_MDF_DEVICE_39, 48}, + [MDF40] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_MDF_DEVICE_40, 48}, + [MDF41] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_MDF_DEVICE_41, 48}, + [MDF42] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_MDF_DEVICE_42, 48}, + [MDF43] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_MDF_DEVICE_43, 48}, + [MDF44] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_MDF_DEVICE_44, 48}, + [MDF45] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_MDF_DEVICE_45, 48}, + [MDF46] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_MDF_DEVICE_46, 48}, + [MDF47] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_MDF_DEVICE_47, 48}, + [MDF48] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_MDF_DEVICE_48, 48}, + [MDF49] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_MDF_DEVICE_49, 48}, + [QBOX0] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, PCI_QPI_DEVICE_PORT_0, 48}, + [QBOX1] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, PCI_QPI_DEVICE_PORT_1, 48}, + [QBOX2] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, PCI_QPI_DEVICE_PORT_2, 48}, + [QBOX3] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, PCI_QPI_DEVICE_PORT_3, 48}, + [CBOX0] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C0, 48}, + [CBOX1] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C1, 48}, + [CBOX2] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C2, 48}, + [CBOX3] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C3, 48}, + [CBOX4] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C4, 48}, + [CBOX5] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C5, 48}, + [CBOX6] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C6, 48}, + [CBOX7] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C7, 48}, + [CBOX8] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C8, 48}, + [CBOX9] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C9, 48}, + [CBOX10] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C10, 48}, + [CBOX11] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C11, 48}, + [CBOX12] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C12, 48}, + [CBOX13] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C13, 48}, + [CBOX14] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C14, 48}, + [CBOX15] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C15, 48}, + [CBOX16] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C16, 48}, + [CBOX17] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C17, 48}, + [CBOX18] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C18, 48}, + [CBOX19] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C19, 48}, + [CBOX20] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C20, 48}, + [CBOX21] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C21, 48}, + [CBOX22] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C22, 48}, + [CBOX23] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C23, 48}, + [CBOX24] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C24, 48}, + [CBOX25] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C25, 48}, + [CBOX26] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C26, 48}, + [CBOX27] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C27, 48}, + [CBOX28] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C28, 48}, + [CBOX29] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C29, 48}, + [CBOX30] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C30, 48}, + [CBOX31] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C31, 48}, + [CBOX32] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C32, 48}, + [CBOX33] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C33, 48}, + [CBOX34] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C34, 48}, + [CBOX35] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C35, 48}, + [CBOX36] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C36, 48}, + [CBOX37] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C37, 48}, + [CBOX38] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C38, 48}, + [CBOX39] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C39, 48}, + [CBOX40] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C40, 48}, + [CBOX41] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C41, 48}, + [CBOX42] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C42, 48}, + [CBOX43] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C43, 48}, + [CBOX44] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C44, 48}, + [CBOX45] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C45, 48}, + [CBOX46] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C46, 48}, + [CBOX47] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C47, 48}, + [CBOX48] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C48, 48}, + [CBOX49] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C49, 48}, + [CBOX50] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C50, 48}, + [CBOX51] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C51, 48}, + [CBOX52] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C52, 48}, + [CBOX53] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C53, 48}, + [CBOX54] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C54, 48}, + [CBOX55] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C55, 48}, + [CBOX56] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C56, 48}, + [CBOX57] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C57, 48}, + [CBOX58] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C58, 48}, + [CBOX59] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C59, 48}, + [CBOX60] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C60, 48}, + [CBOX61] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C61, 48}, + [CBOX62] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C62, 48}, + [CBOX63] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C63, 48}, + [CBOX64] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C64, 48}, + [CBOX65] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C65, 48}, + [CBOX66] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C66, 48}, + [CBOX67] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C67, 48}, + [CBOX68] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C68, 48}, + [CBOX69] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C69, 48}, + [CBOX70] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C70, 48}, + [CBOX71] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C71, 48}, + [CBOX72] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C72, 48}, + [CBOX73] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C73, 48}, + [CBOX74] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C74, 48}, + [CBOX75] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C75, 48}, + [CBOX76] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C76, 48}, + [CBOX77] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C77, 48}, + [CBOX78] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C78, 48}, + [CBOX79] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C79, 48}, + [CBOX80] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C80, 48}, + [CBOX81] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C81, 48}, + [CBOX82] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C82, 48}, + [CBOX83] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C83, 48}, + [CBOX84] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C84, 48}, + [CBOX85] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C85, 48}, + [CBOX86] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C86, 48}, + [CBOX87] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C87, 48}, + [CBOX88] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C88, 48}, + [CBOX89] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C89, 48}, + [CBOX90] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C90, 48}, + [CBOX91] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C91, 48}, + [CBOX92] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C92, 48}, + [CBOX93] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C93, 48}, + [CBOX94] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C94, 48}, + [CBOX95] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C95, 48}, + [CBOX96] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C96, 48}, + [CBOX97] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C97, 48}, + [CBOX98] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C98, 48}, + [CBOX99] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C99, 48}, + [CBOX100] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C100, 48}, + [CBOX101] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C101, 48}, + [CBOX102] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C102, 48}, + [CBOX103] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C103, 48}, + [CBOX104] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C104, 48}, + [CBOX105] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C105, 48}, + [CBOX106] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C106, 48}, + [CBOX107] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C107, 48}, + [CBOX108] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C108, 48}, + [CBOX109] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C109, 48}, + [CBOX110] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C110, 48}, + [CBOX111] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C111, 48}, + [CBOX112] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C112, 48}, + [CBOX113] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C113, 48}, + [CBOX114] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C114, 48}, + [CBOX115] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C115, 48}, + [CBOX116] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C116, 48}, + [CBOX117] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C117, 48}, + [CBOX118] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C118, 48}, + [CBOX119] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C119, 48}, + [CBOX120] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C120, 48}, + [CBOX121] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C121, 48}, + [CBOX122] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C122, 48}, + [CBOX123] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C123, 48}, + [CBOX124] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C124, 48}, + [CBOX125] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C125, 48}, + [CBOX126] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C126, 48}, + [CBOX127] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_CBOX_DEVICE_C127, 48}, + [BBOX0] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, PCI_HA_DEVICE_0, 48}, + [BBOX1] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, PCI_HA_DEVICE_1, 48}, + [BBOX2] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, PCI_HA_DEVICE_2, 48}, + [BBOX3] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, PCI_HA_DEVICE_3, 48}, + [BBOX4] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, PCI_HA_DEVICE_4, 48}, + [BBOX5] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, PCI_HA_DEVICE_5, 48}, + [BBOX6] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, PCI_HA_DEVICE_6, 48}, + [BBOX7] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, PCI_HA_DEVICE_7, 48}, + [BBOX8] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, PCI_HA_DEVICE_8, 48}, + [BBOX9] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, PCI_HA_DEVICE_9, 48}, + [BBOX10] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, PCI_HA_DEVICE_10, 48}, + [BBOX11] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, PCI_HA_DEVICE_11, 48}, + [BBOX12] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, PCI_HA_DEVICE_12, 48}, + [BBOX13] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, PCI_HA_DEVICE_13, 48}, + [BBOX14] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, PCI_HA_DEVICE_14, 48}, + [BBOX15] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, PCI_HA_DEVICE_15, 48}, + [BBOX16] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, PCI_HA_DEVICE_16, 48}, + [BBOX17] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, PCI_HA_DEVICE_17, 48}, + [BBOX18] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, PCI_HA_DEVICE_18, 48}, + [BBOX19] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, PCI_HA_DEVICE_19, 48}, + [BBOX20] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, PCI_HA_DEVICE_20, 48}, + [BBOX21] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, PCI_HA_DEVICE_21, 48}, + [BBOX22] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, PCI_HA_DEVICE_22, 48}, + [BBOX23] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, PCI_HA_DEVICE_23, 48}, + [BBOX24] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, PCI_HA_DEVICE_24, 48}, + [BBOX25] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, PCI_HA_DEVICE_25, 48}, + [BBOX26] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, PCI_HA_DEVICE_26, 48}, + [BBOX27] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, PCI_HA_DEVICE_27, 48}, + [BBOX28] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, PCI_HA_DEVICE_28, 48}, + [BBOX29] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, PCI_HA_DEVICE_29, 48}, + [BBOX30] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, PCI_HA_DEVICE_30, 48}, + [BBOX31] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, PCI_HA_DEVICE_31, 48}, + [RBOX0] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, PCI_R3QPI_DEVICE_LINK_0, 48}, + [RBOX1] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, PCI_R3QPI_DEVICE_LINK_1, 48}, + [RBOX2] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, PCI_R3QPI_DEVICE_LINK_2, 48}, + [RBOX3] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, PCI_R3QPI_DEVICE_LINK_3, 48}, + [PBOX0] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, PCI_R2PCIE_DEVICE0, 48}, + [PBOX1] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, PCI_R2PCIE_DEVICE1, 48}, + [PBOX2] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, PCI_R2PCIE_DEVICE2, 48}, + [PBOX3] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, PCI_R2PCIE_DEVICE3, 48}, + [PBOX4] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, PCI_R2PCIE_DEVICE4, 48}, + [PBOX5] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, PCI_R2PCIE_DEVICE5, 48}, + [PBOX6] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, PCI_R2PCIE_DEVICE6, 48}, + [PBOX7] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, PCI_R2PCIE_DEVICE7, 48}, + [PBOX8] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, PCI_R2PCIE_DEVICE8, 48}, + [PBOX9] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, PCI_R2PCIE_DEVICE9, 48}, + [PBOX10] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, PCI_R2PCIE_DEVICE10, 48}, + [PBOX11] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, PCI_R2PCIE_DEVICE11, 48}, + [PBOX12] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, PCI_R2PCIE_DEVICE12, 48}, + [PBOX13] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, PCI_R2PCIE_DEVICE13, 48}, + [PBOX14] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, PCI_R2PCIE_DEVICE14, 48}, + [PBOX15] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, PCI_R2PCIE_DEVICE15, 48}, + [PBOX16] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, PCI_R2PCIE_DEVICE16, 48}, + [PBOX17] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, PCI_R2PCIE_DEVICE17, 48}, + [PBOX18] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, PCI_R2PCIE_DEVICE18, 48}, + [PBOX19] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, PCI_R2PCIE_DEVICE19, 48}, + [PBOX20] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, PCI_R2PCIE_DEVICE20, 48}, + [PBOX21] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, PCI_R2PCIE_DEVICE21, 48}, + [PBOX22] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, PCI_R2PCIE_DEVICE22, 48}, + [PBOX23] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, PCI_R2PCIE_DEVICE23, 48}, + [PBOX24] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, PCI_R2PCIE_DEVICE24, 48}, + [PBOX25] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, PCI_R2PCIE_DEVICE25, 48}, + [PBOX26] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, PCI_R2PCIE_DEVICE26, 48}, + [PBOX27] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, PCI_R2PCIE_DEVICE27, 48}, + [PBOX28] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, PCI_R2PCIE_DEVICE28, 48}, + [PBOX29] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, PCI_R2PCIE_DEVICE29, 48}, + [PBOX30] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, PCI_R2PCIE_DEVICE30, 48}, + [PBOX31] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, PCI_R2PCIE_DEVICE31, 48}, + [IRP0] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_IRP_DEVICE_0, 48}, + [IRP1] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_IRP_DEVICE_1, 48}, + [IRP2] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_IRP_DEVICE_2, 48}, + [IRP3] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_IRP_DEVICE_3, 48}, + [IRP4] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_IRP_DEVICE_4, 48}, + [IRP5] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_IRP_DEVICE_5, 48}, + [IRP6] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_IRP_DEVICE_6, 48}, + [IRP7] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_IRP_DEVICE_7, 48}, + [IRP8] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_IRP_DEVICE_8, 48}, + [IRP9] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_IRP_DEVICE_9, 48}, + [IRP10] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_IRP_DEVICE_10, 48}, + [IRP11] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_IRP_DEVICE_11, 48}, + [IRP12] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_IRP_DEVICE_12, 48}, + [IRP13] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_IRP_DEVICE_13, 48}, + [IRP14] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_IRP_DEVICE_14, 48}, + [IRP15] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_IRP_DEVICE_15, 48}, + [IBOX0] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_IIO_DEVICE_0, 48}, + [IBOX1] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_IIO_DEVICE_1, 48}, + [IBOX2] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_IIO_DEVICE_2, 48}, + [IBOX3] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_IIO_DEVICE_3, 48}, + [IBOX4] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_IIO_DEVICE_4, 48}, + [IBOX5] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_IIO_DEVICE_5, 48}, + [IBOX6] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_IIO_DEVICE_6, 48}, + [IBOX7] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_IIO_DEVICE_7, 48}, + [IBOX8] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_IIO_DEVICE_8, 48}, + [IBOX9] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_IIO_DEVICE_9, 48}, + [IBOX10] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_IIO_DEVICE_10, 48}, + [IBOX11] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_IIO_DEVICE_11, 48}, + [IBOX12] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_IIO_DEVICE_12, 48}, + [IBOX13] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_IIO_DEVICE_13, 48}, + [IBOX14] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_IIO_DEVICE_14, 48}, + [IBOX15] = {FAKE_UNC_UNIT_CTRL, FAKE_UNC_UNIT_STATUS, FAKE_UNC_UNIT_STATUS, 0, 0, MSR_IIO_DEVICE_15, 48}, +}; + +static PciDevice graniterapids_pci_devices[MAX_NUM_PCI_DEVICES] = { + [MSR_DEV] = {NODEVTYPE, "", "MSR", ""}, + [MMIO_IMC_DEVICE_0_CH_0] = {IMC, NULL, "MMAP_IMC_DEVICE", "MBOX0", 0x3451}, + [MMIO_IMC_DEVICE_0_CH_1] = {IMC, NULL, "MMAP_IMC_DEVICE", "MBOX1", 0x3451}, + [MMIO_IMC_DEVICE_0_CH_2] = {IMC, NULL, "MMAP_IMC_DEVICE", "MBOX2", 0x3451}, + [MMIO_IMC_DEVICE_0_CH_3] = {IMC, NULL, "MMAP_IMC_DEVICE", "MBOX3", 0x3451}, + [MMIO_IMC_DEVICE_0_CH_4] = {IMC, NULL, "MMAP_IMC_DEVICE", "MBOX4", 0x3451}, + [MMIO_IMC_DEVICE_0_CH_5] = {IMC, NULL, "MMAP_IMC_DEVICE", "MBOX5", 0x3451}, + [MMIO_IMC_DEVICE_0_CH_6] = {IMC, NULL, "MMAP_IMC_DEVICE", "MBOX6", 0x3451}, + [MMIO_IMC_DEVICE_0_CH_7] = {IMC, NULL, "MMAP_IMC_DEVICE", "MBOX7", 0x3451}, + [MMIO_IMC_DEVICE_1_CH_0] = {IMC, NULL, "MMAP_IMC_DEVICE", "MBOX8", 0x3451}, + [MMIO_IMC_DEVICE_1_CH_1] = {IMC, NULL, "MMAP_IMC_DEVICE", "MBOX9", 0x3451}, + [MMIO_IMC_DEVICE_1_CH_2] = {IMC, NULL, "MMAP_IMC_DEVICE", "MBOX10", 0x3451}, + [MMIO_IMC_DEVICE_1_CH_3] = {IMC, NULL, "MMAP_IMC_DEVICE", "MBOX11", 0x3451}, + [MMIO_IMC_DEVICE_1_CH_4] = {IMC, NULL, "MMAP_IMC_DEVICE", "MBOX12", 0x3451}, + [MMIO_IMC_DEVICE_1_CH_5] = {IMC, NULL, "MMAP_IMC_DEVICE", "MBOX13", 0x3451}, + [MMIO_IMC_DEVICE_1_CH_6] = {IMC, NULL, "MMAP_IMC_DEVICE", "MBOX14", 0x3451}, + [MMIO_IMC_DEVICE_1_CH_7] = {IMC, NULL, "MMAP_IMC_DEVICE", "MBOX15", 0x3451}, +}; + +static char* graniterapids_translate_types[NUM_UNITS] = { + [FIXED] = "/sys/bus/event_source/devices/cpu", + [PMC] = "/sys/bus/event_source/devices/cpu", + // I don't get it to work, so no TMA metrics with perf_event at the moment + //[METRICS] = "/sys/bus/event_source/devices/cpu", + [POWER] = "/sys/bus/event_source/devices/power", + [MBOX0] = "/sys/bus/event_source/devices/uncore_imc_0", + [MBOX1] = "/sys/bus/event_source/devices/uncore_imc_1", + [MBOX2] = "/sys/bus/event_source/devices/uncore_imc_2", + [MBOX3] = "/sys/bus/event_source/devices/uncore_imc_3", + [MBOX4] = "/sys/bus/event_source/devices/uncore_imc_4", + [MBOX5] = "/sys/bus/event_source/devices/uncore_imc_5", + [MBOX6] = "/sys/bus/event_source/devices/uncore_imc_6", + [MBOX7] = "/sys/bus/event_source/devices/uncore_imc_7", + [MBOX8] = "/sys/bus/event_source/devices/uncore_imc_8", + [MBOX9] = "/sys/bus/event_source/devices/uncore_imc_9", + [MBOX10] = "/sys/bus/event_source/devices/uncore_imc_10", + [MBOX11] = "/sys/bus/event_source/devices/uncore_imc_11", + [MBOX12] = "/sys/bus/event_source/devices/uncore_imc_12", + [MBOX13] = "/sys/bus/event_source/devices/uncore_imc_13", + [MBOX14] = "/sys/bus/event_source/devices/uncore_imc_14", + [MBOX15] = "/sys/bus/event_source/devices/uncore_imc_15", + [PBOX0] = "/sys/bus/event_source/devices/uncore_b2cxl_0", + [PBOX1] = "/sys/bus/event_source/devices/uncore_b2cxl_1", + [PBOX2] = "/sys/bus/event_source/devices/uncore_b2cxl_2", + [PBOX3] = "/sys/bus/event_source/devices/uncore_b2cxl_3", + [PBOX4] = "/sys/bus/event_source/devices/uncore_b2cxl_4", + [PBOX5] = "/sys/bus/event_source/devices/uncore_b2cxl_5", + [PBOX6] = "/sys/bus/event_source/devices/uncore_b2cxl_6", + [PBOX7] = "/sys/bus/event_source/devices/uncore_b2cxl_7", + [PBOX8] = "/sys/bus/event_source/devices/uncore_b2cxl_8", + [PBOX9] = "/sys/bus/event_source/devices/uncore_b2cxl_9", + [PBOX10] = "/sys/bus/event_source/devices/uncore_b2cxl_10", + [PBOX11] = "/sys/bus/event_source/devices/uncore_b2cxl_11", + [PBOX12] = "/sys/bus/event_source/devices/uncore_b2cxl_12", + [PBOX13] = "/sys/bus/event_source/devices/uncore_b2cxl_13", + [PBOX14] = "/sys/bus/event_source/devices/uncore_b2cxl_14", + [PBOX15] = "/sys/bus/event_source/devices/uncore_b2cxl_15", + [PBOX16] = "/sys/bus/event_source/devices/uncore_b2cxl_16", + [PBOX17] = "/sys/bus/event_source/devices/uncore_b2cxl_17", + [PBOX18] = "/sys/bus/event_source/devices/uncore_b2cxl_18", + [PBOX19] = "/sys/bus/event_source/devices/uncore_b2cxl_19", + [PBOX20] = "/sys/bus/event_source/devices/uncore_b2cxl_20", + [PBOX21] = "/sys/bus/event_source/devices/uncore_b2cxl_21", + [PBOX22] = "/sys/bus/event_source/devices/uncore_b2cxl_22", + [PBOX23] = "/sys/bus/event_source/devices/uncore_b2cxl_23", + [PBOX24] = "/sys/bus/event_source/devices/uncore_b2cxl_24", + [PBOX25] = "/sys/bus/event_source/devices/uncore_b2cxl_25", + [PBOX26] = "/sys/bus/event_source/devices/uncore_b2cxl_26", + [PBOX27] = "/sys/bus/event_source/devices/uncore_b2cxl_27", + [PBOX28] = "/sys/bus/event_source/devices/uncore_b2cxl_28", + [PBOX29] = "/sys/bus/event_source/devices/uncore_b2cxl_29", + [PBOX30] = "/sys/bus/event_source/devices/uncore_b2cxl_30", + [PBOX31] = "/sys/bus/event_source/devices/uncore_b2cxl_31", + [UBOX] = "/sys/bus/event_source/devices/uncore_ubox", + [MDF0] = "/sys/bus/event_source/devices/uncore_mdf_0", + [MDF1] = "/sys/bus/event_source/devices/uncore_mdf_1", + [MDF2] = "/sys/bus/event_source/devices/uncore_mdf_2", + [MDF3] = "/sys/bus/event_source/devices/uncore_mdf_3", + [MDF4] = "/sys/bus/event_source/devices/uncore_mdf_4", + [MDF5] = "/sys/bus/event_source/devices/uncore_mdf_5", + [MDF6] = "/sys/bus/event_source/devices/uncore_mdf_6", + [MDF7] = "/sys/bus/event_source/devices/uncore_mdf_7", + [MDF8] = "/sys/bus/event_source/devices/uncore_mdf_8", + [MDF9] = "/sys/bus/event_source/devices/uncore_mdf_9", + [MDF10] = "/sys/bus/event_source/devices/uncore_mdf_10", + [MDF11] = "/sys/bus/event_source/devices/uncore_mdf_11", + [MDF12] = "/sys/bus/event_source/devices/uncore_mdf_12", + [MDF13] = "/sys/bus/event_source/devices/uncore_mdf_13", + [MDF14] = "/sys/bus/event_source/devices/uncore_mdf_14", + [MDF15] = "/sys/bus/event_source/devices/uncore_mdf_15", + [MDF16] = "/sys/bus/event_source/devices/uncore_mdf_16", + [MDF17] = "/sys/bus/event_source/devices/uncore_mdf_17", + [MDF18] = "/sys/bus/event_source/devices/uncore_mdf_18", + [MDF19] = "/sys/bus/event_source/devices/uncore_mdf_19", + [MDF20] = "/sys/bus/event_source/devices/uncore_mdf_20", + [MDF21] = "/sys/bus/event_source/devices/uncore_mdf_21", + [MDF22] = "/sys/bus/event_source/devices/uncore_mdf_22", + [MDF23] = "/sys/bus/event_source/devices/uncore_mdf_23", + [MDF24] = "/sys/bus/event_source/devices/uncore_mdf_24", + [MDF25] = "/sys/bus/event_source/devices/uncore_mdf_25", + [MDF26] = "/sys/bus/event_source/devices/uncore_mdf_26", + [MDF27] = "/sys/bus/event_source/devices/uncore_mdf_27", + [MDF28] = "/sys/bus/event_source/devices/uncore_mdf_28", + [MDF29] = "/sys/bus/event_source/devices/uncore_mdf_29", + [MDF30] = "/sys/bus/event_source/devices/uncore_mdf_30", + [MDF31] = "/sys/bus/event_source/devices/uncore_mdf_31", + [MDF32] = "/sys/bus/event_source/devices/uncore_mdf_32", + [MDF33] = "/sys/bus/event_source/devices/uncore_mdf_33", + [MDF34] = "/sys/bus/event_source/devices/uncore_mdf_34", + [MDF35] = "/sys/bus/event_source/devices/uncore_mdf_35", + [MDF36] = "/sys/bus/event_source/devices/uncore_mdf_36", + [MDF37] = "/sys/bus/event_source/devices/uncore_mdf_37", + [MDF38] = "/sys/bus/event_source/devices/uncore_mdf_38", + [MDF39] = "/sys/bus/event_source/devices/uncore_mdf_39", + [MDF40] = "/sys/bus/event_source/devices/uncore_mdf_40", + [MDF41] = "/sys/bus/event_source/devices/uncore_mdf_41", + [MDF42] = "/sys/bus/event_source/devices/uncore_mdf_42", + [MDF43] = "/sys/bus/event_source/devices/uncore_mdf_43", + [MDF44] = "/sys/bus/event_source/devices/uncore_mdf_44", + [MDF45] = "/sys/bus/event_source/devices/uncore_mdf_45", + [MDF46] = "/sys/bus/event_source/devices/uncore_mdf_46", + [MDF47] = "/sys/bus/event_source/devices/uncore_mdf_47", + [MDF48] = "/sys/bus/event_source/devices/uncore_mdf_48", + [MDF49] = "/sys/bus/event_source/devices/uncore_mdf_49", + [WBOX0] = "/sys/bus/event_source/devices/uncore_pcu_0", + [WBOX1] = "/sys/bus/event_source/devices/uncore_pcu_1", + [WBOX2] = "/sys/bus/event_source/devices/uncore_pcu_2", + [WBOX3] = "/sys/bus/event_source/devices/uncore_pcu_3", + [BBOX0] = "/sys/bus/event_source/devices/uncore_b2cmi_0", + [BBOX1] = "/sys/bus/event_source/devices/uncore_b2cmi_1", + [BBOX2] = "/sys/bus/event_source/devices/uncore_b2cmi_2", + [BBOX3] = "/sys/bus/event_source/devices/uncore_b2cmi_3", + [BBOX4] = "/sys/bus/event_source/devices/uncore_b2cmi_4", + [BBOX5] = "/sys/bus/event_source/devices/uncore_b2cmi_5", + [BBOX6] = "/sys/bus/event_source/devices/uncore_b2cmi_6", + [BBOX7] = "/sys/bus/event_source/devices/uncore_b2cmi_7", + [BBOX8] = "/sys/bus/event_source/devices/uncore_b2cmi_8", + [BBOX9] = "/sys/bus/event_source/devices/uncore_b2cmi_9", + [BBOX10] = "/sys/bus/event_source/devices/uncore_b2cmi_10", + [BBOX11] = "/sys/bus/event_source/devices/uncore_b2cmi_11", + [BBOX12] = "/sys/bus/event_source/devices/uncore_b2cmi_12", + [BBOX13] = "/sys/bus/event_source/devices/uncore_b2cmi_13", + [BBOX14] = "/sys/bus/event_source/devices/uncore_b2cmi_14", + [BBOX15] = "/sys/bus/event_source/devices/uncore_b2cmi_15", + [BBOX16] = "/sys/bus/event_source/devices/uncore_b2cmi_16", + [BBOX17] = "/sys/bus/event_source/devices/uncore_b2cmi_17", + [BBOX18] = "/sys/bus/event_source/devices/uncore_b2cmi_18", + [BBOX19] = "/sys/bus/event_source/devices/uncore_b2cmi_19", + [BBOX20] = "/sys/bus/event_source/devices/uncore_b2cmi_20", + [BBOX21] = "/sys/bus/event_source/devices/uncore_b2cmi_21", + [BBOX22] = "/sys/bus/event_source/devices/uncore_b2cmi_22", + [BBOX23] = "/sys/bus/event_source/devices/uncore_b2cmi_23", + [BBOX24] = "/sys/bus/event_source/devices/uncore_b2cmi_24", + [BBOX25] = "/sys/bus/event_source/devices/uncore_b2cmi_25", + [BBOX26] = "/sys/bus/event_source/devices/uncore_b2cmi_26", + [BBOX27] = "/sys/bus/event_source/devices/uncore_b2cmi_27", + [BBOX28] = "/sys/bus/event_source/devices/uncore_b2cmi_28", + [BBOX29] = "/sys/bus/event_source/devices/uncore_b2cmi_29", + [BBOX30] = "/sys/bus/event_source/devices/uncore_b2cmi_30", + [BBOX31] = "/sys/bus/event_source/devices/uncore_b2cmi_31", + [IRP0] = "/sys/bus/event_source/devices/uncore_irp_0", + [IRP1] = "/sys/bus/event_source/devices/uncore_irp_1", + [IRP2] = "/sys/bus/event_source/devices/uncore_irp_2", + [IRP3] = "/sys/bus/event_source/devices/uncore_irp_3", + [IRP4] = "/sys/bus/event_source/devices/uncore_irp_4", + [IRP5] = "/sys/bus/event_source/devices/uncore_irp_5", + [IRP6] = "/sys/bus/event_source/devices/uncore_irp_6", + [IRP7] = "/sys/bus/event_source/devices/uncore_irp_7", + [IRP8] = "/sys/bus/event_source/devices/uncore_irp_8", + [IRP9] = "/sys/bus/event_source/devices/uncore_irp_9", + [IRP10] = "/sys/bus/event_source/devices/uncore_irp_10", + [IRP11] = "/sys/bus/event_source/devices/uncore_irp_11", + [IRP12] = "/sys/bus/event_source/devices/uncore_irp_12", + [IRP13] = "/sys/bus/event_source/devices/uncore_irp_13", + [IRP14] = "/sys/bus/event_source/devices/uncore_irp_14", + [IBOX0] = "/sys/bus/event_source/devices/uncore_iio_0", + [IBOX1] = "/sys/bus/event_source/devices/uncore_iio_1", + [IBOX2] = "/sys/bus/event_source/devices/uncore_iio_2", + [IBOX3] = "/sys/bus/event_source/devices/uncore_iio_3", + [IBOX4] = "/sys/bus/event_source/devices/uncore_iio_4", + [IBOX5] = "/sys/bus/event_source/devices/uncore_iio_5", + [IBOX6] = "/sys/bus/event_source/devices/uncore_iio_6", + [IBOX7] = "/sys/bus/event_source/devices/uncore_iio_7", + [IBOX8] = "/sys/bus/event_source/devices/uncore_iio_8", + [IBOX9] = "/sys/bus/event_source/devices/uncore_iio_9", + [IBOX10] = "/sys/bus/event_source/devices/uncore_iio_10", + [IBOX11] = "/sys/bus/event_source/devices/uncore_iio_11", + [IBOX12] = "/sys/bus/event_source/devices/uncore_iio_12", + [IBOX13] = "/sys/bus/event_source/devices/uncore_iio_13", + [IBOX14] = "/sys/bus/event_source/devices/uncore_iio_14", +}; + +static char* registerTypeNamesGraniteRapids[MAX_UNITS] = { + [UBOX] = "General Uncore Controller", + [WBOX0] = "Power Control Unit 0", + [WBOX1] = "Power Control Unit 1", + [WBOX2] = "Power Control Unit 2", + [WBOX3] = "Power Control Unit 3", + [MBOX0] = "Memory Controller 0 Channel 0", + [MBOX1] = "Memory Controller 0 Channel 1", + [MBOX2] = "Memory Controller 1 Channel 0", + [MBOX3] = "Memory Controller 1 Channel 1", + [MBOX4] = "Memory Controller 2 Channel 0", + [MBOX5] = "Memory Controller 2 Channel 1", + [MBOX6] = "Memory Controller 3 Channel 0", + [MBOX7] = "Memory Controller 3 Channel 1", + [MBOX8] = "Memory Controller 3 Channel 1", + [MBOX9] = "Memory Controller 3 Channel 1", + [MBOX10] = "Memory Controller 3 Channel 1", + [MBOX11] = "Memory Controller 3 Channel 1", + [MBOX12] = "Memory Controller 3 Channel 1", + [MBOX13] = "Memory Controller 3 Channel 1", + [MBOX14] = "Memory Controller 3 Channel 1", + [MBOX15] = "Memory Controller 3 Channel 1", + [MBOX0FIX] = "Memory Controller 0 Channel 0 Fixed Counter", + [MBOX1FIX] = "Memory Controller 0 Channel 1 Fixed Counter", + [MBOX2FIX] = "Memory Controller 1 Channel 0 Fixed Counter", + [MBOX3FIX] = "Memory Controller 1 Channel 1 Fixed Counter", + [MBOX4FIX] = "Memory Controller 2 Channel 0 Fixed Counter", + [MBOX5FIX] = "Memory Controller 2 Channel 1 Fixed Counter", + [MBOX6FIX] = "Memory Controller 3 Channel 0 Fixed Counter", + [MBOX7FIX] = "Memory Controller 3 Channel 1 Fixed Counter", + [MBOX8FIX] = "Memory Controller 3 Channel 1 Fixed Counter", + [MBOX9FIX] = "Memory Controller 3 Channel 1 Fixed Counter", + [MBOX10FIX] = "Memory Controller 3 Channel 1 Fixed Counter", + [MBOX11FIX] = "Memory Controller 3 Channel 1 Fixed Counter", + [MBOX12FIX] = "Memory Controller 3 Channel 1 Fixed Counter", + [MBOX13FIX] = "Memory Controller 3 Channel 1 Fixed Counter", + [MBOX14FIX] = "Memory Controller 3 Channel 1 Fixed Counter", + [MBOX15FIX] = "Memory Controller 3 Channel 1 Fixed Counter", + [MDF0] = "Embedded Multi-die Interconnect Bridge Interface 0", + [MDF1] = "Embedded Multi-die Interconnect Bridge Interface 1", + [MDF2] = "Embedded Multi-die Interconnect Bridge Interface 2", + [MDF3] = "Embedded Multi-die Interconnect Bridge Interface 3", + [MDF4] = "Embedded Multi-die Interconnect Bridge Interface 4", + [MDF5] = "Embedded Multi-die Interconnect Bridge Interface 5", + [MDF6] = "Embedded Multi-die Interconnect Bridge Interface 6", + [MDF7] = "Embedded Multi-die Interconnect Bridge Interface 7", + [MDF8] = "Embedded Multi-die Interconnect Bridge Interface 8", + [MDF9] = "Embedded Multi-die Interconnect Bridge Interface 9", + [MDF10] = "Embedded Multi-die Interconnect Bridge Interface 10", + [MDF11] = "Embedded Multi-die Interconnect Bridge Interface 11", + [MDF12] = "Embedded Multi-die Interconnect Bridge Interface 12", + [MDF13] = "Embedded Multi-die Interconnect Bridge Interface 13", + [MDF14] = "Embedded Multi-die Interconnect Bridge Interface 14", + [MDF15] = "Embedded Multi-die Interconnect Bridge Interface 15", + [MDF16] = "Embedded Multi-die Interconnect Bridge Interface 16", + [MDF17] = "Embedded Multi-die Interconnect Bridge Interface 17", + [MDF18] = "Embedded Multi-die Interconnect Bridge Interface 18", + [MDF19] = "Embedded Multi-die Interconnect Bridge Interface 19", + [MDF20] = "Embedded Multi-die Interconnect Bridge Interface 20", + [MDF21] = "Embedded Multi-die Interconnect Bridge Interface 21", + [MDF22] = "Embedded Multi-die Interconnect Bridge Interface 22", + [MDF23] = "Embedded Multi-die Interconnect Bridge Interface 23", + [MDF24] = "Embedded Multi-die Interconnect Bridge Interface 24", + [MDF25] = "Embedded Multi-die Interconnect Bridge Interface 25", + [MDF26] = "Embedded Multi-die Interconnect Bridge Interface 26", + [MDF27] = "Embedded Multi-die Interconnect Bridge Interface 27", + [MDF28] = "Embedded Multi-die Interconnect Bridge Interface 28", + [MDF29] = "Embedded Multi-die Interconnect Bridge Interface 29", + [MDF30] = "Embedded Multi-die Interconnect Bridge Interface 30", + [MDF31] = "Embedded Multi-die Interconnect Bridge Interface 31", + [MDF32] = "Embedded Multi-die Interconnect Bridge Interface 32", + [MDF33] = "Embedded Multi-die Interconnect Bridge Interface 33", + [MDF34] = "Embedded Multi-die Interconnect Bridge Interface 34", + [MDF35] = "Embedded Multi-die Interconnect Bridge Interface 35", + [MDF36] = "Embedded Multi-die Interconnect Bridge Interface 36", + [MDF37] = "Embedded Multi-die Interconnect Bridge Interface 37", + [MDF38] = "Embedded Multi-die Interconnect Bridge Interface 38", + [MDF39] = "Embedded Multi-die Interconnect Bridge Interface 39", + [MDF40] = "Embedded Multi-die Interconnect Bridge Interface 40", + [MDF41] = "Embedded Multi-die Interconnect Bridge Interface 41", + [MDF42] = "Embedded Multi-die Interconnect Bridge Interface 42", + [MDF43] = "Embedded Multi-die Interconnect Bridge Interface 43", + [MDF44] = "Embedded Multi-die Interconnect Bridge Interface 44", + [MDF45] = "Embedded Multi-die Interconnect Bridge Interface 45", + [MDF46] = "Embedded Multi-die Interconnect Bridge Interface 46", + [MDF47] = "Embedded Multi-die Interconnect Bridge Interface 47", + [MDF48] = "Embedded Multi-die Interconnect Bridge Interface 48", + [MDF49] = "Embedded Multi-die Interconnect Bridge Interface 49", + [BBOX0] = "B2CMI: gateway between the mesh and the memory channel controllers 0", + [BBOX1] = "B2CMI: gateway between the mesh and the memory channel controllers 1", + [BBOX2] = "B2CMI: gateway between the mesh and the memory channel controllers 2", + [BBOX3] = "B2CMI: gateway between the mesh and the memory channel controllers 3", + [BBOX4] = "B2CMI: gateway between the mesh and the memory channel controllers 4", + [BBOX5] = "B2CMI: gateway between the mesh and the memory channel controllers 5", + [BBOX6] = "B2CMI: gateway between the mesh and the memory channel controllers 6", + [BBOX7] = "B2CMI: gateway between the mesh and the memory channel controllers 7", + [BBOX8] = "B2CMI: gateway between the mesh and the memory channel controllers 8", + [BBOX9] = "B2CMI: gateway between the mesh and the memory channel controllers 9", + [BBOX10] = "B2CMI: gateway between the mesh and the memory channel controllers 10", + [BBOX11] = "B2CMI: gateway between the mesh and the memory channel controllers 11", + [BBOX12] = "B2CMI: gateway between the mesh and the memory channel controllers 12", + [BBOX13] = "B2CMI: gateway between the mesh and the memory channel controllers 13", + [BBOX14] = "B2CMI: gateway between the mesh and the memory channel controllers 14", + [BBOX15] = "B2CMI: gateway between the mesh and the memory channel controllers 15", + [BBOX16] = "B2CMI: gateway between the mesh and the memory channel controllers 16", + [BBOX17] = "B2CMI: gateway between the mesh and the memory channel controllers 17", + [BBOX18] = "B2CMI: gateway between the mesh and the memory channel controllers 18", + [BBOX19] = "B2CMI: gateway between the mesh and the memory channel controllers 19", + [BBOX20] = "B2CMI: gateway between the mesh and the memory channel controllers 20", + [BBOX21] = "B2CMI: gateway between the mesh and the memory channel controllers 21", + [BBOX22] = "B2CMI: gateway between the mesh and the memory channel controllers 22", + [BBOX23] = "B2CMI: gateway between the mesh and the memory channel controllers 23", + [BBOX24] = "B2CMI: gateway between the mesh and the memory channel controllers 24", + [BBOX25] = "B2CMI: gateway between the mesh and the memory channel controllers 25", + [BBOX26] = "B2CMI: gateway between the mesh and the memory channel controllers 26", + [BBOX27] = "B2CMI: gateway between the mesh and the memory channel controllers 27", + [BBOX28] = "B2CMI: gateway between the mesh and the memory channel controllers 28", + [BBOX29] = "B2CMI: gateway between the mesh and the memory channel controllers 29", + [BBOX30] = "B2CMI: gateway between the mesh and the memory channel controllers 30", + [BBOX31] = "B2CMI: gateway between the mesh and the memory channel controllers 31", + [RBOX0] = "B2UPI: mesh to Intel UPI interface 0", + [RBOX1] = "B2UPI: mesh to Intel UPI interface 1", + [RBOX2] = "B2UPI: mesh to Intel UPI interface 2", + [RBOX3] = "B2UPI: mesh to Intel UPI interface 3", + [PBOX0] = "B2CXL: interface between mesh and each IIO/CXL stack 0", + [PBOX1] = "B2CXL: interface between mesh and each IIO/CXL stack 1", + [PBOX2] = "B2CXL: interface between mesh and each IIO/CXL stack 2", + [PBOX3] = "B2CXL: interface between mesh and each IIO/CXL stack 3", + [PBOX4] = "B2CXL: interface between mesh and each IIO/CXL stack 4", + [PBOX5] = "B2CXL: interface between mesh and each IIO/CXL stack 5", + [PBOX6] = "B2CXL: interface between mesh and each IIO/CXL stack 6", + [PBOX7] = "B2CXL: interface between mesh and each IIO/CXL stack 7", + [PBOX8] = "B2CXL: interface between mesh and each IIO/CXL stack 8", + [PBOX9] = "B2CXL: interface between mesh and each IIO/CXL stack 9", + [PBOX10] = "B2CXL: interface between mesh and each IIO/CXL stack 10", + [PBOX11] = "B2CXL: interface between mesh and each IIO/CXL stack 11", + [PBOX12] = "B2CXL: interface between mesh and each IIO/CXL stack 12", + [PBOX13] = "B2CXL: interface between mesh and each IIO/CXL stack 13", + [PBOX14] = "B2CXL: interface between mesh and each IIO/CXL stack 14", + [PBOX15] = "B2CXL: interface between mesh and each IIO/CXL stack 15", + [PBOX16] = "B2CXL: interface between mesh and each IIO/CXL stack 16", + [PBOX17] = "B2CXL: interface between mesh and each IIO/CXL stack 17", + [PBOX18] = "B2CXL: interface between mesh and each IIO/CXL stack 18", + [PBOX19] = "B2CXL: interface between mesh and each IIO/CXL stack 19", + [PBOX20] = "B2CXL: interface between mesh and each IIO/CXL stack 20", + [PBOX21] = "B2CXL: interface between mesh and each IIO/CXL stack 21", + [PBOX22] = "B2CXL: interface between mesh and each IIO/CXL stack 22", + [PBOX23] = "B2CXL: interface between mesh and each IIO/CXL stack 23", + [PBOX24] = "B2CXL: interface between mesh and each IIO/CXL stack 24", + [PBOX25] = "B2CXL: interface between mesh and each IIO/CXL stack 25", + [PBOX26] = "B2CXL: interface between mesh and each IIO/CXL stack 26", + [PBOX27] = "B2CXL: interface between mesh and each IIO/CXL stack 27", + [PBOX28] = "B2CXL: interface between mesh and each IIO/CXL stack 28", + [PBOX29] = "B2CXL: interface between mesh and each IIO/CXL stack 29", + [PBOX30] = "B2CXL: interface between mesh and each IIO/CXL stack 30", + [PBOX31] = "B2CXL: interface between mesh and each IIO/CXL stack 31", + [IRP0] = "IIO Ring Port 0", + [IRP1] = "IIO Ring Port 1", + [IRP2] = "IIO Ring Port 2", + [IRP3] = "IIO Ring Port 3", + [IRP4] = "IIO Ring Port 4", + [IRP5] = "IIO Ring Port 5", + [IRP6] = "IIO Ring Port 6", + [IRP7] = "IIO Ring Port 7", + [IRP8] = "IIO Ring Port 8", + [IRP9] = "IIO Ring Port 9", + [IRP10] = "IIO Ring Port 10", + [IRP11] = "IIO Ring Port 11", + [IRP12] = "IIO Ring Port 12", + [IRP13] = "IIO Ring Port 13", + [IRP14] = "IIO Ring Port 14", + [IRP15] = "IIO Ring Port 15", + [IBOX0] = "IIO stack 0", + [IBOX1] = "IIO stack 1", + [IBOX2] = "IIO stack 2", + [IBOX3] = "IIO stack 3", + [IBOX4] = "IIO stack 4", + [IBOX5] = "IIO stack 5", + [IBOX6] = "IIO stack 6", + [IBOX7] = "IIO stack 7", + [IBOX8] = "IIO stack 8", + [IBOX9] = "IIO stack 9", + [IBOX10] = "IIO stack 10", + [IBOX11] = "IIO stack 11", + [IBOX12] = "IIO stack 12", + [IBOX13] = "IIO stack 13", + [IBOX14] = "IIO stack 14", + [IBOX15] = "IIO stack 15", +}; + +#define GNR_DEVICE_ID_CHA 0 +#define GNR_DEVICE_ID_IIO 1 +#define GNR_DEVICE_ID_IRP 2 +#define GNR_DEVICE_ID_iMC 6 +#define GNR_DEVICE_ID_UPI 8 +#define GNR_DEVICE_ID_PCU 4 +#define GNR_DEVICE_ID_UBOX 5 +#define GNR_DEVICE_ID_B2UPI 18 +#define GNR_DEVICE_ID_B2CMI 16 +#define GNR_DEVICE_ID_B2CXL 17 +#define GNR_DEVICE_ID_MDF 20 + +static PerfmonUncoreDiscovery graniterapids_uncore_discovery_map[] = { + {"CBOX", GNR_DEVICE_ID_CHA, 127, MSR_CBOX_DEVICE_C0}, + {"MBOX", GNR_DEVICE_ID_iMC, 15, MMIO_IMC_DEVICE_0_CH_0}, + {"UBOX", GNR_DEVICE_ID_UBOX, 1, MSR_UBOX_DEVICE}, + {"WBOX", GNR_DEVICE_ID_PCU, 3, MSR_PCU_DEVICE_0}, + {"IRP", GNR_DEVICE_ID_IRP, 15, MSR_IRP_DEVICE_0}, + {"IIO", GNR_DEVICE_ID_IIO, 15, MSR_IIO_DEVICE_0}, + {"QBOX", GNR_DEVICE_ID_UPI, 3, PCI_QPI_DEVICE_PORT_0}, + {"MDF", GNR_DEVICE_ID_MDF, 49, MSR_MDF_DEVICE_0}, + {"M2M", GNR_DEVICE_ID_B2CMI, 31, PCI_HA_DEVICE_0}, + {"RBOX", GNR_DEVICE_ID_B2UPI, 3, PCI_R3QPI_DEVICE_LINK_0}, + {"PBOX", GNR_DEVICE_ID_B2CXL, 31, PCI_R2PCIE_DEVICE0}, + {"INVALID", -1, 0, MSR_DEV} +}; diff --git a/src/includes/perfmon_graniterapids_events.txt b/src/includes/perfmon_graniterapids_events.txt new file mode 100644 index 000000000..fbf02cc31 --- /dev/null +++ b/src/includes/perfmon_graniterapids_events.txt @@ -0,0 +1,1400 @@ +# ======================================================================================= +# +# Filename: perfmon_graniterapids_events.txt +# +# Description: Event list for Intel Granite Rapids +# +# Version: +# Released: +# +# Author: Thomas Gruber (tr), thomas.roehl@googlemail.com +# Project: likwid +# +# Copyright (C) 2015 RRZE, University Erlangen-Nuremberg +# +# This program is free software: you can redistribute it and/or modify it under +# the terms of the GNU General Public License as published by the Free Software +# Foundation, either version 3 of the License, or (at your option) any later +# version. +# +# This program is distributed in the hope that it will be useful, but WITHOUT ANY +# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A +# PARTICULAR PURPOSE. See the GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License along with +# this program. If not, see . +# +# ======================================================================================= + +EVENT_TEMP_CORE 0x00 TMP0 +UMASK_TEMP_CORE 0x00 + +EVENT_PWR_PKG_ENERGY 0x02 PWR0 +UMASK_PWR_PKG_ENERGY 0x00 + +EVENT_PWR_PP0_ENERGY 0x01 PWR1 +UMASK_PWR_PP0_ENERGY 0x00 + +EVENT_PWR_PP1_ENERGY 0x04 PWR2 +UMASK_PWR_PP1_ENERGY 0x00 + +EVENT_PWR_DRAM_ENERGY 0x03 PWR3 +UMASK_PWR_DRAM_ENERGY 0x00 + +EVENT_PWR_PLATFORM_ENERGY 0x05 PWR4 +UMASK_PWR_PLATFORM_ENERGY 0x00 + +EVENT_VOLTAGE_CORE 0x00 VTG0 +UMASK_VOLTAGE_CORE 0x00 + +EVENT_INSTR_RETIRED 0x00 FIXC0 +UMASK_INSTR_RETIRED_ANY 0x01 + +EVENT_CPU_CLK_UNHALTED_CORE 0x00 FIXC1 +UMASK_CPU_CLK_UNHALTED_CORE 0x02 + +EVENT_CPU_CLK_UNHALTED_REF 0x00 FIXC2 +UMASK_CPU_CLK_UNHALTED_REF 0x03 + +EVENT_TOPDOWN_SLOTS 0x00 FIXC3 +UMASK_TOPDOWN_SLOTS 0x04 + +EVENT_RETIRING 0x00 TMA0 +UMASK_RETIRING 0x00 + +EVENT_BAD_SPECULATION 0x00 TMA1 +UMASK_BAD_SPECULATION 0x00 + +EVENT_FRONTEND_BOUND 0x00 TMA2 +UMASK_FRONTEND_BOUND 0x00 + +EVENT_BACKEND_BOUND 0x00 TMA3 +UMASK_BACKEND_BOUND 0x00 + +EVENT_CPU_CLOCK_UNHALTED 0x3C PMC +UMASK_CPU_CLOCK_UNHALTED_THREAD_P 0x00 +UMASK_CPU_CLOCK_UNHALTED_REF_XCLK 0x01 +UMASK_CPU_CLOCK_UNHALTED_ONE_THREAD_ACTIVE 0x02 +UMASK_CPU_CLOCK_UNHALTED_REF_DISTRIBUTED 0x08 +# Added by Thomas Gruber: Idea is to count also in halted state +DEFAULT_OPTIONS_CPU_CLOCK_UNHALTED_TOTAL_CYCLES EVENT_OPTION_THRESHOLD=0xA,EVENT_OPTION_INVERT=1 +UMASK_CPU_CLOCK_UNHALTED_TOTAL_CYCLES 0x00 + +# https://github.com/intel/perfmon/blob/main/GNR/events/graniterapids_core.json +# v1.02 + +EVENT_LD_BLOCKS 0x03 PMC +UMASK_LD_BLOCKS_ADDRESS_ALIAS 0x04 +UMASK_LD_BLOCKS_STORE_FORWARD 0x82 +UMASK_LD_BLOCKS_NO_SR 0x88 + +EVENT_ITLB_MISSES 0x11 PMC +UMASK_ITLB_MISSES_WALK_COMPLETED_4K 0x02 +UMASK_ITLB_MISSES_WALK_COMPLETED_2M_4M 0x04 +UMASK_ITLB_MISSES_WALK_COMPLETED 0x0E +DEFAULT_OPTIONS_ITLB_MISSES_WALK_ACTIVE EVENT_OPTION_THRESHOLD=0x1 +UMASK_ITLB_MISSES_WALK_ACTIVE 0x10 +UMASK_ITLB_MISSES_WALK_PENDING 0x10 +UMASK_ITLB_MISSES_STLB_HIT 0x20 + +EVENT_DTLB_LOAD_MISSES 0x12 PMC +UMASK_DTLB_LOAD_MISSES_WALK_COMPLETED_4K 0x02 +UMASK_DTLB_LOAD_MISSES_WALK_COMPLETED_2M_4M 0x04 +UMASK_DTLB_LOAD_MISSES_WALK_COMPLETED_1G 0x08 +UMASK_DTLB_LOAD_MISSES_WALK_COMPLETED 0x0E +DEFAULT_OPTIONS_DTLB_LOAD_MISSES_WALK_ACTIVE EVENT_OPTION_THRESHOLD=0x1 +UMASK_DTLB_LOAD_MISSES_WALK_ACTIVE 0x10 +UMASK_DTLB_LOAD_MISSES_WALK_PENDING 0x10 +UMASK_DTLB_LOAD_MISSES_STLB_HIT 0x20 + +EVENT_DTLB_STORE_MISSES 0x13 PMC +UMASK_DTLB_STORE_MISSES_WALK_COMPLETED_4K 0x02 +UMASK_DTLB_STORE_MISSES_WALK_COMPLETED_2M_4M 0x04 +UMASK_DTLB_STORE_MISSES_WALK_COMPLETED_1G 0x08 +UMASK_DTLB_STORE_MISSES_WALK_COMPLETED 0x0E +DEFAULT_OPTIONS_DTLB_STORE_MISSES_WALK_ACTIVE EVENT_OPTION_THRESHOLD=0x1 +UMASK_DTLB_STORE_MISSES_WALK_ACTIVE 0x10 +UMASK_DTLB_STORE_MISSES_WALK_PENDING 0x10 +UMASK_DTLB_STORE_MISSES_STLB_HIT 0x20 + +EVENT_OFFCORE_REQUESTS_OUTSTANDING 0x20 PMC +DEFAULT_OPTIONS_OFFCORE_REQUESTS_OUTSTANDING_CYCLES_WITH_DEMAND_DATA_RD EVENT_OPTION_THRESHOLD=0x1 +UMASK_OFFCORE_REQUESTS_OUTSTANDING_CYCLES_WITH_DEMAND_DATA_RD 0x01 +UMASK_OFFCORE_REQUESTS_OUTSTANDING_DEMAND_DATA_RD 0x01 +DEFAULT_OPTIONS_OFFCORE_REQUESTS_OUTSTANDING_CYCLES_WITH_DEMAND_CODE_RD EVENT_OPTION_THRESHOLD=0x1 +UMASK_OFFCORE_REQUESTS_OUTSTANDING_CYCLES_WITH_DEMAND_CODE_RD 0x02 +UMASK_OFFCORE_REQUESTS_OUTSTANDING_DEMAND_CODE_RD 0x02 +DEFAULT_OPTIONS_OFFCORE_REQUESTS_OUTSTANDING_CYCLES_WITH_DEMAND_RFO EVENT_OPTION_THRESHOLD=0x1 +UMASK_OFFCORE_REQUESTS_OUTSTANDING_CYCLES_WITH_DEMAND_RFO 0x04 +UMASK_OFFCORE_REQUESTS_OUTSTANDING_DEMAND_RFO 0x04 +DEFAULT_OPTIONS_OFFCORE_REQUESTS_OUTSTANDING_CYCLES_WITH_DATA_RD EVENT_OPTION_THRESHOLD=0x1 +UMASK_OFFCORE_REQUESTS_OUTSTANDING_CYCLES_WITH_DATA_RD 0x08 +UMASK_OFFCORE_REQUESTS_OUTSTANDING_DATA_RD 0x08 +DEFAULT_OPTIONS_OFFCORE_REQUESTS_OUTSTANDING_CYCLES_WITH_L3_MISS_DEMAND_DATA_RD EVENT_OPTION_THRESHOLD=0x1 +UMASK_OFFCORE_REQUESTS_OUTSTANDING_CYCLES_WITH_L3_MISS_DEMAND_DATA_RD 0x10 +UMASK_OFFCORE_REQUESTS_OUTSTANDING_L3_MISS_DEMAND_DATA_RD 0x10 + +EVENT_OFFCORE_REQUESTS 0x21 PMC +UMASK_OFFCORE_REQUESTS_DEMAND_DATA_RD 0x01 +UMASK_OFFCORE_REQUESTS_DEMAND_CODE_RD 0x02 +UMASK_OFFCORE_REQUESTS_DEMAND_RFO 0x04 +UMASK_OFFCORE_REQUESTS_DATA_RD 0x08 +UMASK_OFFCORE_REQUESTS_L3_MISS_DEMAND_DATA_RD 0x10 +UMASK_OFFCORE_REQUESTS_ALL_REQUESTS 0x80 + + +EVENT_L2_TRANS 0x23 PMC +UMASK_L2_TRANS_L2_WB 0x40 + +EVENT_L2_REQUEST 0x24 PMC +UMASK_L2_REQUEST_MISS 0x3F +UMASK_L2_REQUEST_HIT 0xDF + +EVENT_L2_RQSTS 0x24 PMC +UMASK_L2_RQSTS_DEMAND_DATA_RD_MISS 0x21 +UMASK_L2_RQSTS_RFO_MISS 0x22 +UMASK_L2_RQSTS_CODE_RD_MISS 0x24 +UMASK_L2_RQSTS_ALL_DEMAND_MISS 0x27 +UMASK_L2_RQSTS_SWPF_MISS 0x28 +UMASK_L2_RQSTS_HWPF_MISS 0x30 +UMASK_L2_RQSTS_MISS 0x3F +UMASK_L2_RQSTS_DEMAND_DATA_RD_HIT 0xC1 +UMASK_L2_RQSTS_RFO_HIT 0xC2 +UMASK_L2_RQSTS_CODE_RD_HIT 0xC4 +UMASK_L2_RQSTS_SWPF_HIT 0xC8 +UMASK_L2_RQSTS_HIT 0xDF +UMASK_L2_RQSTS_ALL_DEMAND_DATA_RD 0xE1 +UMASK_L2_RQSTS_ALL_RFO 0xE2 +UMASK_L2_RQSTS_ALL_ALL_CODE_RD 0xE4 +UMASK_L2_RQSTS_ALL_DEMAND_REFERENCES 0xE7 +UMASK_L2_RQSTS_ALL_HWPF 0xF0 +UMASK_L2_RQSTS_REFERENCES 0xFF +UMASK_L2_RQSTS_ALL 0xFF + +EVENT_L2_LINES_IN 0x25 PMC +UMASK_L2_LINES_IN_ALL 0x1F + +EVENT_L2_LINES_OUT 0x26 PMC +UMASK_L2_LINES_OUT_SILENT 0x01 +UMASK_L2_LINES_OUT_NON_SILENT 0x02 +UMASK_L2_LINES_OUT_USELESS_HWPF 0x04 + +EVENT_SQ_MISC 0x2C PMC +UMASK_SQ_MISC_BUS_LOCK 0x10 + +EVENT_XQ 0x2D PMC +UMASK_XQ_FULL_CYCLES 0x01 + +EVENT_LONGEST_LAT_CACHE 0x2E PMC +UMASK_LONGEST_LAT_CACHE_MISS 0x41 +UMASK_LONGEST_LAT_CACHE_REFERENCE 0x4F + +EVENT_SW_PREFETCH_ACCESS 0x40 PMC +UMASK_SW_PREFETCH_ACCESS_NTA 0x01 +UMASK_SW_PREFETCH_ACCESS_T0 0x02 +UMASK_SW_PREFETCH_ACCESS_T1_T2 0x04 +UMASK_SW_PREFETCH_ACCESS_PREFETCHW 0x08 +UMASK_SW_PREFETCH_ACCESS_ANY 0x0F + +EVENT_MEM_LOAD_COMPLETED_L1_MISS_ANY 0x43 PMC +UMASK_MEM_LOAD_COMPLETED_L1_MISS_ANY 0xFD + +EVENT_MEM_STORE_RETIRED_L2_HIT 0x44 PMC +UMASK_MEM_STORE_RETIRED_L2_HIT 0x01 + +EVENT_MEMORY_ACTIVITY 0x47 PMC +DEFAULT_OPTIONS_MEMORY_ACTIVITY_CYCLES_L1D_MISS EVENT_OPTION_THRESHOLD=0x02 +UMASK_MEMORY_ACTIVITY_CYCLES_L1D_MISS 0x02 +DEFAULT_OPTIONS_MEMORY_ACTIVITY_STALLS_L1D_MISS EVENT_OPTION_THRESHOLD=0x03 +UMASK_MEMORY_ACTIVITY_STALLS_L1D_MISS 0x03 +DEFAULT_OPTIONS_MEMORY_ACTIVITY_STALLS_L2_MISS EVENT_OPTION_THRESHOLD=0x05 +UMASK_MEMORY_ACTIVITY_STALLS_L2_MISS 0x05 +DEFAULT_OPTIONS_MEMORY_ACTIVITY_STALLS_L3_MISS EVENT_OPTION_THRESHOLD=0x09 +UMASK_MEMORY_ACTIVITY_STALLS_L3_MISS 0x09 + +EVENT_L1D_PEND_MISS 0x48 PMC +UMASK_L1D_PEND_MISS_PENDING 0x01 +DEFAULT_OPTIONS_L1D_PEND_MISS_PENDING_CYCLES EVENT_OPTION_THRESHOLD=0x01 +UMASK_L1D_PEND_MISS_PENDING_CYCLES 0x01 +UMASK_L1D_PEND_MISS_FB_FULL 0x02 +DEFAULT_OPTIONS_L1D_PEND_MISS_FB_FULL_PERIODS EVENT_OPTION_THRESHOLD=0x01 +UMASK_L1D_PEND_MISS_FB_FULL_PERIODS 0x02 +UMASK_L1D_PEND_MISS_L2_STALLS 0x04 + +EVENT_LOAD_HIT_PREFETCH 0x4C PMC +UMASK_LOAD_HIT_PREFETCH_SWPF 0x01 + +EVENT_L1D 0x51 PMC +UMASK_L1D_REPLACEMENT 0x01 +UMASK_L1D_HWPF_MISS 0x20 + +EVENT_BACLEARS_ANY 0x60 PMC +UMASK_BACLEARS_ANY 0x01 + +EVENT_DSB2MITE_SWITCHES_PENALTY_CYCLES 0x61 PMC +UMASK_DSB2MITE_SWITCHES_PENALTY_CYCLES 0x02 + +EVENT_INST_DECODED_DECODERS 0x75 PMC +UMASK_INST_DECODED_DECODERS 0x01 + +EVENT_UOPS_DECODED_DEC0_UOPS 0x76 PMC +UMASK_UOPS_DECODED_DEC0_UOPS 0x01 + +EVENT_IDQ 0x79 PMC +DEFAULT_OPTIONS_IDQ_MITE_CYCLES_ANY EVENT_OPTION_THRESHOLD=0x01 +UMASK_IDQ_MITE_CYCLES_ANY 0x04 +DEFAULT_OPTIONS_IDQ_MITE_CYCLES_OK EVENT_OPTION_THRESHOLD=0x06 +UMASK_IDQ_MITE_CYCLES_OK 0x04 +UMASK_IDQ_MITE_UOPS 0x04 +DEFAULT_OPTIONS_IDQ_DSB_CYCLES_ANY EVENT_OPTION_THRESHOLD=0x01 +UMASK_IDQ_DSB_CYCLES_ANY 0x08 +DEFAULT_OPTIONS_IDQ_DSB_CYCLES_OK EVENT_OPTION_THRESHOLD=0x06 +UMASK_IDQ_DSB_CYCLES_OK 0x08 +UMASK_IDQ_DSB_UOPS 0x08 +DEFAULT_OPTIONS_IDQ_MS_CYCLES_ANY EVENT_OPTION_THRESHOLD=0x01 +UMASK_IDQ_MS_CYCLES_ANY 0x08 +DEFAULT_OPTIONS_IDQ_MS_SWITCHES EVENT_OPTION_THRESHOLD=0x01,EVENT_OPTION_EDGE=0x1 +UMASK_IDQ_MS_SWITCHES 0x08 +UMASK_IDQ_MS_UOPS 0x08 + +EVENT_ICACHE_DATA 0x80 PMC +UMASK_ICACHE_DATA_STALLS 0x04 +DEFAULT_OPTIONS_ICACHE_DATA_STALL_PERIODS EVENT_OPTION_THRESHOLD=0x01,EVENT_OPTION_EDGE=0x1 +UMASK_ICACHE_DATA_STALL_PERIODS 0x04 + +EVENT_ICACHE_TAG 0x83 PMC +UMASK_ICACHE_TAG_STALLS 0x04 + +EVENT_DECODE 0x87 PMC +UMASK_DECODE_LCP 0x01 +UMASK_DECODE_MS_BUSY 0x02 + +EVENT_IDQ_UOPS_NOT_DELIVERED 0x9C PMC +UMASK_IDQ_UOPS_NOT_DELIVERED_CORE 0x01 +DEFAULT_OPTIONS_IDQ_UOPS_NOT_DELIVERED_CYCLES_0_UOPS_DELIV_CORE EVENT_OPTION_THRESHOLD=0x06 +UMASK_IDQ_UOPS_NOT_DELIVERED_CYCLES_0_UOPS_DELIV_CORE 0x01 +DEFAULT_OPTIONS_IDQ_UOPS_NOT_DELIVERED_CYCLES_FE_WAS_OK EVENT_OPTION_THRESHOLD=0x01,EVENT_OPTION_INVERT=0x1 +UMASK_IDQ_UOPS_NOT_DELIVERED_CYCLES_FE_WAS_OK 0x01 + +EVENT_IDQ_BUBBLES 0x9C PMC +UMASK_IDQ_BUBBLES_CORE 0x01 +DEFAULT_OPTIONS_IDQ_BUBBLES_CYCLES_0_UOPS_DELIV_CORE EVENT_OPTION_THRESHOLD=0x06 +UMASK_IDQ_BUBBLES_CYCLES_0_UOPS_DELIV_CORE 0x01 +DEFAULT_OPTIONS_IDQ_BUBBLES_CYCLES_FE_WAS_OK EVENT_OPTION_THRESHOLD=0x01,EVENT_OPTION_INVERT=0x1 +UMASK_IDQ_BUBBLES_CYCLES_FE_WAS_OK 0x01 + +EVENT_RESOURCE_STALLS 0xA2 PMC +UMASK_RESOURCE_STALLS_SCOREBOARD 0x02 + +EVENT_CYCLE_ACTIVITY 0xA3 PMC +DEFAULT_OPTIONS_CYCLE_ACTIVITY_CYCLES_L2_MISS EVENT_OPTION_THRESHOLD=0x01 +UMASK_CYCLE_ACTIVITY_CYCLES_L2_MISS 0x01 +DEFAULT_OPTIONS_CYCLE_ACTIVITY_CYCLES_L3_MISS EVENT_OPTION_THRESHOLD=0x02 +UMASK_CYCLE_ACTIVITY_CYCLES_L3_MISS 0x02 +DEFAULT_OPTIONS_CYCLE_ACTIVITY_STALLS_TOTAL EVENT_OPTION_THRESHOLD=0x04 +UMASK_CYCLE_ACTIVITY_STALLS_TOTAL 0x04 +DEFAULT_OPTIONS_CYCLE_ACTIVITY_STALLS_L2_MISS EVENT_OPTION_THRESHOLD=0x05 +UMASK_CYCLE_ACTIVITY_STALLS_L2_MISS 0x05 +DEFAULT_OPTIONS_CYCLE_ACTIVITY_STALLS_L3_MISS EVENT_OPTION_THRESHOLD=0x06 +UMASK_CYCLE_ACTIVITY_STALLS_L3_MISS 0x06 +DEFAULT_OPTIONS_CYCLE_ACTIVITY_CYCLES_L1D_MISS EVENT_OPTION_THRESHOLD=0x08 +UMASK_CYCLE_ACTIVITY_CYCLES_L1D_MISS 0x08 +DEFAULT_OPTIONS_CYCLE_ACTIVITY_STALLS_L1D_MISS EVENT_OPTION_THRESHOLD=0x0C +UMASK_CYCLE_ACTIVITY_STALLS_L1D_MISS 0x0C +DEFAULT_OPTIONS_CYCLE_ACTIVITY_CYCLES_MEM_ANY EVENT_OPTION_THRESHOLD=0x10 +UMASK_CYCLE_ACTIVITY_CYCLES_MEM_ANY 0x10 + +EVENT_TOPDOWN 0x4C PMC +UMASK_TOPDOWN_SLOTS_P 0x01 +UMASK_TOPDOWN_BACKEND_BOUND_SLOTS 0x02 +UMASK_TOPDOWN_BAD_SPEC_SLOTS 0x04 +UMASK_TOPDOWN_BR_MISPREDICT_SLOTS 0x08 +UMASK_TOPDOWN_MEMORY_BOUND_SLOTS 0x10 + +EVENT_RS 0xA5 PMC +UMASK_RS_EMPTY_RESOURCE 0x01 +UMASK_RS_EMPTY 0x07 +DEFAULT_OPTIONS_RS_EMPTY_COUNT EVENT_OPTION_THRESHOLD=0x01,EVENT_OPTION_INVERT=0x1 +UMASK_RS_EMPTY_COUNT 0x07 + +EVENT_EXE_ACTIVITY 0xA6 PMC +UMASK_EXE_ACTIVITY_1_PORTS_UTIL 0x02 +UMASK_EXE_ACTIVITY_2_PORTS_UTIL 0x04 +UMASK_EXE_ACTIVITY_3_PORTS_UTIL 0x08 +UMASK_EXE_ACTIVITY_4_PORTS_UTIL 0x10 +UMASK_EXE_ACTIVITY_BOUND_ON_LOADS 0x21 +UMASK_EXE_ACTIVITY_BOUND_ON_STORES 0x40 +UMASK_EXE_ACTIVITY_EXE_BOUND_0_PORTS 0x80 +UMASK_EXE_ACTIVITY_2_3_PORTS_UTIL 0xC0 + +EVENT_LSD 0xA8 PMC +DEFAULT_OPTIONS_LSD_CYCLES_ACTIVE EVENT_OPTION_THRESHOLD=0x1 +UMASK_LSD_CYCLES_ACTIVE 0x01 +DEFAULT_OPTIONS_LSD_CYCLES_OK EVENT_OPTION_THRESHOLD=0x6 +UMASK_LSD_CYCLES_OK 0x01 +UMASK_LSD_UOPS 0x01 + +EVENT_INT_MISC 0xAD PMC +UMASK_INT_MISC_RECOVERY_CYCLES 0x01 +DEFAULT_OPTIONS_INT_MISC_CLEARS_COUNT EVENT_OPTION_THRESHOLD=0x01,EVENT_OPTION_EDGE=0x1 +UMASK_INT_MISC_CLEARS_COUNT 0x01 +UMASK_INT_MISC_UOP_DROPPING 0x10 +UMASK_INT_MISC_MBA_STALLS 0x20 +UMASK_INT_MISC_UNKNOWN_BRANCH_CYCLES 0x40 +UMASK_INT_MISC_CLEAR_RESTEER_CYCLES 0x80 + +EVENT_UOPS_ISSUED 0xAE PMC +UMASK_UOPS_ISSUED_ANY 0x01 +DEFAULT_OPTIONS_UOPS_ISSUED_CYCLES EVENT_OPTION_THRESHOLD=0x01 +UMASK_UOPS_ISSUED_CYCLES 0x01 + +EVENT_ARITH 0xD0 PMC +DEFAULT_OPTIONS_ARITH_FPDIV_ACTIVE EVENT_OPTION_THRESHOLD=0x01 +UMASK_ARITH_FPDIV_ACTIVE 0x01 +DEFAULT_OPTIONS_ARITH_IDIV_ACTIVE EVENT_OPTION_THRESHOLD=0x01 +UMASK_ARITH_IDIV_ACTIVE 0x08 +DEFAULT_OPTIONS_ARITH_DIV_ACTIVE EVENT_OPTION_THRESHOLD=0x01 +UMASK_ARITH_DIV_ACTIVE 0x09 + +EVENT_UOPS_EXECUTED 0xB1 PMC +UMASK_UOPS_EXECUTED_THREAD 0x01 +DEFAULT_OPTIONS_UOPS_EXECUTED_CYCLES_GE_1 EVENT_OPTION_THRESHOLD=0x01 +UMASK_UOPS_EXECUTED_CYCLES_GE_1 0x01 +DEFAULT_OPTIONS_UOPS_EXECUTED_CYCLES_GE_2 EVENT_OPTION_THRESHOLD=0x02 +UMASK_UOPS_EXECUTED_CYCLES_GE_2 0x01 +DEFAULT_OPTIONS_UOPS_EXECUTED_CYCLES_GE_3 EVENT_OPTION_THRESHOLD=0x03 +UMASK_UOPS_EXECUTED_CYCLES_GE_3 0x01 +DEFAULT_OPTIONS_UOPS_EXECUTED_CYCLES_GE_4 EVENT_OPTION_THRESHOLD=0x04 +UMASK_UOPS_EXECUTED_CYCLES_GE_4 0x01 +DEFAULT_OPTIONS_UOPS_EXECUTED_STALLS EVENT_OPTION_THRESHOLD=0x01,EVENT_OPTION_INVERT=0x1 +UMASK_UOPS_EXECUTED_STALLS 0x01 +UMASK_UOPS_EXECUTED_CORE 0x02 +DEFAULT_OPTIONS_UOPS_EXECUTED_CORE_CYCLES_GE_1 EVENT_OPTION_THRESHOLD=0x01 +UMASK_UOPS_EXECUTED_CORE_CYCLES_GE_1 0x02 +DEFAULT_OPTIONS_UOPS_EXECUTED_CORE_CYCLES_GE_2 EVENT_OPTION_THRESHOLD=0x02 +UMASK_UOPS_EXECUTED_CORE_CYCLES_GE_2 0x02 +DEFAULT_OPTIONS_UOPS_EXECUTED_CORE_CYCLES_GE_3 EVENT_OPTION_THRESHOLD=0x03 +UMASK_UOPS_EXECUTED_CORE_CYCLES_GE_3 0x02 +DEFAULT_OPTIONS_UOPS_EXECUTED_CORE_CYCLES_GE_4 EVENT_OPTION_THRESHOLD=0x04 +UMASK_UOPS_EXECUTED_CORE_CYCLES_GE_4 0x02 +DEFAULT_OPTIONS_UOPS_EXECUTED_CORE_STALLS EVENT_OPTION_THRESHOLD=0x01,EVENT_OPTION_INVERT=0x1 +UMASK_UOPS_EXECUTED_CORE_STALLS 0x02 +UMASK_UOPS_EXECUTED_X87 0x10 + +EVENT_UOPS_DISPATCHED 0xB2 PMC +UMASK_UOPS_DISPATCHED_PORT_0 0x01 +UMASK_UOPS_DISPATCHED_PORT_1 0x02 +UMASK_UOPS_DISPATCHED_PORT_2_3_10 0x04 +UMASK_UOPS_DISPATCHED_PORT_4_9 0x10 +UMASK_UOPS_DISPATCHED_PORT_5_11 0x20 +UMASK_UOPS_DISPATCHED_PORT_6 0x40 +UMASK_UOPS_DISPATCHED_PORT_7_8 0x80 + +EVENT_FP_ARITH_DISPATCHED 0xB3 PMC +UMASK_FP_ARITH_DISPATCHED_PORT_0 0x01 +UMASK_FP_ARITH_DISPATCHED_V0 0x01 +UMASK_FP_ARITH_DISPATCHED_PORT_1 0x02 +UMASK_FP_ARITH_DISPATCHED_V1 0x02 +UMASK_FP_ARITH_DISPATCHED_PORT_5 0x04 +UMASK_FP_ARITH_DISPATCHED_V2 0x04 + +EVENT_EXE 0xB7 PMC +UMASK_EXE_AMX_BUSY 0x02 + +EVENT_INST_RETIRED 0xC0 PMC +UMASK_INST_RETIRED_ANY_P 0x00 +UMASK_INST_RETIRED_NOP 0x02 +UMASK_INST_RETIRED_REP_ITERATION 0x08 +UMASK_INST_RETIRED_MACRO_FUSED 0x10 + +EVENT_ASSISTS 0xC1 PMC +UMASK_ASSISTS_FP 0x02 +UMASK_ASSISTS_PAGE_FAULT 0x08 +UMASK_ASSISTS_SSE_AVX_MIX 0x10 +UMASK_ASSISTS_ANY 0x1B + +EVENT_UOPS_RETIRED 0xC2 PMC +UMASK_UOPS_RETIRED_HEAVY 0x01 +UMASK_UOPS_RETIRED_SLOTS 0x02 +DEFAULT_OPTIONS_UOPS_RETIRED_STALLS EVENT_OPTION_THRESHOLD=0x01,EVENT_OPTION_INVERT=0x1 +UMASK_UOPS_RETIRED_STALLS 0x02 +DEFAULT_OPTIONS_UOPS_RETIRED_CYCLES EVENT_OPTION_THRESHOLD=0x01 +UMASK_UOPS_RETIRED_CYCLES 0x02 +# Has to be taken alone and required additional filtering. Not added +#UMASK_UOPS_RETIRED_MS 0x04 + +EVENT_MACHINE_CLEARS 0xC3 PMC +DEFAULT_OPTIONS_MACHINE_CLEARS_COUNT EVENT_OPTION_THRESHOLD=0x01,EVENT_OPTION_EDGE=0x1 +UMASK_MACHINE_CLEARS_COUNT 0x01 +UMASK_MACHINE_CLEARS_MEMORY_ORDERING 0x02 +UMASK_MACHINE_CLEARS_SMC 0x04 + +EVENT_BR_INST_RETIRED 0xC4 PMC +UMASK_BR_INST_RETIRED_ALL_BRANCHES 0x00 +UMASK_BR_INST_RETIRED_COND_TAKEN 0x01 +UMASK_BR_INST_RETIRED_NEAR_CALL 0x02 +UMASK_BR_INST_RETIRED_NEAR_RETURN 0x08 +UMASK_BR_INST_RETIRED_COND_NTAKEN 0x10 +UMASK_BR_INST_RETIRED_COND 0x11 +UMASK_BR_INST_RETIRED_NEAR_TAKEN 0x20 +UMASK_BR_INST_RETIRED_FAR_BRANCH 0x40 +UMASK_BR_INST_RETIRED_INDIRECT 0x80 + +EVENT_BR_MISP_RETIRED 0xC5 PMC +UMASK_BR_MISP_RETIRED_ALL_BRANCHES 0x00 +UMASK_BR_MISP_RETIRED_COND_TAKEN 0x01 +UMASK_BR_MISP_RETIRED_INDIRECT_CALL 0x02 +UMASK_BR_MISP_RETIRED_RET 0x08 +UMASK_BR_MISP_RETIRED_COND_NTAKEN 0x10 +UMASK_BR_MISP_RETIRED_COND 0x11 +UMASK_BR_MISP_RETIRED_NEAR_TAKEN 0x20 +UMASK_BR_MISP_RETIRED_COND_TAKEN_COST 0x41 +UMASK_BR_MISP_RETIRED_INDIRECT_CALL_COST 0x42 +UMASK_BR_MISP_RETIRED_ALL_CALL_COST 0x44 +UMASK_BR_MISP_RETIRED_RET_COST 0x48 +UMASK_BR_MISP_RETIRED_COND_NTAKEN_COST 0x50 +UMASK_BR_MISP_RETIRED_COND_COST 0x51 +UMASK_BR_MISP_RETIRED_NEAR_TAKEN_COST 0x60 +UMASK_BR_MISP_RETIRED_INDIRECT 0x80 +UMASK_BR_MISP_RETIRED_INDIRECT_COST 0xC0 + +# FRONTEND_RETIRED skipped +#EVENT_FRONTEND_RETIRED 0xC6 PMC +#DEFAULT_OPTION_FRONTEND_RETIRED_ANY_DSB_MISS EVENT_OPTION_MATCH0=0x1 +#UMAKS_FRONTEND_RETIRED_ANY_DSB_MISS 0x03 +#DEFAULT_OPTION_FRONTEND_RETIRED_MISP_ANT EVENT_OPTION_MATCH0=0x9 +#UMAKS_FRONTEND_RETIRED_MISP_ANT 0x02 +#DEFAULT_OPTION_FRONTEND_RETIRED_ANY_ANT EVENT_OPTION_MATCH0=0x9 +#UMAKS_FRONTEND_RETIRED_ANY_ANT 0x03 +#DEFAULT_OPTION_FRONTEND_RETIRED_LATE_SWPF EVENT_OPTION_MATCH0=0x9 +#UMAKS_FRONTEND_RETIRED_LATE_SWPF 0x03 +#DEFAULT_OPTION_FRONTEND_RETIRED_DSB_MISS EVENT_OPTION_MATCH0=0x11 +#UMAKS_FRONTEND_RETIRED_DSB_MISS 0x03 +#DEFAULT_OPTION_FRONTEND_RETIRED_ITLB_MISS EVENT_OPTION_MATCH0=0x14 +#UMAKS_FRONTEND_RETIRED_ITLB_MISS 0x03 +#DEFAULT_OPTION_FRONTEND_RETIRED_L1I_MISS EVENT_OPTION_MATCH0=0x12 +#UMAKS_FRONTEND_RETIRED_L1I_MISS 0x03 +#DEFAULT_OPTION_FRONTEND_RETIRED_L2_MISS EVENT_OPTION_MATCH0=0x13 +#UMAKS_FRONTEND_RETIRED_L2_MISS 0x03 +#DEFAULT_OPTION_FRONTEND_RETIRED_STLB_MISS EVENT_OPTION_MATCH0=0x15 +#UMAKS_FRONTEND_RETIRED_STLB_MISS 0x03 +#DEFAULT_OPTION_FRONTEND_RETIRED_MS_FLOWS EVENT_OPTION_MATCH0=0x8 +#UMAKS_FRONTEND_RETIRED_MS_FLOWS 0x03 +#DEFAULT_OPTION_FRONTEND_RETIRED_UNKNOWN_BRANCH EVENT_OPTION_MATCH0=0x17 +#UMAKS_FRONTEND_RETIRED_UNKNOWN_BRANCH 0x03 +#DEFAULT_OPTION_FRONTEND_RETIRED_LATENCY_GE_1 EVENT_OPTION_MATCH0=0x600106 +#UMAKS_FRONTEND_RETIRED_LATENCY_GE_1 0x03 +#DEFAULT_OPTION_FRONTEND_RETIRED_LATENCY_GE_2 EVENT_OPTION_MATCH0=0x600206 +#UMAKS_FRONTEND_RETIRED_LATENCY_GE_2 0x03 +#DEFAULT_OPTION_FRONTEND_RETIRED_LATENCY_GE_2_BUBBLES_GE_1 EVENT_OPTION_MATCH0=0x100206 +#UMASK_FRONTEND_RETIRED_LATENCY_GE_2_BUBBLES_GE_1 0x03 +#DEFAULT_OPTION_FRONTEND_RETIRED_LATENCY_GE_4 EVENT_OPTION_MATCH0=0x600406 +#UMAKS_FRONTEND_RETIRED_LATENCY_GE_4 0x03 +#DEFAULT_OPTION_FRONTEND_RETIRED_LATENCY_GE_8 EVENT_OPTION_MATCH0=0x600806 +#UMAKS_FRONTEND_RETIRED_LATENCY_GE_8 0x03 +#DEFAULT_OPTION_FRONTEND_RETIRED_LATENCY_GE_16 EVENT_OPTION_MATCH0=0x601006 +#UMAKS_FRONTEND_RETIRED_LATENCY_GE_16 0x03 +#DEFAULT_OPTION_FRONTEND_RETIRED_LATENCY_GE_32 EVENT_OPTION_MATCH0=0x602006 +#UMAKS_FRONTEND_RETIRED_LATENCY_GE_32 0x03 +#DEFAULT_OPTION_FRONTEND_RETIRED_LATENCY_GE_64 EVENT_OPTION_MATCH0=0x604006 +#UMAKS_FRONTEND_RETIRED_LATENCY_GE_64 0x03 +#DEFAULT_OPTION_FRONTEND_RETIRED_LATENCY_GE_128 EVENT_OPTION_MATCH0=0x608006 +#UMAKS_FRONTEND_RETIRED_LATENCY_GE_128 0x03 +#DEFAULT_OPTION_FRONTEND_RETIRED_LATENCY_GE_256 EVENT_OPTION_MATCH0=0x610006 +#UMAKS_FRONTEND_RETIRED_LATENCY_GE_256 0x03 +#DEFAULT_OPTION_FRONTEND_RETIRED_LATENCY_GE_512 EVENT_OPTION_MATCH0=0x620006 +#UMAKS_FRONTEND_RETIRED_LATENCY_GE_512 0x03 + +EVENT_FP_ARITH_INST_RETIRED 0xC7 PMC +UMASK_FP_ARITH_INST_RETIRED_SCALAR_DOUBLE 0x01 +UMASK_FP_ARITH_INST_RETIRED_SCALAR_SINGLE 0x02 +UMASK_FP_ARITH_INST_RETIRED_SCALAR 0x03 +UMASK_FP_ARITH_INST_RETIRED_128B_PACKED_DOUBLE 0x04 +UMASK_FP_ARITH_INST_RETIRED_128B_PACKED_SINGLE 0x08 +UMASK_FP_ARITH_INST_RETIRED_256B_PACKED_DOUBLE 0x10 +UMASK_FP_ARITH_INST_RETIRED_4_FLOPS 0x18 +UMASK_FP_ARITH_INST_RETIRED_256B_PACKED_SINGLE 0x20 +UMASK_FP_ARITH_INST_RETIRED_512B_PACKED_DOUBLE 0x40 +UMASK_FP_ARITH_INST_RETIRED_8_FLOPS 0x60 +UMASK_FP_ARITH_INST_RETIRED_512B_PACKED_SINGLE 0x80 +UMASK_FP_ARITH_INST_RETIRED_VECTOR 0xFC + +EVENT_FP_ARITH_INST_RETIRED2 0xCF PMC +UMASK_FP_ARITH_INST_RETIRED2_SCALAR_HALF 0x01 +UMASK_FP_ARITH_INST_RETIRED2_COMPLEX_SCALAR_HALF 0x02 +UMASK_FP_ARITH_INST_RETIRED2_SCALAR 0x03 +UMASK_FP_ARITH_INST_RETIRED2_128B_PACKED_HALF 0x04 +UMASK_FP_ARITH_INST_RETIRED2_256B_PACKED_HALF 0x08 +UMASK_FP_ARITH_INST_RETIRED2_512B_PACKED_HALF 0x10 +UMASK_FP_ARITH_INST_RETIRED2_VECTOR 0x1C + +EVENT_LBR_INSERTS 0xCC PMC +UMASK_LBR_INSERTS_LBR_INSERTS 0x20 + +#MEM_TRANS_RETIRED skipped + +EVENT_MEM_INST_RETIRED 0xD0 PMC +UMASK_MEM_INST_RETIRED_STLB_HIT_LOADS 0x09 +UMASK_MEM_INST_RETIRED_STLB_HIT_STORES 0x0A +UMASK_MEM_INST_RETIRED_STLB_MISS_LOADS 0x11 +UMASK_MEM_INST_RETIRED_STLB_MISS_STORES 0x12 +UMASK_MEM_INST_RETIRED_LOCK_LOADS 0x21 +UMASK_MEM_INST_RETIRED_SPLIT_LOADS 0x41 +UMASK_MEM_INST_RETIRED_SPLIT_STORES 0x42 +UMASK_MEM_INST_RETIRED_ALL_LOADS 0x81 +UMASK_MEM_INST_RETIRED_ALL_STORES 0x82 +UMASK_MEM_INST_RETIRED_ANY 0x83 + +EVENT_MEM_LOAD_RETIRED 0xD1 PMC +UMASK_MEM_LOAD_RETIRED_L1_HIT 0x01 +UMASK_MEM_LOAD_RETIRED_L2_HIT 0x02 +UMASK_MEM_LOAD_RETIRED_L3_HIT 0x04 +UMASK_MEM_LOAD_RETIRED_L1_MISS 0x08 +UMASK_MEM_LOAD_RETIRED_L2_MISS 0x10 +UMASK_MEM_LOAD_RETIRED_L3_MISS 0x20 +UMASK_MEM_LOAD_RETIRED_FB_HIT 0x40 + +EVENT_MEM_LOAD_L3_HIT_RETIRED 0xD2 PMC +UMASK_MEM_LOAD_L3_HIT_RETIRED_XSNP_MISS 0x01 +UMASK_MEM_LOAD_L3_HIT_RETIRED_XSNP_NO_FWD 0x02 +UMASK_MEM_LOAD_L3_HIT_RETIRED_XSNP_FWD 0x04 +UMASK_MEM_LOAD_L3_HIT_RETIRED_XSNP_NONE 0x08 + +EVENT_MEM_LOAD_L3_MISS_RETIRED 0xD3 PMC +UMASK_MEM_LOAD_L3_MISS_RETIRED_LOCAL_DRAM 0x01 +UMASK_MEM_LOAD_L3_MISS_RETIRED_REMOTE_DRAM 0x02 +UMASK_MEM_LOAD_L3_MISS_RETIRED_REMOTE_HITM 0x04 +UMASK_MEM_LOAD_L3_MISS_RETIRED_REMOTE_FWD 0x08 + +EVENT_MEM_LOAD_MISC_RETIRED_UC 0xD4 PMC +UMASK_MEM_LOAD_MISC_RETIRED_UC 0x04 + +EVENT_MISC2_RETIRED_LFENCE 0xE0 PMC +UMASK_MISC2_RETIRED_LFENCE 0x20 + +EVENT_MEM_UOP_RETIRED_ANY 0xE5 PMC +UMASK_MEM_UOP_RETIRED_ANY 0x03 + +EVENT_INT_VEC_RETIRED 0xE7 PMC +UMASK_INT_VEC_RETIRED_ADD_128 0x03 +UMASK_INT_VEC_RETIRED_ADD_256 0x0C +UMASK_INT_VEC_RETIRED_VNNI_128 0x10 +UMASK_INT_VEC_RETIRED_128BIT 0x13 +UMASK_INT_VEC_RETIRED_VNNI_256 0x20 +UMASK_INT_VEC_RETIRED_SHUFFLES 0x40 +UMASK_INT_VEC_RETIRED_MUL_256 0x80 +UMASK_INT_VEC_RETIRED_256BIT 0xAC + +EVENT_CPU_CLK_UNHALTED 0xEC PMC +UMASK_CPU_CLK_UNHALTED_DISTRIBUTED 0x02 +UMASK_CPU_CLK_UNHALTED_C01 0x10 +UMASK_CPU_CLK_UNHALTED_C02 0x20 +UMASK_CPU_CLK_UNHALTED_PAUSE 0x40 +DEFAULT_OPTIONS_CPU_CLK_UNHALTED_PAUSE_INST EVENT_OPTION_THRESHOLD=0x01 +UMASK_CPU_CLK_UNHALTED_PAUSE_INST 0x40 +UMASK_CPU_CLK_UNHALTED_C0_WAIT 0x70 + +EVENT_OFFCORE_RESPONSE_0 0x2A PMC +OPTIONS_OFFCORE_RESPONSE_0_OPTIONS EVENT_OPTION_MATCH0_MASK|EVENT_OPTION_MATCH1_MASK +UMASK_OFFCORE_RESPONSE_0_OPTIONS 0x01 0xFF 0xFF + +EVENT_OFFCORE_RESPONSE_1 0x2B PMC +OPTIONS_OFFCORE_RESPONSE_1_OPTIONS EVENT_OPTION_MATCH0_MASK|EVENT_OPTION_MATCH1_MASK +UMASK_OFFCORE_RESPONSE_1_OPTIONS 0x01 0xFF 0xFF + +# https://github.com/intel/perfmon/blob/main/GNR/events/graniterapids_uncore_experimental.json +# https://github.com/intel/perfmon/blob/main/GNR/events/graniterapids_uncore.json +# v1.03 + +####################################################### +# UBOX == UBOX # +####################################################### + +EVENT_UNCORE_CLOCKTICKS 0x01 UBOX +UMASK_UNCORE_CLOCKTICKS 0x00 + +####################################################### +# MBOX == iMC # +####################################################### + +EVENT_MBOX_CLOCKTICKS 0x01 MBOX +UMASK_MBOX_CLOCKTICKS 0x00 + +EVENT_ACT_COUNT 0x02 MBOX +UMASK_ACT_COUNT_RD 0xF1 +UMASK_ACT_COUNT_WR 0xF2 +UMASK_ACT_COUNT_UFILL 0xF4 +UMASK_ACT_COUNT_ALL 0xF7 + +EVENT_PRE_COUNT 0x03 MBOX +UMASK_PRE_COUNT_RD 0xF1 +UMASK_PRE_COUNT_WR 0xF2 +UMASK_PRE_COUNT_UFILL 0xF4 +UMASK_PRE_COUNT_PGT 0xF8 +UMASK_PRE_COUNT_ALL 0xFF + +EVENT_CAS_COUNT_SCH0 0x05 MBOX +UMASK_CAS_COUNT_SCH0_RD_REG 0xC1 +UMASK_CAS_COUNT_SCH0_RD_UNDERFILL 0xC4 +UMASK_CAS_COUNT_SCH0_RD 0xCF +UMASK_CAS_COUNT_SCH0_WR_PRE 0xE0 +UMASK_CAS_COUNT_SCH0_WR_NONPRE 0xD0 +UMASK_CAS_COUNT_SCH0_WR 0xF0 +UMASK_CAS_COUNT_SCH0_ALL 0xFF + +EVENT_CAS_COUNT_SCH1 0x06 MBOX +UMASK_CAS_COUNT_SCH1_RD_REG 0xC1 +UMASK_CAS_COUNT_SCH1_RD_UNDERFILL 0xC4 +UMASK_CAS_COUNT_SCH1_RD 0xCF +UMASK_CAS_COUNT_SCH1_WR_PRE 0xE0 +UMASK_CAS_COUNT_SCH1_WR_NONPRE 0xD0 +UMASK_CAS_COUNT_SCH1_WR 0xF0 +UMASK_CAS_COUNT_SCH1_ALL 0xFF + +EVENT_RPQ_INSERTS 0x10 MBOX +UMASK_RPQ_INSERTS_SCH0_PCH0 0x10 +UMASK_RPQ_INSERTS_SCH0_PCH1 0x20 +# Added by Thomas Gruber +UMASK_RPQ_INSERTS_SCH0_ANY 0x30 +UMASK_RPQ_INSERTS_SCH1_PCH0 0x40 +UMASK_RPQ_INSERTS_SCH1_PCH1 0x80 +# Added by Thomas Gruber +UMASK_RPQ_INSERTS_SCH1_ANY 0xC0 +UMASK_RPQ_INSERTS_ANY_ANY 0xF0 + +EVENT_WPQ_INSERTS 0x22 MBOX +UMASK_WPQ_INSERTS_SCH0_PCH0 0x10 +UMASK_WPQ_INSERTS_SCH0_PCH1 0x20 +# Added by Thomas Gruber +UMASK_WPQ_INSERTS_SCH0_ANY 0x30 +UMASK_WPQ_INSERTS_SCH1_PCH0 0x40 +UMASK_WPQ_INSERTS_SCH1_PCH1 0x80 +# Added by Thomas Gruber +UMASK_WPQ_INSERTS_SCH1_ANY 0xC0 +UMASK_WPQ_INSERTS_ANY_ANY 0xF0 + +EVENT_RDB_INSERTS 0x17 MBOX +UMASK_RDB_INSERTS_SCH0 0x40 +UMASK_RDB_INSERTS_SCH1 0x80 + +EVENT_RDB_OCCUPANCY_SCH0 0x1A MBOX +UMASK_RDB_OCCUPANCY_SCH0 0x00 + +EVENT_RDB_OCCUPANCY_SCH1 0x1B MBOX +UMASK_RDB_OCCUPANCY_SCH1 0x00 + +EVENT_RPQ_OCCUPANCY_SCH0_PCH0 0x80 MBOX +UMASK_RPQ_OCCUPANCY_SCH0_PCH0 0x00 + +EVENT_RPQ_OCCUPANCY_SCH0_PCH1 0x81 MBOX +UMASK_RPQ_OCCUPANCY_SCH0_PCH1 0x00 + +EVENT_RPQ_OCCUPANCY_SCH1_PCH0 0x82 MBOX +UMASK_RPQ_OCCUPANCY_SCH1_PCH0 0x00 + +EVENT_RPQ_OCCUPANCY_SCH1_PCH1 0x83 MBOX +UMASK_RPQ_OCCUPANCY_SCH1_PCH1 0x00 + +EVENT_WPQ_OCCUPANCY_SCH0_PCH0 0x84 MBOX +UMASK_WPQ_OCCUPANCY_SCH0_PCH0 0x00 + +EVENT_WPQ_OCCUPANCY_SCH0_PCH1 0x85 MBOX +UMASK_WPQ_OCCUPANCY_SCH0_PCH1 0x00 + +EVENT_WPQ_OCCUPANCY_SCH1_PCH0 0x86 MBOX +UMASK_WPQ_OCCUPANCY_SCH1_PCH0 0x00 + +EVENT_WPQ_OCCUPANCY_SCH1_PCH1 0x87 MBOX +UMASK_WPQ_OCCUPANCY_SCH1_PCH1 0x00 + +EVENT_POWERDOWN_CYCLES 0x47 MBOX +UMASK_POWERDOWN_CYCLES_SCH0_RANK0 0x01 +UMASK_POWERDOWN_CYCLES_SCH0_RANK1 0x02 +UMASK_POWERDOWN_CYCLES_SCH0_RANK2 0x04 +UMASK_POWERDOWN_CYCLES_SCH0_RANK3 0x08 +UMASK_POWERDOWN_CYCLES_SCH1_RANK0 0x10 +UMASK_POWERDOWN_CYCLES_SCH1_RANK1 0x20 +UMASK_POWERDOWN_CYCLES_SCH1_RANK2 0x40 +UMASK_POWERDOWN_CYCLES_SCH1_RANK3 0x80 +#Added by T.Gruber +UMASK_POWERDOWN_CYCLES_SCH0_ANYRANK 0x0F +UMASK_POWERDOWN_CYCLES_SCH1_ANYRANK 0xF0 +UMASK_POWERDOWN_CYCLES_ANY 0xFF + +EVENT_POWER_CHANNEL_PPD_CYCLES 0x88 MBOX +UMASK_POWER_CHANNEL_PPD_CYCLES 0x00 + +EVENT_SELF_REFRESH 0x43 MBOX +UMASK_SELF_REFRESH_ENTER_SUCCESS_CYCLES 0x01 +UMASK_SELF_REFRESH_ENTER_SUCCESS 0x02 + +#EVENT_MBOX_CLOCKTICKS_DCLK 0x00 MBOX0FIX|MBOX1FIX|MBOX2FIX|MBOX3FIX|MBOX4FIX|MBOX5FIX|MBOX6FIX|MBOX7FIX|MBOX8FIX|MBOX9FIX|MBOX10FIX|MBOX11FIX|MBOX12FIX|MBOX13FIX|MBOX14FIX|MBOX15FIX +#UMASK_MBOX_CLOCKTICKS_DCLK 0x00 + +####################################################### +# MDF == MDF # +####################################################### + +EVENT_MDF_CLOCKTICKS 0x01 MDF +UMASK_MDF_CLOCKTICKS 0x00 + +EVENT_RXR_INSERTS 0x12 MDF +UMASK_RXR_INSERTS_AD_BNC 0x01 +UMASK_RXR_INSERTS_AK 0x02 +UMASK_RXR_INSERTS_BL_BNC 0x04 +UMASK_RXR_INSERTS_IV 0x08 +UMASK_RXR_INSERTS_AD_CRD 0x10 +UMASK_RXR_INSERTS_BL_CRD 0x20 + +EVENT_RXR_OCCUPANCY 0x13 MDF +UMASK_RXR_OCCUPANCY_AD_BNC 0x01 +UMASK_RXR_OCCUPANCY_AK 0x02 +UMASK_RXR_OCCUPANCY_BL_BNC 0x04 +UMASK_RXR_OCCUPANCY_IV 0x08 +UMASK_RXR_OCCUPANCY_AD_CRD 0x10 +UMASK_RXR_OCCUPANCY_BL_CRD 0x20 + +EVENT_RXR_BYPASS 0x14 MDF +UMASK_RXR_BYPASS_AD_BNC 0x01 +UMASK_RXR_BYPASS_AK 0x02 +UMASK_RXR_BYPASS_BL_BNC 0x04 +UMASK_RXR_BYPASS_IV 0x08 +UMASK_RXR_BYPASS_AD_CRD 0x10 +UMASK_RXR_BYPASS_BL_CRD 0x20 + +EVENT_TXR_INSERTS 0x1C MDF +UMASK_TXR_INSERTS_AD_BNC 0x01 +UMASK_TXR_INSERTS_AK 0x02 +UMASK_TXR_INSERTS_BL_BNC 0x04 +UMASK_TXR_INSERTS_IV 0x08 +UMASK_TXR_INSERTS_AD_CRD 0x10 +UMASK_TXR_INSERTS_BL_CRD 0x20 + +EVENT_TXR_OCCUPANCY 0x1D MDF +UMASK_TXR_OCCUPANCY_AD_BNC 0x01 +UMASK_TXR_OCCUPANCY_AK 0x02 +UMASK_TXR_OCCUPANCY_BL_BNC 0x04 +UMASK_TXR_OCCUPANCY_IV 0x08 +UMASK_TXR_OCCUPANCY_AD_CRD 0x10 +UMASK_TXR_OCCUPANCY_BL_CRD 0x20 + +EVENT_TXR_BYPASS 0x1E MDF +UMASK_TXR_BYPASS_AD_BNC 0x01 +UMASK_TXR_BYPASS_AK 0x02 +UMASK_TXR_BYPASS_BL_BNC 0x04 +UMASK_TXR_BYPASS_IV 0x08 +UMASK_TXR_BYPASS_AD_CRD 0x10 +UMASK_TXR_BYPASS_BL_CRD 0x20 + +####################################################### +# UPI == UPI LL # +####################################################### + +EVENT_UPI_CLOCKTICKS 0x01 UPI +UMASK_UPI_CLOCKTICKS 0x00 + +EVENT_TXL_FLITS 0x02 UPI +UMASK_TXL_FLITS_SLOT0 0x01 +UMASK_TXL_FLITS_SLOT1 0x02 +UMASK_TXL_FLITS_SLOT2 0x04 +UMASK_TXL_FLITS_DATA 0x08 +UMASK_TXL_FLITS_LLCRD 0x10 +UMASK_TXL_FLITS_NULL 0x20 +UMASK_TXL_FLITS_LLCTRL 0x40 +UMASK_TXL_FLITS_PROTHDR 0x80 +UMASK_TXL_FLITS_IDLE 0x47 +UMASK_TXL_FLITS_ALL_PROTHDR 0x87 +UMASK_TXL_FLITS_ALL_LLCTRL 0x47 +UMASK_TXL_FLITS_ALL_LLCRD 0x17 +# Added by T. Gruber +UMASK_TXL_FLITS_DATA_SLOT0 0x09 +# Added by T. Gruber +UMASK_TXL_FLITS_DATA_SLOT1 0x0A +# Added by T. Gruber +UMASK_TXL_FLITS_DATA_SLOT2 0x0C +# Added by T. Gruber +UMASK_TXL_FLITS_ALL_DATA 0x0F +UMASK_TXL_FLITS_ALL_NULL 0x27 +UMASK_TXL_FLITS_NON_DATA 0x97 + +EVENT_RXL_FLITS 0x03 UPI +UMASK_RXL_FLITS_SLOT0 0x01 +UMASK_RXL_FLITS_SLOT1 0x02 +UMASK_RXL_FLITS_SLOT2 0x04 +UMASK_RXL_FLITS_DATA 0x08 +UMASK_RXL_FLITS_LLCRD 0x10 +UMASK_RXL_FLITS_NULL 0x20 +UMASK_RXL_FLITS_LLCTRL 0x40 +UMASK_RXL_FLITS_PROTHDR 0x80 +UMASK_RXL_FLITS_IDLE 0x47 +# Added by T. Gruber +UMASK_RXL_FLITS_DATA_SLOT0 0x09 +# Added by T. Gruber +UMASK_RXL_FLITS_DATA_SLOT1 0x0A +# Added by T. Gruber +UMASK_RXL_FLITS_DATA_SLOT2 0x0C +UMASK_RXL_FLITS_ALL_DATA 0x0F +UMASK_RXL_FLITS_NON_DATA 0x97 + +EVENT_TXL_BASIC_HDR_MATCH 0x04 UPI +OPTIONS_TXL_BASIC_HDR_MATCH EVENT_OPTION_MATCH0_MASK +UMASK_TXL_BASIC_HDR_MATCH_REQ 0x08 +DEFAULT_OPTIONS_TXL_BASIC_HDR_MATCH_REQ_OPC EVENT_OPTION_MATCH0=0x01 +UMASK_TXL_BASIC_HDR_MATCH_REQ_OPC 0x08 +UMASK_TXL_BASIC_HDR_MATCH_SNP 0x09 +DEFAULT_OPTIONS_TXL_BASIC_HDR_MATCH_SNP_OPC EVENT_OPTION_MATCH0=0x01 +UMASK_TXL_BASIC_HDR_MATCH_SNP_OPC 0x09 +UMASK_TXL_BASIC_HDR_MATCH_RSP_NODATA 0x0A +DEFAULT_OPTIONS_TXL_BASIC_HDR_MATCH_RSP_NODATA_OPC EVENT_OPTION_MATCH0=0x01 +UMASK_TXL_BASIC_HDR_MATCH_RSP_NODATA_OPC 0x0A +UMASK_TXL_BASIC_HDR_MATCH_RSP_DATA 0x0C +DEFAULT_OPTIONS_TXL_BASIC_HDR_MATCH_RSP_DATA_OPC EVENT_OPTION_MATCH0=0x01 +UMASK_TXL_BASIC_HDR_MATCH_RSP_DATA_OPC 0x0C +UMASK_TXL_BASIC_HDR_MATCH_WB 0x0D +DEFAULT_OPTIONS_TXL_BASIC_HDR_MATCH_WB_OPC EVENT_OPTION_MATCH0=0x01 +UMASK_TXL_BASIC_HDR_MATCH_WB_OPC 0x0D +UMASK_TXL_BASIC_HDR_MATCH_NCB 0x0E +DEFAULT_OPTIONS_TXL_BASIC_HDR_MATCH_NCB_OPC EVENT_OPTION_MATCH0=0x01 +UMASK_TXL_BASIC_HDR_MATCH_NCB_OPC 0x0E +UMASK_TXL_BASIC_HDR_MATCH_NCS 0x0F +DEFAULT_OPTIONS_TXL_BASIC_HDR_MATCH_NCS_OPC EVENT_OPTION_MATCH0=0x01 +UMASK_TXL_BASIC_HDR_MATCH_NCS_OPC 0x0F +DEFAULT_OPTIONS_TXL_BASIC_HDR_MATCH_RSPI EVENT_OPTION_MATCH0=0x01 +UMASK_TXL_BASIC_HDR_MATCH_RSPI 0x2A +DEFAULT_OPTIONS_TXL_BASIC_HDR_MATCH_RSPCNFLT EVENT_OPTION_MATCH0=0x01 +UMASK_TXL_BASIC_HDR_MATCH_RSPCNFLT 0xAA + +EVENT_RXL_BASIC_HDR_MATCH 0x05 UPI +OPTIONS_RXL_BASIC_HDR_MATCH EVENT_OPTION_MATCH0_MASK +UMASK_RXL_BASIC_HDR_MATCH_REQ 0x08 +DEFAULT_OPTIONS_RXL_BASIC_HDR_MATCH_REQ_OPC EVENT_OPTION_MATCH0=0x01 +UMASK_RXL_BASIC_HDR_MATCH_REQ_OPC 0x08 +UMASK_RXL_BASIC_HDR_MATCH_SNP 0x09 +DEFAULT_OPTIONS_RXL_BASIC_HDR_MATCH_SNP_OPC EVENT_OPTION_MATCH0=0x01 +UMASK_RXL_BASIC_HDR_MATCH_SNP_OPC 0x09 +UMASK_RXL_BASIC_HDR_MATCH_RSP_NODATA 0x0A +DEFAULT_OPTIONS_RXL_BASIC_HDR_MATCH_RSP_NODATA_OPC EVENT_OPTION_MATCH0=0x01 +UMASK_RXL_BASIC_HDR_MATCH_RSP_NODATA_OPC 0x0A +UMASK_RXL_BASIC_HDR_MATCH_RSP_DATA 0x0C +DEFAULT_OPTIONS_RXL_BASIC_HDR_MATCH_RSP_DATA_OPC EVENT_OPTION_MATCH0=0x01 +UMASK_RXL_BASIC_HDR_MATCH_RSP_DATA_OPC 0x0C +UMASK_RXL_BASIC_HDR_MATCH_WB 0x0D +DEFAULT_OPTIONS_RXL_BASIC_HDR_MATCH_WB_OPC EVENT_OPTION_MATCH0=0x01 +UMASK_RXL_BASIC_HDR_MATCH_WB_OPC 0x0D +UMASK_RXL_BASIC_HDR_MATCH_NCB 0x0E +DEFAULT_OPTIONS_RXL_BASIC_HDR_MATCH_NCB_OPC EVENT_OPTION_MATCH0=0x01 +UMASK_RXL_BASIC_HDR_MATCH_NCB_OPC 0x0E +UMASK_RXL_BASIC_HDR_MATCH_NCS 0x0F +DEFAULT_OPTIONS_RXL_BASIC_HDR_MATCH_NCS_OPC EVENT_OPTION_MATCH0=0x01 +UMASK_RXL_BASIC_HDR_MATCH_NCS_OPC 0x0F +DEFAULT_OPTIONS_RXL_BASIC_HDR_MATCH_RSPI EVENT_OPTION_MATCH0=0x01 +UMASK_RXL_BASIC_HDR_MATCH_RSPI 0x2A +DEFAULT_OPTIONS_RXL_BASIC_HDR_MATCH_RSPCNFLT EVENT_OPTION_MATCH0=0x01 +UMASK_RXL_BASIC_HDR_MATCH_RSPCNFLT 0xAA + +EVENT_L1_POWER_CYCLES 0x21 UPI +UMASK_L1_POWER_CYCLES 0x00 + +EVENT_TXL0P_POWER_CYCLES 0x27 UPI +UMASK_TXL0P_POWER_CYCLES 0x00 + +EVENT_TXL0P_POWER_CYCLES_LL_ENTER 0x28 UPI +EVENT_TXL0P_POWER_CYCLES_LL_ENTER 0x00 + +EVENT_TXL0P_POWER_CYCLES_M3_EXIT 0x29 UPI +UMASK_TXL0P_POWER_CYCLES_M3_EXIT 0x00 + +EVENT_RXL_INSERTS 0x30 UPI +UMASK_RXL_INSERTS_SLOT0 0x01 +UMASK_RXL_INSERTS_SLOT1 0x02 +UMASK_RXL_INSERTS_SLOT2 0x04 + +EVENT_RXL_OCCUPANCY 0x32 UPI +UMASK_RXL_OCCUPANCY_SLOT0 0x01 +UMASK_RXL_OCCUPANCY_SLOT1 0x02 +UMASK_RXL_OCCUPANCY_SLOT2 0x04 + +EVENT_TXL_INSERTS 0x40 UPI +UMASK_TXL_INSERTS 0x00 + +EVENT_TXL_OCCUPANCY 0x42 UPI +UMASK_TXL_OCCUPANCY 0x00 + +####################################################### +# CBOX == CHA # +####################################################### + +EVENT_CBOX_CLOCKTICKS 0x01 CBOX +UMASK_CBOX_CLOCKTICKS 0x00 + +EVENT_CHA_CLOCKTICKS 0x01 CBOX +UMASK_CHA_CLOCKTICKS 0x00 + +EVENT_DISTRESS_ASSERTED 0x59 CBOX +UMASK_DISTRESS_ASSERTED_DPT_IRQ 0x01 +UMASK_DISTRESS_ASSERTED_DPT_TOR 0x02 +UMASK_DISTRESS_ASSERTED_DPT_ANY 0x03 + +EVENT_TOR_INSERTS 0x35 CBOX +OPTIONS_TOR_INSERTS EVENT_OPTION_MATCH0_MASK +DEFAULT_OPTIONS_TOR_INSERTS_LLC_OR_SF_EVICTIONS EVENT_OPTION_MATCH0=0x00C001FF +UMASK_TOR_INSERTS_LLC_OR_SF_EVICTIONS 0x02 +DEFAULT_OPTIONS_TOR_INSERTS_IO_ITOMCACHENEAR_LOCAL EVENT_OPTION_MATCH0=0x00CD42FF +UMASK_TOR_INSERTS_IO_ITOMCACHENEAR_LOCAL 0x04 +DEFAULT_OPTIONS_TOR_INSERTS_IO_ITOMCACHENEAR_REMOTE EVENT_OPTION_MATCH0=0x00CD437F +UMASK_TOR_INSERTS_IO_ITOMCACHENEAR_REMOTE 0x04 +DEFAULT_OPTIONS_TOR_INSERTS_IO_ITOM_LOCAL EVENT_OPTION_MATCH0=0x00CC42FF +UMASK_TOR_INSERTS_IO_ITOM_LOCAL 0x04 +DEFAULT_OPTIONS_TOR_INSERTS_IO_ITOM_REMOTE EVENT_OPTION_MATCH0=0x00CC437F +UMASK_TOR_INSERTS_IO_ITOM_REMOTE 0x04 +DEFAULT_OPTIONS_TOR_INSERTS_IO_PCIRDCUR_LOCAL EVENT_OPTION_MATCH0=0x00C8F2FF +UMASK_TOR_INSERTS_IO_PCIRDCUR_LOCAL 0x04 +DEFAULT_OPTIONS_TOR_INSERTS_IO_PCIRDCUR_REMOTE EVENT_OPTION_MATCH0=0x00C8F37F +UMASK_TOR_INSERTS_IO_PCIRDCUR_REMOTE 0x04 + + +EVENT_TOR_OCCUPANCY 0x36 CBOX0C0|CBOX1C0|CBOX2C0|CBOX3C0|CBOX4C0|CBOX5C0|CBOX6C0|CBOX7C0|CBOX8C0|CBOX9C0|CBOX10C0|CBOX11C0|CBOX12C0|CBOX13C0|CBOX14C0|CBOX15C0|CBOX16C0|CBOX17C0|CBOX18C0|CBOX19C0|CBOX20C0|CBOX21C0|CBOX22C0|CBOX23C0|CBOX24C0|CBOX25C0|CBOX26C0|CBOX27C0|CBOX28C0|CBOX29C0|CBOX30C0|CBOX31C0|CBOX32C0|CBOX33C0|CBOX34C0|CBOX35C0|CBOX36C0|CBOX37C0|CBOX38C0|CBOX39C0|CBOX40C0|CBOX41C0|CBOX42C0|CBOX43C0|CBOX44C0|CBOX45C0|CBOX46C0|CBOX47C0|CBOX48C0|CBOX49C0|CBOX50C0|CBOX51C0|CBOX52C0|CBOX53C0|CBOX54C0|CBOX55C0|CBOX56C0|CBOX57C0|CBOX58C0|CBOX59C0|CBOX60C0|CBOX61C0|CBOX62C0|CBOX63C0|CBOX64C0|CBOX65C0|CBOX66C0|CBOX67C0|CBOX68C0|CBOX69C0|CBOX70C0|CBOX71C0|CBOX72C0|CBOX73C0|CBOX74C0|CBOX75C0|CBOX76C0|CBOX77C0|CBOX78C0|CBOX79C0|CBOX80C0|CBOX81C0|CBOX82C0|CBOX83C0|CBOX84C0|CBOX85C0|CBOX86C0|CBOX87C0|CBOX88C0|CBOX89C0|CBOX90C0|CBOX91C0|CBOX92C0|CBOX93C0|CBOX94C0|CBOX95C0|CBOX96C0|CBOX97C0|CBOX98C0|CBOX99C0|CBOX100C0|CBOX101C0|CBOX102C0|CBOX103C0|CBOX104C0|CBOX105C0|CBOX106C0|CBOX107C0|CBOX108C0|CBOX109C0|CBOX110C0|CBOX111C0|CBOX112C0|CBOX113C0|CBOX114C0|CBOX115C0|CBOX116C0|CBOX117C0|CBOX118C0|CBOX119C0|CBOX120C0|CBOX121C0|CBOX122C0|CBOX123C0|CBOX124C0|CBOX125C0 +OPTIONS_TOR_OCCUPANCY EVENT_OPTION_MATCH0_MASK +DEFAULT_OPTIONS_TOR_OCCUPANCY_IO_MISS_PCIRDCUR_REMOTE EVENT_OPTION_MATCH0=0x00C8F37E +UMASK_TOR_OCCUPANCY_IO_MISS_PCIRDCUR_REMOTE 0x04 +DEFAULT_OPTIONS_TOR_OCCUPANCY_IO_MISS_PCIRDCUR_LOCAL EVENT_OPTION_MATCH0=0x00C8F2FE +UMASK_TOR_OCCUPANCY_IO_MISS_PCIRDCUR_LOCAL 0x04 +DEFAULT_OPTIONS_TOR_OCCUPANCY_IO_MISS_ITOM_REMOTE EVENT_OPTION_MATCH0=0x00CC437E +UMASK_TOR_OCCUPANCY_IO_MISS_ITOM_REMOTE 0x04 +DEFAULT_OPTIONS_TOR_OCCUPANCY_IO_MISS_ITOM_LOCAL EVENT_OPTION_MATCH0=0x00CC42FE +UMASK_TOR_OCCUPANCY_IO_MISS_ITOM_LOCAL 0x04 +DEFAULT_OPTIONS_TOR_OCCUPANCY_IO_MISS_ITOMCACHENEAR_REMOTE EVENT_OPTION_MATCH0=0x00CD437E +UMASK_TOR_OCCUPANCY_IO_MISS_ITOMCACHENEAR_REMOTE 0x04 +DEFAULT_OPTIONS_TOR_OCCUPANCY_IO_MISS_ITOMCACHENEAR_LOCAL EVENT_OPTION_MATCH0=0x00CD42FE +UMASK_TOR_OCCUPANCY_IO_MISS_ITOMCACHENEAR_LOCAL 0x04 + + +EVENT_LLC_VICTIMS 0x37 CBOX +OPTIONS_LLC_VICTIMS EVENT_OPTION_MATCH0_MASK +DEFAULT_OPTIONS_LLC_VICTIMS_LOCAL_M EVENT_OPTION_MATCH0=0x00000020 +UMASK_LLC_VICTIMS_LOCAL_M 0x01 +DEFAULT_OPTIONS_LLC_VICTIMS_LOCAL_E EVENT_OPTION_MATCH0=0x00000020 +UMASK_LLC_VICTIMS_LOCAL_E 0x02 +DEFAULT_OPTIONS_LLC_VICTIMS_LOCAL_S EVENT_OPTION_MATCH0=0x00000020 +UMASK_LLC_VICTIMS_LOCAL_S 0x04 +DEFAULT_OPTIONS_LLC_VICTIMS_LOCAL_F EVENT_OPTION_MATCH0=0x00000020 +UMASK_LLC_VICTIMS_LOCAL_F 0x08 +DEFAULT_OPTIONS_LLC_VICTIMS_REMOTE_M EVENT_OPTION_MATCH0=0x00000080 +UMASK_LLC_VICTIMS_REMOTE_M 0x01 +DEFAULT_OPTIONS_LLC_VICTIMS_REMOTE_E EVENT_OPTION_MATCH0=0x00000080 +UMASK_LLC_VICTIMS_REMOTE_E 0x02 +DEFAULT_OPTIONS_LLC_VICTIMS_REMOTE_S EVENT_OPTION_MATCH0=0x00000080 +UMASK_LLC_VICTIMS_REMOTE_S 0x04 + +EVENT_REMOTE_SF 0x69 CBOX +UMASK_REMOTE_SF_HIT 0x01 +UMASK_REMOTE_SF_HIT_EXCLUSIVE 0x02 +UMASK_REMOTE_SF_MISS 0x04 +UMASK_REMOTE_SF_ALLOC_SHARED 0x08 +UMASK_REMOTE_SF_ALLOC_EXCLUSIVE 0x10 +UMASK_REMOTE_SF_DEALLOC_EVCTCLN 0x40 +UMASK_REMOTE_SF_UPDATE_SHARED 0x80 +OPTIONS_REMOTE_SF_UPDATE_EXCLUSIVE EVENT_OPTION_MATCH0_MASK +DEFAULT_OPTIONS_REMOTE_SF_UPDATE_EXCLUSIVE EVENT_OPTION_MATCH0=0x00000001 +UMASK_REMOTE_SF_UPDATE_EXCLUSIVE 0x00 +OPTIONS_REMOTE_SF_VICTIM_SHARED EVENT_OPTION_MATCH0_MASK +DEFAULT_OPTIONS_REMOTE_SF_VICTIM_SHARED EVENT_OPTION_MATCH0=0x00000002 +UMASK_REMOTE_SF_VICTIM_SHARED 0x00 +OPTIONS_REMOTE_SF_VICTIM_EXCLUSIVE EVENT_OPTION_MATCH0_MASK +DEFAULT_OPTIONS_REMOTE_SF_VICTIM_EXCLUSIVE EVENT_OPTION_MATCH0=0x00000004 +UMASK_REMOTE_SF_VICTIM_EXCLUSIVE 0x00 +OPTIONS_REMOTE_SF_INCLUSIVE_ONLY EVENT_OPTION_MATCH0_MASK +DEFAULT_OPTIONS_REMOTE_SF_INCLUSIVE_ONLY EVENT_OPTION_MATCH0=0x00000020 +UMASK_REMOTE_SF_INCLUSIVE_ONLY 0x00 +OPTIONS_REMOTE_SF_DIRBACKED_ONLY EVENT_OPTION_MATCH0_MASK +DEFAULT_OPTIONS_REMOTE_SF_DIRBACKED_ONLY EVENT_OPTION_MATCH0=0x00000040 +UMASK_REMOTE_SF_DIRBACKED_ONLY 0x00 + +####################################################### +# M2M == B2CMI # +####################################################### + +EVENT_M2M_CLOCKTICKS 0x01 M2M +UMASK_M2M_CLOCKTICKS 0x00 + +EVENT_B2CMI_CLOCKTICKS 0x01 M2M +UMASK_B2CMI_CLOCKTICKS 0x00 + +EVENT_IMC_READS 0x24 M2M +OPTIONS_IMC_READS EVENT_OPTION_MATCH0_MASK +DEFAULT_OPTIONS_IMC_READS_NORMAL EVENT_OPTION_MATCH0=0x00000001 +UMASK_IMC_READS_NORMAL 0x01 +DEFAULT_OPTIONS_IMC_READS_ALL EVENT_OPTION_MATCH0=0x00000001 +UMASK_IMC_READS_ALL 0x04 +DEFAULT_OPTIONS_IMC_READS_TO_DDR_AS_MEM EVENT_OPTION_MATCH0=0x00000001 +UMASK_IMC_READS_TO_DDR_AS_MEM 0x08 +DEFAULT_OPTIONS_IMC_READS_TO_DDR_AS_CACHE EVENT_OPTION_MATCH0=0x00000001 +UMASK_IMC_READS_TO_DDR_AS_CACHE 0x10 + +EVENT_IMC_WRITES 0x25 M2M +OPTIONS_IMC_WRITES EVENT_OPTION_MATCH0_MASK +DEFAULT_OPTIONS_IMC_WRITES_FULL EVENT_OPTION_MATCH0=0x00000001 +UMASK_IMC_WRITES_FULL 0x01 +DEFAULT_OPTIONS_IMC_WRITES_PARTIAL EVENT_OPTION_MATCH0=0x00000001 +UMASK_IMC_WRITES_PARTIAL 0x02 +DEFAULT_OPTIONS_IMC_WRITES_ALL EVENT_OPTION_MATCH0=0x00000001 +UMASK_IMC_WRITES_ALL 0x10 +DEFAULT_OPTIONS_IMC_WRITES_TO_DDR_AS_MEM EVENT_OPTION_MATCH0=0x00000001 +UMASK_IMC_WRITES_TO_DDR_AS_MEM 0x20 +DEFAULT_OPTIONS_IMC_WRITES_TO_DDR_AS_CACHE EVENT_OPTION_MATCH0=0x00000001 +UMASK_IMC_WRITES_TO_DDR_AS_CACHE 0x40 +DEFAULT_OPTIONS_IMC_WRITES_NI EVENT_OPTION_MATCH0=0x00000003 +UMASK_IMC_WRITES_NI 0x00 +DEFAULT_OPTIONS_IMC_WRITES_NI_MISS EVENT_OPTION_MATCH0=0x00000005 +UMASK_IMC_WRITES_NI_MISS 0x00 + +EVENT_TRACKER_INSERT 0x32 M2M +UMASK_TRACKER_INSERT_CH0 0x04 + +EVENT_TRACKER_OCCUPANCY 0x33 M2M +UMASK_TRACKER_OCCUPANCY_CH0 0x01 + +EVENT_WR_TRACKER_INSERTS 0x40 M2M +UMASK_WR_TRACKER_INSERTS_CH0 0x01 + +EVENT_TAG_MISS 0x4B M2M +UMASK_TAG_MISS_RD_CLEAN 0x01 +UMASK_TAG_MISS_RD_DIRTY 0x02 +UMASK_TAG_MISS_WR_CLEAN 0x04 +UMASK_TAG_MISS_WR_DIRTY 0x08 +UMASK_TAG_MISS_CLEAN 0x05 +UMASK_TAG_MISS_DIRTY 0x0A +UMASK_TAG_MISS_RD_2WAY 0x10 +UMASK_TAG_MISS_WR_2WAY 0x20 + +EVENT_PREFCAM_OCCUPANCY 0x54 M2M +UMASK_PREFCAM_OCCUPANCY_CH0 0x01 + +EVENT_PREFCAM_INSERTS 0x56 M2M +UMASK_PREFCAM_INSERTS_CH0_XPT 0x01 +UMASK_PREFCAM_INSERTS_XPT_ALLCH 0x01 +UMASK_PREFCAM_INSERTS_CH0_UPI 0x02 +UMASK_PREFCAM_INSERTS_UPI_ALLCH 0x02 + +EVENT_DIRECTORY_HIT 0x1D M2M +UMASK_DIRECTORY_HIT_DIRTY_I 0x01 +UMASK_DIRECTORY_HIT_DIRTY_S 0x02 +UMASK_DIRECTORY_HIT_DIRTY_A 0x04 +UMASK_DIRECTORY_HIT_DIRTY 0x07 +UMASK_DIRECTORY_HIT_CLEAN_I 0x08 +UMASK_DIRECTORY_HIT_CLEAN_S 0x10 +UMASK_DIRECTORY_HIT_CLEAN_A 0x20 +UMASK_DIRECTORY_HIT_CLEAN 0x38 + +EVENT_DIRECTORY_MISS 0x1E M2M +UMASK_DIRECTORY_MISS_DIRTY_I 0x01 +UMASK_DIRECTORY_MISS_DIRTY_S 0x02 +UMASK_DIRECTORY_MISS_DIRTY_A 0x04 +UMASK_DIRECTORY_MISS_DIRTY 0x07 +UMASK_DIRECTORY_MISS_CLEAN_I 0x08 +UMASK_DIRECTORY_MISS_CLEAN_S 0x10 +UMASK_DIRECTORY_MISS_CLEAN_A 0x20 +UMASK_DIRECTORY_MISS_CLEAN 0x38 + +EVENT_TAG_HIT 0x1F M2M +UMASK_TAG_HIT_RD_CLEAN 0x01 +UMASK_TAG_HIT_RD_DIRTY 0x02 +UMASK_TAG_HIT_WR_CLEAN 0x04 +UMASK_TAG_HIT_WR_DIRTY 0x08 +UMASK_TAG_HIT_ALL 0x0F + +EVENT_DIRECTORY_UPDATE 0x21 M2M +OPTIONS_DIRECTORY_UPDATE EVENT_OPTION_MATCH0_MASK +DEFAULT_OPTIONS_DIRECTORY_UPDATE_ANY EVENT_OPTION_MATCH0=0x00000003 +UMASK_DIRECTORY_UPDATE_ANY 0x01 +DEFAULT_OPTIONS_DIRECTORY_UPDATE_I2S EVENT_OPTION_MATCH0=0x00000003 +UMASK_DIRECTORY_UPDATE_I2S 0x02 +DEFAULT_OPTIONS_DIRECTORY_UPDATE_I2A EVENT_OPTION_MATCH0=0x00000003 +UMASK_DIRECTORY_UPDATE_I2A 0x04 +DEFAULT_OPTIONS_DIRECTORY_UPDATE_A2I EVENT_OPTION_MATCH0=0x00000003 +UMASK_DIRECTORY_UPDATE_A2I 0x20 +DEFAULT_OPTIONS_DIRECTORY_UPDATE_A2S EVENT_OPTION_MATCH0=0x00000003 +UMASK_DIRECTORY_UPDATE_A2S 0x40 +DEFAULT_OPTIONS_DIRECTORY_UPDATE_X2S EVENT_OPTION_MATCH0=0x00000003 +UMASK_DIRECTORY_UPDATE_X2S 0x42 +DEFAULT_OPTIONS_DIRECTORY_UPDATE_X2A EVENT_OPTION_MATCH0=0x00000003 +UMASK_DIRECTORY_UPDATE_X2A 0x14 +DEFAULT_OPTIONS_DIRECTORY_UPDATE_X2I EVENT_OPTION_MATCH0=0x00000003 +UMASK_DIRECTORY_UPDATE_X2I 0x28 +DEFAULT_OPTIONS_DIRECTORY_UPDATE_S2I EVENT_OPTION_MATCH0=0x00000003 +UMASK_DIRECTORY_UPDATE_S2I 0x08 +DEFAULT_OPTIONS_DIRECTORY_UPDATE_S2A EVENT_OPTION_MATCH0=0x00000003 +UMASK_DIRECTORY_UPDATE_S2A 0x10 +DEFAULT_OPTIONS_DIRECTORY_UPDATE_HIT_ANY EVENT_OPTION_MATCH0=0x00000001 +UMASK_DIRECTORY_UPDATE_HIT_ANY 0x01 +DEFAULT_OPTIONS_DIRECTORY_UPDATE_HIT_X2S EVENT_OPTION_MATCH0=0x00000001 +UMASK_DIRECTORY_UPDATE_HIT_X2S 0x42 +DEFAULT_OPTIONS_DIRECTORY_UPDATE_HIT_X2A EVENT_OPTION_MATCH0=0x00000001 +UMASK_DIRECTORY_UPDATE_HIT_X2A 0x14 +DEFAULT_OPTIONS_DIRECTORY_UPDATE_HIT_X2I EVENT_OPTION_MATCH0=0x00000001 +UMASK_DIRECTORY_UPDATE_HIT_X2I 0x28 +DEFAULT_OPTIONS_DIRECTORY_UPDATE_MISS_X2S EVENT_OPTION_MATCH0=0x00000002 +UMASK_DIRECTORY_UPDATE_MISS_X2S 0x42 +DEFAULT_OPTIONS_DIRECTORY_UPDATE_MISS_X2A EVENT_OPTION_MATCH0=0x00000002 +UMASK_DIRECTORY_UPDATE_MISS_X2A 0x14 +DEFAULT_OPTIONS_DIRECTORY_UPDATE_MISS_X2I EVENT_OPTION_MATCH0=0x00000002 +UMASK_DIRECTORY_UPDATE_MISS_X2I 0x28 + +EVENT_DIRECTORY_LOOKUP 0x20 M2M +UMASK_DIRECTORY_LOOKUP_ANY 0x01 +UMASK_DIRECTORY_LOOKUP_STATE_I 0x02 +UMASK_DIRECTORY_LOOKUP_STATE_S 0x04 +UMASK_DIRECTORY_LOOKUP_STATE_A 0x08 + +EVENT_DIRECT2UPI_NOT_TAKEN_DIRSTATE_EGRESS 0x1A M2M +UMASK_DIRECT2UPI_NOT_TAKEN_DIRSTATE_EGRESS 0x01 + +EVENT_DIRECT2UPI_NOT_TAKEN_CREDITS_EGRESS 0x1B M2M +UMASK_DIRECT2UPI_NOT_TAKEN_CREDITS_EGRESS 0x01 + +EVENT_DIRECT2CORE_TAKEN 0x16 M2M +UMASK_DIRECT2CORE_TAKEN 0x01 + +EVENT_DIRECT2CORE_NOT_TAKEN_DIRSTATE 0x17 M2M +UMASK_DIRECT2CORE_NOT_TAKEN_DIRSTATE 0x01 + +EVENT_DIRECT2CORE_TXN_OVERRIDE 0x18 M2M +UMASK_DIRECT2CORE_TXN_OVERRIDE 0x01 + +EVENT_DIRECT2UPI_TAKEN 0x19 M2M +UMASK_DIRECT2UPI_TAKEN 0x01 + +EVENT_DIRECT2UPI_NOT_TAKEN_DIRSTATE 0x1A M2M +UMASK_DIRECT2UPI_NOT_TAKEN_DIRSTATE 0x01 + +EVENT_DIRECT2UPI_NOT_TAKEN_CREDITS 0x1B M2M +UMASK_DIRECT2UPI_NOT_TAKEN_CREDITS 0x01 + +EVENT_DIRECT2UPI_TXN_OVERRIDE 0x1C M2M +UMASK_DIRECT2UPI_TXN_OVERRIDE 0x01 + +####################################################### +# IIO == IIO # +####################################################### +EVENT_IIO_CLOCKTICKS 0x01 IBOX +UMASK_IIO_CLOCKTICKS 0x00 + +EVENT_IBOX_CLOCKTICKS 0x01 IBOX +UMASK_IBOX_CLOCKTICKS 0x00 + +EVENT_IIO_DATA_REQ_OF_CPU 0x83 IBOX0C0|IBOX0C1|IBOX1C0|IBOX1C1|IBOX2C0|IBOX2C1|IBOX3C0|IBOX3C1|IBOX4C0|IBOX4C1|IBOX5C0|IBOX5C1|IBOX6C0|IBOX6C1|IBOX7C0|IBOX7C1|IBOX8C0|IBOX8C1|IBOX9C0|IBOX9C1|IBOX10C0|IBOX10C1|IBOX11C0|IBOX11C1|IBOX12C0|IBOX12C1|IBOX13C0|IBOX13C1|IBOX14C0|IBOX14C1|IBOX15C0|IBOX15C1 +OPTIONS_IIO_DATA_REQ_OF_CPU EVENT_OPTION_MATCH0_MASK +DEFAULT_OPTIONS_IIO_DATA_REQ_OF_CPU_MEM_WRITE_PART1 EVENT_OPTION_MATCH0=0x00070020 +UMASK_IIO_DATA_REQ_OF_CPU_MEM_WRITE_PART1 0x01 +DEFAULT_OPTIONS_IIO_DATA_REQ_OF_CPU_MEM_WRITE_PART2 EVENT_OPTION_MATCH0=0x00070040 +UMASK_IIO_DATA_REQ_OF_CPU_MEM_WRITE_PART2 0x01 +DEFAULT_OPTIONS_IIO_DATA_REQ_OF_CPU_MEM_WRITE_PART3 EVENT_OPTION_MATCH0=0x00070080 +UMASK_IIO_DATA_REQ_OF_CPU_MEM_WRITE_PART3 0x01 +DEFAULT_OPTIONS_IIO_DATA_REQ_OF_CPU_MEM_WRITE_PART4 EVENT_OPTION_MATCH0=0x00070100 +UMASK_IIO_DATA_REQ_OF_CPU_MEM_WRITE_PART4 0x01 +DEFAULT_OPTIONS_IIO_DATA_REQ_OF_CPU_MEM_WRITE_PART5 EVENT_OPTION_MATCH0=0x00070200 +UMASK_IIO_DATA_REQ_OF_CPU_MEM_WRITE_PART5 0x01 +DEFAULT_OPTIONS_IIO_DATA_REQ_OF_CPU_MEM_WRITE_PART6 EVENT_OPTION_MATCH0=0x00070400 +UMASK_IIO_DATA_REQ_OF_CPU_MEM_WRITE_PART6 0x01 +DEFAULT_OPTIONS_IIO_DATA_REQ_OF_CPU_MEM_WRITE_PART7 EVENT_OPTION_MATCH0=0x00070800 +UMASK_IIO_DATA_REQ_OF_CPU_MEM_WRITE_PART7 0x01 +DEFAULT_OPTIONS_IIO_DATA_REQ_OF_CPU_MEM_READ_PART1 EVENT_OPTION_MATCH0=0x00070020 +UMASK_IIO_DATA_REQ_OF_CPU_MEM_READ_PART1 0x04 +DEFAULT_OPTIONS_IIO_DATA_REQ_OF_CPU_MEM_READ_PART2 EVENT_OPTION_MATCH0=0x00070040 +UMASK_IIO_DATA_REQ_OF_CPU_MEM_READ_PART2 0x04 +DEFAULT_OPTIONS_IIO_DATA_REQ_OF_CPU_MEM_READ_PART3 EVENT_OPTION_MATCH0=0x00070080 +UMASK_IIO_DATA_REQ_OF_CPU_MEM_READ_PART3 0x04 +DEFAULT_OPTIONS_IIO_DATA_REQ_OF_CPU_MEM_READ_PART4 EVENT_OPTION_MATCH0=0x00070100 +UMASK_IIO_DATA_REQ_OF_CPU_MEM_READ_PART4 0x04 +DEFAULT_OPTIONS_IIO_DATA_REQ_OF_CPU_MEM_READ_PART5 EVENT_OPTION_MATCH0=0x00070200 +UMASK_IIO_DATA_REQ_OF_CPU_MEM_READ_PART5 0x04 +DEFAULT_OPTIONS_IIO_DATA_REQ_OF_CPU_MEM_READ_PART6 EVENT_OPTION_MATCH0=0x00070400 +UMASK_IIO_DATA_REQ_OF_CPU_MEM_READ_PART6 0x04 +DEFAULT_OPTIONS_IIO_DATA_REQ_OF_CPU_MEM_READ_PART7 EVENT_OPTION_MATCH0=0x00070800 +UMASK_IIO_DATA_REQ_OF_CPU_MEM_READ_PART7 0x04 + +EVENT_TXN_DATA_REQ_OF_CPU 0x84 IBOX0C0|IBOX0C1|IBOX1C0|IBOX1C1|IBOX2C0|IBOX2C1|IBOX3C0|IBOX3C1|IBOX4C0|IBOX4C1|IBOX5C0|IBOX5C1|IBOX6C0|IBOX6C1|IBOX7C0|IBOX7C1|IBOX8C0|IBOX8C1|IBOX9C0|IBOX9C1|IBOX10C0|IBOX10C1|IBOX11C0|IBOX11C1|IBOX12C0|IBOX12C1|IBOX13C0|IBOX13C1|IBOX14C0|IBOX14C1|IBOX15C0|IBOX15C1 +OPTIONS_TXN_DATA_REQ_OF_CPU EVENT_OPTION_MATCH0_MASK +DEFAULT_OPTIONS_TXN_DATA_REQ_OF_CPU_MEM_WRITE_PART1 EVENT_OPTION_MATCH0=0x00070020 +UMASK_TXN_DATA_REQ_OF_CPU_MEM_WRITE_PART1 0x01 +DEFAULT_OPTIONS_TXN_DATA_REQ_OF_CPU_MEM_WRITE_PART2 EVENT_OPTION_MATCH0=0x00070040 +UMASK_TXN_DATA_REQ_OF_CPU_MEM_WRITE_PART2 0x01 +DEFAULT_OPTIONS_TXN_DATA_REQ_OF_CPU_MEM_WRITE_PART3 EVENT_OPTION_MATCH0=0x00070080 +UMASK_TXN_DATA_REQ_OF_CPU_MEM_WRITE_PART3 0x01 +DEFAULT_OPTIONS_TXN_DATA_REQ_OF_CPU_MEM_WRITE_PART4 EVENT_OPTION_MATCH0=0x00070100 +UMASK_TXN_DATA_REQ_OF_CPU_MEM_WRITE_PART4 0x01 +DEFAULT_OPTIONS_TXN_DATA_REQ_OF_CPU_MEM_WRITE_PART5 EVENT_OPTION_MATCH0=0x00070200 +UMASK_TXN_DATA_REQ_OF_CPU_MEM_WRITE_PART5 0x01 +DEFAULT_OPTIONS_TXN_DATA_REQ_OF_CPU_MEM_WRITE_PART6 EVENT_OPTION_MATCH0=0x00070400 +UMASK_TXN_DATA_REQ_OF_CPU_MEM_WRITE_PART6 0x01 +DEFAULT_OPTIONS_TXN_DATA_REQ_OF_CPU_MEM_WRITE_PART7 EVENT_OPTION_MATCH0=0x00070800 +UMASK_TXN_DATA_REQ_OF_CPU_MEM_WRITE_PART7 0x01 +DEFAULT_OPTIONS_TXN_DATA_REQ_OF_CPU_MEM_READ_PART1 EVENT_OPTION_MATCH0=0x00070020 +UMASK_TXN_DATA_REQ_OF_CPU_MEM_READ_PART1 0x04 +DEFAULT_OPTIONS_TXN_DATA_REQ_OF_CPU_MEM_READ_PART2 EVENT_OPTION_MATCH0=0x00070040 +UMASK_TXN_DATA_REQ_OF_CPU_MEM_READ_PART2 0x04 +DEFAULT_OPTIONS_TXN_DATA_REQ_OF_CPU_MEM_READ_PART3 EVENT_OPTION_MATCH0=0x00070080 +UMASK_TXN_DATA_REQ_OF_CPU_MEM_READ_PART3 0x04 +DEFAULT_OPTIONS_TXN_DATA_REQ_OF_CPU_MEM_READ_PART4 EVENT_OPTION_MATCH0=0x00070100 +UMASK_TXN_DATA_REQ_OF_CPU_MEM_READ_PART4 0x04 +DEFAULT_OPTIONS_TXN_DATA_REQ_OF_CPU_MEM_READ_PART5 EVENT_OPTION_MATCH0=0x00070200 +UMASK_TXN_DATA_REQ_OF_CPU_MEM_READ_PART5 0x04 +DEFAULT_OPTIONS_TXN_DATA_REQ_OF_CPU_MEM_READ_PART6 EVENT_OPTION_MATCH0=0x00070400 +UMASK_TXN_DATA_REQ_OF_CPU_MEM_READ_PART6 0x04 +DEFAULT_OPTIONS_TXN_DATA_REQ_OF_CPU_MEM_READ_PART7 EVENT_OPTION_MATCH0=0x00070800 +UMASK_TXN_DATA_REQ_OF_CPU_MEM_READ_PART7 0x04 + + +EVENT_IIO_DATA_REQ_BY_CPU 0xC0 IBOX0C2|IBOX0C3|IBOX1C2|IBOX1C3|IBOX2C2|IBOX2C3|IBOX3C2|IBOX3C3|IBOX4C2|IBOX4C3|IBOX5C2|IBOX5C3|IBOX6C2|IBOX6C3|IBOX7C2|IBOX7C3|IBOX8C2|IBOX8C3|IBOX9C2|IBOX9C3|IBOX10C2|IBOX10C3|IBOX11C2|IBOX11C3|IBOX12C2|IBOX12C3|IBOX13C2|IBOX13C3|IBOX14C2|IBOX14C3|IBOX15C2|IBOX15C3 +OPTIONS_IIO_DATA_REQ_BY_CPU EVENT_OPTION_MATCH0_MASK +DEFAULT_OPTIONS_IIO_DATA_REQ_BY_CPU_MEM_WRITE_PART1 EVENT_OPTION_MATCH0=0x00070020 +UMASK_IIO_DATA_REQ_BY_CPU_MEM_WRITE_PART1 0x01 +DEFAULT_OPTIONS_IIO_DATA_REQ_BY_CPU_MEM_WRITE_PART2 EVENT_OPTION_MATCH0=0x00070040 +UMASK_IIO_DATA_REQ_BY_CPU_MEM_WRITE_PART2 0x01 +DEFAULT_OPTIONS_IIO_DATA_REQ_BY_CPU_MEM_WRITE_PART3 EVENT_OPTION_MATCH0=0x00070080 +UMASK_IIO_DATA_REQ_BY_CPU_MEM_WRITE_PART3 0x01 +DEFAULT_OPTIONS_IIO_DATA_REQ_BY_CPU_MEM_WRITE_PART4 EVENT_OPTION_MATCH0=0x00070100 +UMASK_IIO_DATA_REQ_BY_CPU_MEM_WRITE_PART4 0x01 +DEFAULT_OPTIONS_IIO_DATA_REQ_BY_CPU_MEM_WRITE_PART5 EVENT_OPTION_MATCH0=0x00070200 +UMASK_IIO_DATA_REQ_BY_CPU_MEM_WRITE_PART5 0x01 +DEFAULT_OPTIONS_IIO_DATA_REQ_BY_CPU_MEM_WRITE_PART6 EVENT_OPTION_MATCH0=0x00070400 +UMASK_IIO_DATA_REQ_BY_CPU_MEM_WRITE_PART6 0x01 +DEFAULT_OPTIONS_IIO_DATA_REQ_BY_CPU_MEM_WRITE_PART7 EVENT_OPTION_MATCH0=0x00070800 +UMASK_IIO_DATA_REQ_BY_CPU_MEM_WRITE_PART7 0x01 +DEFAULT_OPTIONS_IIO_DATA_REQ_BY_CPU_PEER_WRITE_ALL_PARTS EVENT_OPTION_MATCH0=0x00070FF0 +UMASK_IIO_DATA_REQ_BY_CPU_PEER_WRITE_ALL_PARTS 0x02 +DEFAULT_OPTIONS_IIO_DATA_REQ_BY_CPU_PEER_READ_ALL_PARTS EVENT_OPTION_MATCH0=0x00070FF0 +UMASK_IIO_DATA_REQ_BY_CPU_PEER_READ_ALL_PARTS 0x08 + +#DEFAULT_OPTIONS_IIO_DATA_REQ_BY_CPU_MEM_READ_PART1 EVENT_OPTION_MATCH0=0x00070020 +#UMASK_IIO_DATA_REQ_BY_CPU_MEM_READ_PART1 0x04 +#DEFAULT_OPTIONS_IIO_DATA_REQ_BY_CPU_MEM_READ_PART2 EVENT_OPTION_MATCH0=0x00070040 +#UMASK_IIO_DATA_REQ_BY_CPU_MEM_READ_PART2 0x04 +#DEFAULT_OPTIONS_IIO_DATA_REQ_BY_CPU_MEM_READ_PART3 EVENT_OPTION_MATCH0=0x00070080 +#UMASK_IIO_DATA_REQ_BY_CPU_MEM_READ_PART3 0x04 +#DEFAULT_OPTIONS_IIO_DATA_REQ_BY_CPU_MEM_READ_PART4 EVENT_OPTION_MATCH0=0x00070100 +#UMASK_IIO_DATA_REQ_BY_CPU_MEM_READ_PART4 0x04 +#DEFAULT_OPTIONS_IIO_DATA_REQ_BY_CPU_MEM_READ_PART5 EVENT_OPTION_MATCH0=0x00070200 +#UMASK_IIO_DATA_REQ_BY_CPU_MEM_READ_PART5 0x04 +#DEFAULT_OPTIONS_IIO_DATA_REQ_BY_CPU_MEM_READ_PART6 EVENT_OPTION_MATCH0=0x00070400 +#UMASK_IIO_DATA_REQ_BY_CPU_MEM_READ_PART6 0x04 +#DEFAULT_OPTIONS_IIO_DATA_REQ_BY_CPU_MEM_READ_PART7 EVENT_OPTION_MATCH0=0x00070800 +#UMASK_IIO_DATA_REQ_BY_CPU_MEM_READ_PART7 0x04 + + +EVENT_TXN_DATA_REQ_BY_CPU 0xC1 IBOX0C2|IBOX0C3|IBOX1C2|IBOX1C3|IBOX2C2|IBOX2C3|IBOX3C2|IBOX3C3|IBOX4C2|IBOX4C3|IBOX5C2|IBOX5C3|IBOX6C2|IBOX6C3|IBOX7C2|IBOX7C3|IBOX8C2|IBOX8C3|IBOX9C2|IBOX9C3|IBOX10C2|IBOX10C3|IBOX11C2|IBOX11C3|IBOX12C2|IBOX12C3|IBOX13C2|IBOX13C3|IBOX14C2|IBOX14C3|IBOX15C2|IBOX15C3 +OPTIONS_TXN_DATA_REQ_BY_CPU EVENT_OPTION_MATCH0_MASK +DEFAULT_OPTIONS_TXN_DATA_REQ_BY_CPU_MEM_WRITE_PART1 EVENT_OPTION_MATCH0=0x00070020 +UMASK_TXN_DATA_REQ_BY_CPU_MEM_WRITE_PART1 0x01 +DEFAULT_OPTIONS_TXN_DATA_REQ_BY_CPU_MEM_WRITE_PART2 EVENT_OPTION_MATCH0=0x00070040 +UMASK_TXN_DATA_REQ_BY_CPU_MEM_WRITE_PART2 0x01 +DEFAULT_OPTIONS_TXN_DATA_REQ_BY_CPU_MEM_WRITE_PART3 EVENT_OPTION_MATCH0=0x00070080 +UMASK_TXN_DATA_REQ_BY_CPU_MEM_WRITE_PART3 0x01 +DEFAULT_OPTIONS_TXN_DATA_REQ_BY_CPU_MEM_WRITE_PART4 EVENT_OPTION_MATCH0=0x00070100 +UMASK_TXN_DATA_REQ_BY_CPU_MEM_WRITE_PART4 0x01 +DEFAULT_OPTIONS_TXN_DATA_REQ_BY_CPU_MEM_WRITE_PART5 EVENT_OPTION_MATCH0=0x00070200 +UMASK_TXN_DATA_REQ_BY_CPU_MEM_WRITE_PART5 0x01 +DEFAULT_OPTIONS_TXN_DATA_REQ_BY_CPU_MEM_WRITE_PART6 EVENT_OPTION_MATCH0=0x00070400 +UMASK_TXN_DATA_REQ_BY_CPU_MEM_WRITE_PART6 0x01 +DEFAULT_OPTIONS_TXN_DATA_REQ_BY_CPU_MEM_WRITE_PART7 EVENT_OPTION_MATCH0=0x00070800 +UMASK_TXN_DATA_REQ_BY_CPU_MEM_WRITE_PART7 0x01 +DEFAULT_OPTIONS_TXN_DATA_REQ_BY_CPU_MEM_WRITE_ALL_PARTS EVENT_OPTION_MATCH0=0x00070FF0 +UMASK_TXN_DATA_REQ_BY_CPU_MEM_WRITE_ALL_PARTS 0x01 +DEFAULT_OPTIONS_TXN_DATA_REQ_BY_CPU_PEER_WRITE_ALL_PARTS EVENT_OPTION_MATCH0=0x00070FF0 +UMASK_TXN_DATA_REQ_BY_CPU_PEER_WRITE_ALL_PARTS 0x02 +DEFAULT_OPTIONS_TXN_DATA_REQ_BY_CPU_MEM_READ_PART1 EVENT_OPTION_MATCH0=0x00070020 +UMASK_TXN_DATA_REQ_BY_CPU_MEM_READ_PART1 0x04 +DEFAULT_OPTIONS_TXN_DATA_REQ_BY_CPU_MEM_READ_PART2 EVENT_OPTION_MATCH0=0x00070040 +UMASK_TXN_DATA_REQ_BY_CPU_MEM_READ_PART2 0x04 +DEFAULT_OPTIONS_TXN_DATA_REQ_BY_CPU_MEM_READ_PART3 EVENT_OPTION_MATCH0=0x00070080 +UMASK_TXN_DATA_REQ_BY_CPU_MEM_READ_PART3 0x04 +DEFAULT_OPTIONS_TXN_DATA_REQ_BY_CPU_MEM_READ_PART4 EVENT_OPTION_MATCH0=0x00070100 +UMASK_TXN_DATA_REQ_BY_CPU_MEM_READ_PART4 0x04 +DEFAULT_OPTIONS_TXN_DATA_REQ_BY_CPU_MEM_READ_PART5 EVENT_OPTION_MATCH0=0x00070200 +UMASK_TXN_DATA_REQ_BY_CPU_MEM_READ_PART5 0x04 +DEFAULT_OPTIONS_TXN_DATA_REQ_BY_CPU_MEM_READ_PART6 EVENT_OPTION_MATCH0=0x00070400 +UMASK_TXN_DATA_REQ_BY_CPU_MEM_READ_PART6 0x04 +DEFAULT_OPTIONS_TXN_DATA_REQ_BY_CPU_MEM_READ_PART7 EVENT_OPTION_MATCH0=0x00070800 +UMASK_TXN_DATA_REQ_BY_CPU_MEM_READ_PART7 0x04 +DEFAULT_OPTIONS_TXN_DATA_REQ_BY_CPU_MEM_READ_ALL_PARTS EVENT_OPTION_MATCH0=0x00070FF0 +UMASK_TXN_DATA_REQ_BY_CPU_MEM_READ_ALL_PARTS 0x04 +DEFAULT_OPTIONS_TXN_DATA_REQ_BY_CPU_PEER_READ_ALL_PARTS EVENT_OPTION_MATCH0=0x00070FF0 +UMASK_TXN_DATA_REQ_BY_CPU_PEER_READ_ALL_PARTS 0x08 + +####################################################### +# IRP == IRP # +####################################################### +EVENT_IRP_CLOCKTICKS 0x01 IRP +UMASK_IRP_CLOCKTICKS 0x00 + +EVENT_TRANSACTIONS 0x11 IRP +UMASK_TRANSACTIONS_WR_PRE 0x08 + +EVENT_FAF_INSERT 0x18 IRP +UMASK_FAF_INSERT 0x00 + +EVENT_CACHE_TOTAL_OCCUPANCY 0x0F IRP +UMASK_CACHE_TOTAL_OCCUPANCY_MEM 0x04 + +EVENT_FAF_OCCUPANCY 0x19 IRP +UMASK_FAF_OCCUPANCY 0x00 + +EVENT_MISC1 0x1F IRP +UMASK_MISC1_LOST_FWD 0x10 + +####################################################### +# PBOX == B2CXL # +####################################################### + +EVENT_PBOX_CLOCKTICKS 0x01 PBOX +UMASK_PBOX_CLOCKTICKS 0x00 + +EVENT_B2CXL_CLOCKTICKS 0x01 PBOX +UMASK_B2CXL_CLOCKTICKS 0x00 + +####################################################### +# RBOX == B2UPI # +####################################################### + +EVENT_RBOX_CLOCKTICKS 0x01 RBOX +UMASK_RBOX_CLOCKTICKS 0x00 + +EVENT_B2UPI_CLOCKTICKS 0x01 RBOX +UMASK_B2UPI_CLOCKTICKS 0x00 + +####################################################### +# PCU == PCU # +####################################################### + +EVENT_PCU_CLOCKTICKS 0x01 PCU +UMASK_PCU_CLOCKTICKS 0x00 + +EVENT_POWER_STATE_OCCUPANCY_CORES_C0 0x35 PCU +UMASK_POWER_STATE_OCCUPANCY_CORES_C0 0x00 + +EVENT_POWER_STATE_OCCUPANCY_CORES_C6 0x37 PCU +UMASK_POWER_STATE_OCCUPANCY_CORES_C6 0x00 + +EVENT_FREQ_MAX_LIMIT_THERMAL_CYCLES 0x04 PCU +UMASK_FREQ_MAX_LIMIT_THERMAL_CYCLES 0x00 + +EVENT_FREQ_MAX_POWER_CYCLES 0x05 PCU +UMASK_FREQ_MAX_POWER_CYCLES 0x00 + +EVENT_FREQ_TRANS_CYCLES 0x74 PCU +UMASK_FREQ_TRANS_CYCLES 0x00 + +EVENT_PKG_RESIDENCY_C2E_CYCLES 0x2B PCU +UMASK_PKG_RESIDENCY_C2E_CYCLES 0x00 + +EVENT_PKG_RESIDENCY_C6_CYCLES 0x2D PCU +UMASK_PKG_RESIDENCY_C6_CYCLES 0x00 + +EVENT_POWER_STATE_OCCUPANCY_CORES_C3 0x36 PCU +UMASK_POWER_STATE_OCCUPANCY_CORES_C3 0x00 + +EVENT_PROCHOT_EXTERNAL_CYCLES 0x0A PCU +UMASK_PROCHOT_EXTERNAL_CYCLES 0x00 + +EVENT_PROCHOT_INTERNAL_CYCLES 0x09 PCU +UMASK_PROCHOT_INTERNAL_CYCLES 0x00 diff --git a/src/includes/perfmon_sapphirerapids_counters.h b/src/includes/perfmon_sapphirerapids_counters.h index fd4750084..ec752e6a4 100644 --- a/src/includes/perfmon_sapphirerapids_counters.h +++ b/src/includes/perfmon_sapphirerapids_counters.h @@ -1942,3 +1942,30 @@ static char* registerTypeNamesSapphireRapids[MAX_UNITS] = { }; +#define SPR_DEVICE_ID_CHA 0 +#define SPR_DEVICE_ID_IIO 1 +#define SPR_DEVICE_ID_IRP 2 +#define SPR_DEVICE_ID_M2PCIe 3 +#define SPR_DEVICE_ID_PCU 4 +#define SPR_DEVICE_ID_iMC 6 +#define SPR_DEVICE_ID_M2M 7 +#define SPR_DEVICE_ID_UPI 8 +#define SPR_DEVICE_ID_M3UPI 9 +#define SPR_DEVICE_ID_MDF 11 +#define SPR_DEVICE_ID_HBM 14 + +static PerfmonUncoreDiscovery sapphirerapids_uncore_discovery_map[] = { + {"CBOX", SPR_DEVICE_ID_CHA, 60, MSR_CBOX_DEVICE_C0}, + {"MBOX", SPR_DEVICE_ID_iMC, 15, MMIO_IMC_DEVICE_0_CH_0}, + {"PBOX", SPR_DEVICE_ID_M2PCIe, 15, PCI_R2PCIE_DEVICE0}, + {"WBOX", SPR_DEVICE_ID_PCU, 1, MSR_PCU_DEVICE}, + {"IRP", SPR_DEVICE_ID_IRP, 12, MSR_IRP_DEVICE_0}, + {"IIO", SPR_DEVICE_ID_IIO, 12, MSR_IIO_DEVICE_0}, + {"QBOX", SPR_DEVICE_ID_UPI, 3, PCI_QPI_DEVICE_PORT_0}, + {"MDF", SPR_DEVICE_ID_MDF, 49, MSR_MDF_DEVICE_0}, + {"M2M", SPR_DEVICE_ID_M2M, 31, MMIO_HBM_DEVICE_0}, + {"RBOX", SPR_DEVICE_ID_M3UPI, 3, PCI_R3QPI_DEVICE_LINK_0}, + {"HBM", SPR_DEVICE_ID_HBM, 31, MMIO_HBM_DEVICE_0}, + {"INVALID", -1, 0, MSR_DEV} +}; + diff --git a/src/includes/perfmon_sierraforrest.h b/src/includes/perfmon_sierraforrest.h new file mode 100644 index 000000000..156e34356 --- /dev/null +++ b/src/includes/perfmon_sierraforrest.h @@ -0,0 +1,559 @@ +/* + * ======================================================================================= + * + * Filename: perfmon_sierraforrest.h + * + * Description: Header File of perfmon module for Intel SierraForrest. + * + * Version: + * Released: + * + * Author: Thomas Gruber (tr), thomas.roehl@googlemail.com + * Project: likwid + * + * Copyright (C) 2015 RRZE, University Erlangen-Nuremberg + * + * This program is free software: you can redistribute it and/or modify it under + * the terms of the GNU General Public License as published by the Free Software + * Foundation, either version 3 of the License, or (at your option) any later + * version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT ANY + * WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A + * PARTICULAR PURPOSE. See the GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + * + * ======================================================================================= + */ + + +#include +#include + + +static int perfmon_numCountersSierraForrest = NUM_COUNTERS_SIERRAFORREST; +static int perfmon_numCoreCountersSierraForrest = NUM_COUNTERS_CORE_SIERRAFORREST; +static int perfmon_numArchEventsSierraForrest = NUM_ARCH_EVENTS_SIERRAFORREST; + +int perfmon_init_sierraforrest(int cpu_id) +{ + int ret = 0; + lock_acquire((int*) &tile_lock[affinity_thread2core_lookup[cpu_id]], cpu_id); + lock_acquire((int*) &socket_lock[affinity_thread2socket_lookup[cpu_id]], cpu_id); + lock_acquire((int*) &die_lock[affinity_thread2die_lookup[cpu_id]], cpu_id); + +/* uint64_t misc_enable = 0x0;*/ +/* ret = HPMread(cpu_id, MSR_DEV, MSR_IA32_MISC_ENABLE, &misc_enable);*/ +/* if (ret == 0 && (testBit(misc_enable, 7) == 1) && (testBit(misc_enable, 12) == 0))*/ +/* {*/ +/* ret = HPMwrite(cpu_id, MSR_DEV, MSR_PEBS_ENABLE, 0x0ULL);*/ +/* if (ret != 0)*/ +/* {*/ +/* ERROR_PRINT(Cannot zero %s (0x%X), str(MSR_PEBS_ENABLE), MSR_PEBS_ENABLE);*/ +/* }*/ +/* ret = HPMwrite(cpu_id, MSR_DEV, MSR_PEBS_FRONTEND, 0x0ULL);*/ +/* if (ret != 0)*/ +/* {*/ +/* ERROR_PRINT(Cannot zero %s (0x%X), str(MSR_PEBS_FRONTEND), MSR_PEBS_FRONTEND);*/ +/* }*/ +/* }*/ + return 0; +} + +uint64_t srf_fixed_setup(int thread_id, RegisterIndex index, PerfmonEvent *event, PerfmonCounter* data) +{ + return spr_fixed_setup(thread_id, index, event, data); +} + +uint64_t srf_fixed_start(int thread_id, RegisterIndex index, PerfmonEvent *event, PerfmonCounter* data) +{ + return spr_fixed_start(thread_id, index, event, data); +} + +uint64_t srf_pmc_setup(int thread_id, RegisterIndex index, PerfmonEvent *event, PerfmonCounter* data) +{ + return spr_pmc_setup(thread_id, index, event, data); +} + +uint64_t srf_pmc_start(int thread_id, RegisterIndex index, PerfmonEvent* event, PerfmonCounter* data) +{ + return spr_pmc_start(thread_id, index, event, data); +} + +uint64_t srf_power_start(int thread_id, RegisterIndex index, PerfmonEvent* event, PerfmonCounter* data) +{ + return spr_power_start(thread_id, index, event, data); +} + +uint64_t srf_metrics_start(int thread_id, RegisterIndex index, PerfmonEvent* event, PerfmonCounter* data) +{ + return spr_metrics_start(thread_id, index, event, data); +} + +uint64_t srf_fixed_stop(int thread_id, RegisterIndex index, PerfmonEvent* event, PerfmonCounter* data) +{ + return spr_fixed_stop(thread_id, index, event, data); +} + +uint64_t srf_pmc_stop(int thread_id, RegisterIndex index, PerfmonEvent* event, PerfmonCounter* data) +{ + return spr_pmc_stop(thread_id, index, event, data); +} + +uint64_t srf_power_stop(int thread_id, RegisterIndex index, PerfmonEvent* event, PerfmonCounter* data) +{ + return spr_power_stop(thread_id, index, event, data); +} + +uint64_t srf_thermal_stop(int thread_id, RegisterIndex index, PerfmonEvent* event, PerfmonCounter* data) +{ + return spr_thermal_stop(thread_id, index, event, data); +} + +uint64_t srf_voltage_stop(int thread_id, RegisterIndex index, PerfmonEvent* event, PerfmonCounter* data) +{ + return spr_voltage_stop(thread_id, index, event, data); +} + +uint64_t srf_metrics_stop(int thread_id, RegisterIndex index, PerfmonEvent* event, PerfmonCounter* data) +{ + return spr_metrics_stop(thread_id, index, event, data); +} + +uint64_t srf_fixed_read(int thread_id, RegisterIndex index, PerfmonEvent* event, PerfmonCounter* data) +{ + return spr_fixed_read(thread_id, index, event, data); +} + +uint64_t srf_pmc_read(int thread_id, RegisterIndex index, PerfmonEvent* event, PerfmonCounter* data) +{ + return spr_pmc_read(thread_id, index, event, data); +} + +uint64_t srf_power_read(int thread_id, RegisterIndex index, PerfmonEvent* event, PerfmonCounter* data) +{ + return spr_power_read(thread_id, index, event, data); +} + +uint64_t srf_thermal_read(int thread_id, RegisterIndex index, PerfmonEvent* event, PerfmonCounter* data) +{ + return spr_thermal_read(thread_id, index, event, data); +} + +uint64_t srf_voltage_read(int thread_id, RegisterIndex index, PerfmonEvent* event, PerfmonCounter* data) +{ + return spr_voltage_read(thread_id, index, event, data); +} + +uint64_t srf_metrics_read(int thread_id, RegisterIndex index, PerfmonEvent* event, PerfmonCounter* data) +{ + return spr_metrics_read(thread_id, index, event, data); +} + + +static PerfmonFuncs SrfUnitFuncs[NUM_UNITS] = { + [PMC] = {srf_pmc_setup, srf_pmc_start, srf_pmc_stop, srf_pmc_read, 0}, + [FIXED] = {srf_fixed_setup, srf_fixed_start, srf_fixed_stop, srf_fixed_read, 0}, + [POWER] = {NULL, srf_power_start, srf_power_stop, srf_power_read, PERFMON_LOCK_SOCKET}, + [THERMAL] = {NULL, NULL, srf_thermal_stop, srf_thermal_read, 0}, + [VOLTAGE] = {NULL, NULL, srf_voltage_stop, srf_voltage_read, 0}, + [METRICS] = {NULL, srf_metrics_start, srf_metrics_stop, srf_metrics_read, 0}, +}; + +int perfmon_setupCounterThread_sierraforrest( + int thread_id, + PerfmonEventSet* eventSet) +{ + int err = 0; + int haveLock = 0; + uint64_t fixed_flags = 0x0ULL; + int cpu_id = groupSet->threads[thread_id].processorId; + + if (socket_lock[affinity_thread2socket_lookup[cpu_id]] == cpu_id) + { + haveLock = 1; + } + + if (MEASURE_CORE(eventSet)) + { + VERBOSEPRINTREG(cpu_id, MSR_PERF_GLOBAL_CTRL, 0x0ULL, FREEZE_PMC_AND_FIXED) + CHECK_MSR_WRITE_ERROR(HPMwrite(cpu_id, MSR_DEV, MSR_PERF_GLOBAL_CTRL, 0x0ULL)); + CHECK_MSR_WRITE_ERROR(HPMwrite(cpu_id, MSR_DEV, MSR_PERF_GLOBAL_OVF_CTRL, 0xC00000070000000F)); + } + if (haveLock && MEASURE_UNCORE(eventSet)) + { + VERBOSEPRINTPCIREG(cpu_id, MSR_UBOX_DEVICE, FAKE_UNC_GLOBAL_CTRL, LLU_CAST (1ULL<<0), FREEZE_UNCORE); + HPMwrite(cpu_id, MSR_UBOX_DEVICE, FAKE_UNC_GLOBAL_CTRL, (1ULL<<0)); + } + for (int i=0;i < eventSet->numberOfEvents;i++) + { + RegisterType type = eventSet->events[i].type; + if (!TESTTYPE(eventSet, type)) + { + continue; + } + RegisterIndex index = eventSet->events[i].index; + PerfmonEvent *event = &(eventSet->events[i].event); + PerfmonCounter* data = eventSet->events[i].threadCounter; + uint64_t reg = counter_map[index].configRegister; + eventSet->events[i].threadCounter[thread_id].init = TRUE; + + PerfmonFuncs *unitFuncs = &SrfUnitFuncs[type]; + if (unitFuncs && unitFuncs->setup != NULL) + { + haveLock = 0; + switch (unitFuncs->requiresLock) + { + case PERFMON_LOCK_HWTHREAD: + haveLock = 1; + break; + case PERFMON_LOCK_SOCKET: + haveLock = (socket_lock[affinity_thread2socket_lookup[cpu_id]] == cpu_id); + break; + } + if (haveLock) + { + uint64_t ret = unitFuncs->setup(thread_id, index, event, data); + if (type == FIXED) + { + fixed_flags |= ret; + } + } + } + } + if ((fixed_flags > 0x0ULL)) + { + VERBOSEPRINTREG(cpu_id, MSR_PERF_FIXED_CTR_CTRL, LLU_CAST fixed_flags, SETUP_FIXED) + CHECK_MSR_WRITE_ERROR(HPMwrite(cpu_id, MSR_DEV, MSR_PERF_FIXED_CTR_CTRL, fixed_flags)); + } + return 0; +} + +int perfmon_startCountersThread_sierraforrest(int thread_id, PerfmonEventSet* eventSet) +{ + int haveLock = 0; + uint64_t flags = 0x0ULL; + uint64_t uflags = 0x0ULL; + uint64_t tmp = 0x0ULL; + int cpu_id = groupSet->threads[thread_id].processorId; + + if (socket_lock[affinity_thread2socket_lookup[cpu_id]] == cpu_id) + { + haveLock = 1; + } + + for (int i=0;i < eventSet->numberOfEvents;i++) + { + if (eventSet->events[i].threadCounter[thread_id].init == TRUE) + { + RegisterType type = eventSet->events[i].type; + if (!TESTTYPE(eventSet, type)) + { + continue; + } + tmp = 0x0ULL; + RegisterIndex index = eventSet->events[i].index; + PerfmonEvent *event = &(eventSet->events[i].event); + PerfmonCounter* data = eventSet->events[i].threadCounter; + uint64_t counter1 = counter_map[index].counterRegister; + + PciDeviceIndex dev = counter_map[index].device; + data[thread_id].startData = 0; + data[thread_id].counterData = 0; + + PerfmonFuncs *unitFuncs = &SrfUnitFuncs[type]; + if (unitFuncs && unitFuncs->start != NULL) + { + haveLock = 0; + switch (unitFuncs->requiresLock) + { + case PERFMON_LOCK_HWTHREAD: + haveLock = 1; + break; + case PERFMON_LOCK_SOCKET: + haveLock = (socket_lock[affinity_thread2socket_lookup[cpu_id]] == cpu_id); + break; + } + if (haveLock) + { + uint64_t ret = unitFuncs->start(thread_id, index, event, data); + if (type == FIXED || type == PMC) + { + flags |= ret; + } + } + } + data[thread_id].counterData = data[thread_id].startData; + } + } + if (haveLock && MEASURE_UNCORE(eventSet)) + { + for (int i = MSR_DEV + 1; i < MAX_NUM_PCI_DEVICES; i++) + { + if (TESTTYPE(eventSet, i) && box_map[i].device != MSR_DEV) + { + VERBOSEPRINTPCIREG(cpu_id, box_map[i].device, box_map[i].ctrlRegister, LLU_CAST 0x0ULL, UNFREEZE_UNIT); + HPMwrite(cpu_id, box_map[i].device, box_map[i].ctrlRegister, 0x0ULL); + } + } + VERBOSEPRINTPCIREG(cpu_id, MSR_UBOX_DEVICE, FAKE_UNC_GLOBAL_CTRL, LLU_CAST 0x0ULL, UNFREEZE_UNCORE); + HPMwrite(cpu_id, MSR_UBOX_DEVICE, FAKE_UNC_GLOBAL_CTRL, 0x0ULL); + } + if (MEASURE_CORE(eventSet)) + { + if (flags & (1ULL << 48)) + { + VERBOSEPRINTREG(cpu_id, MSR_PERF_METRICS, 0x0ULL, CLEAR_METRICS) + CHECK_MSR_WRITE_ERROR(HPMwrite(cpu_id, MSR_DEV, MSR_PERF_METRICS, 0x0ULL)); + } + VERBOSEPRINTREG(cpu_id, MSR_PERF_GLOBAL_OVF_CTRL, LLU_CAST (1ULL<<63)|(1ULL<<62)|flags, CLEAR_PMC_AND_FIXED_OVERFLOW) + CHECK_MSR_WRITE_ERROR(HPMwrite(cpu_id, MSR_DEV, MSR_PERF_GLOBAL_OVF_CTRL, (1ULL<<63)|(1ULL<<62)|flags)); + VERBOSEPRINTREG(cpu_id, MSR_PERF_GLOBAL_CTRL, LLU_CAST flags, UNFREEZE_PMC_AND_FIXED) + CHECK_MSR_WRITE_ERROR(HPMwrite(cpu_id, MSR_DEV, MSR_PERF_GLOBAL_CTRL, flags)); + } + return 0; +} + + +int perfmon_stopCountersThread_sierraforrest(int thread_id, PerfmonEventSet* eventSet) +{ + int haveLock = 0; + int coffset = 0; + uint64_t counter_result = 0x0ULL; + uint64_t tmp = 0x0ULL; + int cpu_id = groupSet->threads[thread_id].processorId; + + if (socket_lock[affinity_thread2socket_lookup[cpu_id]] == cpu_id) + { + haveLock = 1; + } + + if (MEASURE_CORE(eventSet)) + { + VERBOSEPRINTREG(cpu_id, MSR_PERF_GLOBAL_CTRL, 0x0ULL, FREEZE_PMC_AND_FIXED) + CHECK_MSR_WRITE_ERROR(HPMwrite(cpu_id, MSR_DEV, MSR_PERF_GLOBAL_CTRL, 0x0ULL)); + } + if (haveLock && MEASURE_UNCORE(eventSet)) + { + for (int i = MSR_DEV + 1; i < MAX_NUM_PCI_DEVICES; i++) + { + if (TESTTYPE(eventSet, i) && box_map[i].device != MSR_DEV) + { + VERBOSEPRINTPCIREG(cpu_id, box_map[i].device, box_map[i].ctrlRegister, LLU_CAST (1ULL<<0), FREEZE_UNIT); + HPMwrite(cpu_id, box_map[i].device, box_map[i].ctrlRegister, (1ULL<<0)); + } + } + VERBOSEPRINTPCIREG(cpu_id, MSR_UBOX_DEVICE, FAKE_UNC_GLOBAL_CTRL, LLU_CAST (1ULL<<0), FREEZE_UNCORE); + HPMwrite(cpu_id, MSR_UBOX_DEVICE, FAKE_UNC_GLOBAL_CTRL, (1ULL<<0)); + } + + for (int i=0;i < eventSet->numberOfEvents;i++) + { + if (eventSet->events[i].threadCounter[thread_id].init == TRUE) + { + RegisterType type = eventSet->events[i].type; + if (!TESTTYPE(eventSet, type)) + { + continue; + } + tmp = 0x0ULL; + counter_result = 0x0ULL; + RegisterIndex index = eventSet->events[i].index; + PerfmonEvent *event = &(eventSet->events[i].event); + PciDeviceIndex dev = counter_map[index].device; + PerfmonCounter* data = eventSet->events[i].threadCounter; + + uint64_t counter1 = counter_map[index].counterRegister; + uint64_t* current = &(eventSet->events[i].threadCounter[thread_id].counterData); + int* overflows = &(eventSet->events[i].threadCounter[thread_id].overflows); + int ovf_offset = box_map[type].ovflOffset; + PerfmonFuncs *unitFuncs = &SrfUnitFuncs[type]; + if (unitFuncs && unitFuncs->stop != NULL) + { + haveLock = 0; + switch (unitFuncs->requiresLock) + { + case PERFMON_LOCK_HWTHREAD: + haveLock = 1; + break; + case PERFMON_LOCK_SOCKET: + haveLock = (socket_lock[affinity_thread2socket_lookup[cpu_id]] == cpu_id); + break; + } + if (haveLock) + { + unitFuncs->stop(thread_id, index, event, data); + } + } + } + } + return 0; +} + + + +int perfmon_readCountersThread_sierraforrest(int thread_id, PerfmonEventSet* eventSet) +{ + int haveLock = 0; + int coffset = 0; + uint64_t flags = 0x0ULL; + uint64_t counter_result = 0x0ULL; + uint64_t tmp = 0x0ULL; + int cpu_id = groupSet->threads[thread_id].processorId; + + if (socket_lock[affinity_thread2socket_lookup[cpu_id]] == cpu_id) + { + haveLock = 1; + } + + if (MEASURE_CORE(eventSet)) + { + CHECK_MSR_READ_ERROR(HPMread(cpu_id, MSR_DEV, MSR_PERF_GLOBAL_CTRL, &flags)); + VERBOSEPRINTREG(cpu_id, MSR_PERF_GLOBAL_CTRL, LLU_CAST flags, SAFE_PMC_FLAGS) + CHECK_MSR_WRITE_ERROR(HPMwrite(cpu_id, MSR_DEV, MSR_PERF_GLOBAL_CTRL, 0x0ULL)); + VERBOSEPRINTREG(cpu_id, MSR_PERF_GLOBAL_CTRL, 0x0ULL, RESET_PMC_FLAGS) + } + if (haveLock && MEASURE_UNCORE(eventSet)) + { + for (int i = MSR_DEV + 1; i < MAX_NUM_PCI_DEVICES; i++) + { + if (TESTTYPE(eventSet, i) && box_map[i].device != MSR_DEV) + { + VERBOSEPRINTPCIREG(cpu_id, box_map[i].device, box_map[i].ctrlRegister, LLU_CAST (1ULL<<0), FREEZE_UNIT); + HPMwrite(cpu_id, box_map[i].device, box_map[i].ctrlRegister, (1ULL<<0)); + } + } + VERBOSEPRINTPCIREG(cpu_id, MSR_UBOX_DEVICE, FAKE_UNC_GLOBAL_CTRL, LLU_CAST (1ULL<<0), FREEZE_UNCORE); + HPMwrite(cpu_id, MSR_UBOX_DEVICE, FAKE_UNC_GLOBAL_CTRL, (1ULL<<0)); + } + for (int i=0;i < eventSet->numberOfEvents;i++) + { + if (eventSet->events[i].threadCounter[thread_id].init == TRUE) + { + RegisterType type = eventSet->events[i].type; + if (!TESTTYPE(eventSet, type)) + { + continue; + } + tmp = 0x0ULL; + counter_result = 0x0ULL; + RegisterIndex index = eventSet->events[i].index; + PerfmonEvent *event = &(eventSet->events[i].event); + PciDeviceIndex dev = counter_map[index].device; + PerfmonCounter* data = eventSet->events[i].threadCounter; + + uint64_t counter1 = counter_map[index].counterRegister; + uint64_t* current = &(eventSet->events[i].threadCounter[thread_id].counterData); + int* overflows = &(eventSet->events[i].threadCounter[thread_id].overflows); + int ovf_offset = box_map[type].ovflOffset; + PerfmonFuncs *unitFuncs = &SrfUnitFuncs[type]; + if (unitFuncs && unitFuncs->read != NULL) + { + haveLock = 0; + switch (unitFuncs->requiresLock) + { + case PERFMON_LOCK_HWTHREAD: + haveLock = 1; + break; + case PERFMON_LOCK_SOCKET: + haveLock = (socket_lock[affinity_thread2socket_lookup[cpu_id]] == cpu_id); + break; + } + if (haveLock) + { + unitFuncs->read(thread_id, index, event, data); + } + } + } + } + if (haveLock && MEASURE_UNCORE(eventSet)) + { + for (int i = MSR_DEV + 1; i < MAX_NUM_PCI_DEVICES; i++) + { + if (TESTTYPE(eventSet, i) && box_map[i].device != MSR_DEV) + { + VERBOSEPRINTPCIREG(cpu_id, box_map[i].device, box_map[i].ctrlRegister, LLU_CAST 0x0ULL, UNFREEZE_UNIT); + HPMwrite(cpu_id, box_map[i].device, box_map[i].ctrlRegister, 0x0ULL); + } + } + VERBOSEPRINTPCIREG(cpu_id, MSR_UBOX_DEVICE, FAKE_UNC_GLOBAL_CTRL, LLU_CAST 0x0ULL, UNFREEZE_UNCORE); + CHECK_MSR_WRITE_ERROR(HPMwrite(cpu_id, MSR_UBOX_DEVICE, FAKE_UNC_GLOBAL_CTRL, 0x0ULL)); + } + if (MEASURE_CORE(eventSet)) + { + VERBOSEPRINTREG(cpu_id, MSR_PERF_GLOBAL_CTRL, LLU_CAST flags, RESTORE_PMC_FLAGS) + CHECK_MSR_WRITE_ERROR(HPMwrite(cpu_id, MSR_DEV, MSR_PERF_GLOBAL_CTRL, flags)); + } + return 0; +} + + + + +int perfmon_finalizeCountersThread_sierraforrest(int thread_id, PerfmonEventSet* eventSet) +{ + int haveLock = 0; + int haveTileLock = 0; + int clearPBS = 0; + uint64_t ovf_values_core = (1ULL<<63)|(1ULL<<62); + uint64_t ovf_values_uncore = 0x0ULL; + int cpu_id = groupSet->threads[thread_id].processorId; + + if (socket_lock[affinity_thread2socket_lookup[cpu_id]] == cpu_id) + { + haveLock = 1; + } + if (tile_lock[affinity_thread2core_lookup[cpu_id]] == cpu_id) + { + haveTileLock = 1; + } + for (int i=0;i < eventSet->numberOfEvents;i++) + { + RegisterType type = eventSet->events[i].type; + if (!TESTTYPE(eventSet, type)) + { + continue; + } + RegisterIndex index = eventSet->events[i].index; + PciDeviceIndex dev = counter_map[index].device; + uint64_t reg = counter_map[index].configRegister; + switch (type) + { + case FIXED: + ovf_values_core |= (1ULL<<(index+32)); + break; + default: + break; + } + if ((reg) && (((type == PMC)||(type == FIXED))||(type == METRICS)|| ((type >= UNCORE && type < NUM_UNITS) && (haveLock)))) + { + CHECK_MSR_READ_ERROR(HPMread(cpu_id, dev, reg, &ovf_values_uncore)); + VERBOSEPRINTPCIREG(cpu_id, dev, reg, ovf_values_uncore, SHOW_CTL); + ovf_values_uncore = 0x0ULL; + VERBOSEPRINTPCIREG(cpu_id, dev, reg, 0x0ULL, CLEAR_CTL); + CHECK_MSR_WRITE_ERROR(HPMwrite(cpu_id, dev, reg, 0x0ULL)); + if ((type >= SBOX0) && (type <= SBOX3)) + { + CHECK_MSR_WRITE_ERROR(HPMwrite(cpu_id, dev, reg, 0x0ULL)); + } + VERBOSEPRINTPCIREG(cpu_id, dev, counter_map[index].counterRegister, 0x0ULL, CLEAR_CTR); + CHECK_MSR_WRITE_ERROR(HPMwrite(cpu_id, dev, counter_map[index].counterRegister, 0x0ULL)); + if (box_map[type].filterRegister1 != 0x0) + { + VERBOSEPRINTPCIREG(cpu_id, dev, box_map[type].filterRegister1, 0x0ULL, CLEAR_FILTER); + CHECK_MSR_WRITE_ERROR(HPMwrite(cpu_id, dev, box_map[type].filterRegister1, 0x0ULL)); + } + } + eventSet->events[i].threadCounter[thread_id].init = FALSE; + } + if (MEASURE_CORE(eventSet)) + { + VERBOSEPRINTREG(cpu_id, MSR_PERF_GLOBAL_OVF_CTRL, LLU_CAST ovf_values_core, CLEAR_GLOBAL_OVF) + CHECK_MSR_WRITE_ERROR(HPMwrite(cpu_id, MSR_DEV, MSR_PERF_GLOBAL_OVF_CTRL, ovf_values_core)); + VERBOSEPRINTREG(cpu_id, MSR_PERF_GLOBAL_CTRL, LLU_CAST 0x0ULL, CLEAR_GLOBAL_CTRL) + CHECK_MSR_WRITE_ERROR(HPMwrite(cpu_id, MSR_DEV, MSR_PERF_GLOBAL_CTRL, 0x0ULL)); + } + return 0; +} diff --git a/src/includes/perfmon_sierraforrest_counters.h b/src/includes/perfmon_sierraforrest_counters.h new file mode 100644 index 000000000..706e45a52 --- /dev/null +++ b/src/includes/perfmon_sierraforrest_counters.h @@ -0,0 +1,135 @@ +/* + * ======================================================================================= + * + * Filename: perfmon_sierraforrest_counters.h + * + * Description: Counter Header File of perfmon module for Intel Granite Rapids. + * + * Version: + * Released: + * + * Author: Thomas Gruber (tr), thomas.roehl@googlemail.com + * Project: likwid + * + * Copyright (C) 2015 RRZE, University Erlangen-Nuremberg + * + * This program is free software: you can redistribute it and/or modify it under + * the terms of the GNU General Public License as published by the Free Software + * Foundation, either version 3 of the License, or (at your option) any later + * version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT ANY + * WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A + * PARTICULAR PURPOSE. See the GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + * + * ======================================================================================= + */ + +#include + +#define NUM_COUNTERS_SIERRAFORREST 27 +#define NUM_COUNTERS_CORE_SIERRAFORREST 18 +#define NUM_COUNTERS_UNCORE_SIERRAFORREST 5 + + +#define SRF_VALID_OPTIONS_FIXED EVENT_OPTION_ANYTHREAD_MASK|EVENT_OPTION_COUNT_KERNEL_MASK +#define SRF_VALID_OPTIONS_PMC EVENT_OPTION_EDGE_MASK|EVENT_OPTION_COUNT_KERNEL_MASK|EVENT_OPTION_INVERT_MASK| \ + EVENT_OPTION_ANYTHREAD_MASK|EVENT_OPTION_IN_TRANS_MASK|EVENT_OPTION_THRESHOLD_MASK + +#define SRF_VALID_OPTIONS_CBOX EVENT_OPTION_EDGE_MASK|EVENT_OPTION_INVERT_MASK|\ + EVENT_OPTION_THRESHOLD_MASK|EVENT_OPTION_TID_MASK +#define SRF_VALID_OPTIONS_UNCORE EVENT_OPTION_EDGE_MASK|EVENT_OPTION_INVERT_MASK|\ + EVENT_OPTION_THRESHOLD_MASK + + +static RegisterMap sierraforrest_counter_map[NUM_COUNTERS_SIERRAFORREST] = { + /* Fixed Counters: instructions retired, cycles unhalted core */ + {"FIXC0", PMC0, FIXED, MSR_PERF_FIXED_CTR_CTRL, MSR_PERF_FIXED_CTR0, 0, MSR_DEV, SRF_VALID_OPTIONS_FIXED}, + {"FIXC1", PMC1, FIXED, MSR_PERF_FIXED_CTR_CTRL, MSR_PERF_FIXED_CTR1, 0, MSR_DEV, SRF_VALID_OPTIONS_FIXED}, + {"FIXC2", PMC2, FIXED, MSR_PERF_FIXED_CTR_CTRL, MSR_PERF_FIXED_CTR2, 0, MSR_DEV, SRF_VALID_OPTIONS_FIXED}, + {"FIXC3", PMC3, FIXED, MSR_PERF_FIXED_CTR_CTRL, MSR_PERF_FIXED_CTR3, 0, MSR_DEV, SRF_VALID_OPTIONS_FIXED}, + /* PMC Counters: 4 48bit wide */ + {"PMC0", PMC4, PMC, MSR_PERFEVTSEL0, MSR_PMC0, 0, MSR_DEV, SRF_VALID_OPTIONS_PMC}, + {"PMC1", PMC5, PMC, MSR_PERFEVTSEL1, MSR_PMC1, 0, MSR_DEV, SRF_VALID_OPTIONS_PMC}, + {"PMC2", PMC6, PMC, MSR_PERFEVTSEL2, MSR_PMC2, 0, MSR_DEV, SRF_VALID_OPTIONS_PMC|EVENT_OPTION_IN_TRANS_ABORT_MASK}, + {"PMC3", PMC7, PMC, MSR_PERFEVTSEL3, MSR_PMC3, 0, MSR_DEV, SRF_VALID_OPTIONS_PMC}, + /* Additional PMC Counters if HyperThreading is not active: 4 48bit wide */ + {"PMC4", PMC8, PMC, MSR_PERFEVTSEL4, MSR_PMC4, 0, MSR_DEV, SRF_VALID_OPTIONS_PMC}, + {"PMC5", PMC9, PMC, MSR_PERFEVTSEL5, MSR_PMC5, 0, MSR_DEV, SRF_VALID_OPTIONS_PMC}, + {"PMC6", PMC10, PMC, MSR_PERFEVTSEL6, MSR_PMC6, 0, MSR_DEV, SRF_VALID_OPTIONS_PMC|EVENT_OPTION_IN_TRANS_ABORT_MASK}, + {"PMC7", PMC11, PMC, MSR_PERFEVTSEL7, MSR_PMC7, 0, MSR_DEV, SRF_VALID_OPTIONS_PMC}, + /* Temperature Sensor*/ + {"TMP0", PMC12, THERMAL, 0, IA32_THERM_STATUS, 0, MSR_DEV, EVENT_OPTION_NONE_MASK}, + /* Vcore Status*/ + {"VTG0", PMC13, VOLTAGE, 0, MSR_PERF_STATUS, 0, MSR_DEV, EVENT_OPTION_NONE_MASK}, + /* Intel Performance Metrics */ + {"TMA0", PMC14, METRICS, 0, MSR_PERF_METRICS, 0, MSR_DEV, EVENT_OPTION_NONE_MASK}, + {"TMA1", PMC15, METRICS, 0, MSR_PERF_METRICS, 0, MSR_DEV, EVENT_OPTION_NONE_MASK}, + {"TMA2", PMC16, METRICS, 0, MSR_PERF_METRICS, 0, MSR_DEV, EVENT_OPTION_NONE_MASK}, + {"TMA3", PMC17, METRICS, 0, MSR_PERF_METRICS, 0, MSR_DEV, EVENT_OPTION_NONE_MASK}, + {"TMA4", PMC18, METRICS, 0, MSR_PERF_METRICS, 0, MSR_DEV, EVENT_OPTION_NONE_MASK}, + {"TMA5", PMC19, METRICS, 0, MSR_PERF_METRICS, 0, MSR_DEV, EVENT_OPTION_NONE_MASK}, + {"TMA6", PMC20, METRICS, 0, MSR_PERF_METRICS, 0, MSR_DEV, EVENT_OPTION_NONE_MASK}, + {"TMA7", PMC21, METRICS, 0, MSR_PERF_METRICS, 0, MSR_DEV, EVENT_OPTION_NONE_MASK}, + /* RAPL counters */ + {"PWR0", PMC22, POWER, 0, MSR_PKG_ENERGY_STATUS, 0, MSR_DEV, EVENT_OPTION_NONE_MASK}, + {"PWR1", PMC23, POWER, 0, MSR_PP0_ENERGY_STATUS, 0, MSR_DEV, EVENT_OPTION_NONE_MASK}, + {"PWR2", PMC24, POWER, 0, MSR_PP1_ENERGY_STATUS, 0, MSR_DEV, EVENT_OPTION_NONE_MASK}, + {"PWR3", PMC25, POWER, 0, MSR_DRAM_ENERGY_STATUS, 0, MSR_DEV, EVENT_OPTION_NONE_MASK}, + {"PWR4", PMC26, POWER, 0, MSR_PLATFORM_ENERGY_STATUS, 0, MSR_DEV, EVENT_OPTION_NONE_MASK}, +}; + +static BoxMap sierraforrest_box_map[NUM_UNITS] = { + [FIXED] = {MSR_PERF_GLOBAL_CTRL, MSR_V4_PERF_GLOBAL_STATUS, MSR_V4_PERF_GLOBAL_STATUS_RESET, 0, 0, 0, 48}, + [PMC] = {MSR_PERF_GLOBAL_CTRL, MSR_V4_PERF_GLOBAL_STATUS, MSR_V4_PERF_GLOBAL_STATUS_RESET, 0, 0, 0, 48}, + [THERMAL] = {0, 0, 0, 0, 0, 0, 8}, + [POWER] = {0, 0, 0, 0, 0, 0, 32}, + [VOLTAGE] = {0, 0, 0, 0, 0, 0, 16}, + [METRICS] = {0, MSR_V4_PERF_GLOBAL_STATUS, MSR_V4_PERF_GLOBAL_STATUS, 48, 0, 0, 8}, +}; + +static PciDevice sierraforrest_pci_devices[MAX_NUM_PCI_DEVICES] = { + [MSR_DEV] = {NODEVTYPE, "", "MSR", ""}, +}; + +static char* sierraforrest_translate_types[NUM_UNITS] = { + [FIXED] = "/sys/bus/event_source/devices/cpu", + [PMC] = "/sys/bus/event_source/devices/cpu", + // I don't get it to work, so no TMA metrics with perf_event at the moment + //[METRICS] = "/sys/bus/event_source/devices/cpu", + [POWER] = "/sys/bus/event_source/devices/power", +}; + + +static char* registerTypeNamesSierraForrest[MAX_UNITS] = { +}; + +#define SRF_DEVICE_ID_CHA 0 +#define SRF_DEVICE_ID_IIO 1 +#define SRF_DEVICE_ID_IRP 2 +#define SRF_DEVICE_ID_iMC 6 +#define SRF_DEVICE_ID_UPI 8 +#define SRF_DEVICE_ID_PCU 4 +#define SRF_DEVICE_ID_UBOX 5 +#define SRF_DEVICE_ID_B2UPI 18 +#define SRF_DEVICE_ID_B2CMI 16 +#define SRF_DEVICE_ID_B2CXL 17 +#define SRF_DEVICE_ID_MDF 20 + +static PerfmonUncoreDiscovery sierraforrest_uncore_discovery_map[] = { + {"CBOX", SRF_DEVICE_ID_CHA, 127, MSR_CBOX_DEVICE_C0}, + {"MBOX", SRF_DEVICE_ID_iMC, 15, MMIO_IMC_DEVICE_0_CH_0}, + {"UBOX", SRF_DEVICE_ID_UBOX, 1, MSR_UBOX_DEVICE}, + {"WBOX", SRF_DEVICE_ID_PCU, 3, MSR_PCU_DEVICE_0}, + {"IRP", SRF_DEVICE_ID_IRP, 15, MSR_IRP_DEVICE_0}, + {"IIO", SRF_DEVICE_ID_IIO, 15, MSR_IIO_DEVICE_0}, + {"QBOX", SRF_DEVICE_ID_UPI, 3, PCI_QPI_DEVICE_PORT_0}, + {"MDF", SRF_DEVICE_ID_MDF, 49, MSR_MDF_DEVICE_0}, + {"M2M", SRF_DEVICE_ID_B2CMI, 31, PCI_HA_DEVICE_0}, + {"RBOX", SRF_DEVICE_ID_B2UPI, 3, PCI_R3QPI_DEVICE_LINK_0}, + {"PBOX", SRF_DEVICE_ID_B2CXL, 31, PCI_R2PCIE_DEVICE0}, + {"INVALID", -1, 0, MSR_DEV} +}; diff --git a/src/includes/perfmon_sierraforrest_events.txt b/src/includes/perfmon_sierraforrest_events.txt new file mode 100644 index 000000000..c40919081 --- /dev/null +++ b/src/includes/perfmon_sierraforrest_events.txt @@ -0,0 +1,81 @@ +# ======================================================================================= +# +# Filename: perfmon_sierraforrest_events.txt +# +# Description: Event list for Intel SierraForrest +# +# Version: +# Released: +# +# Author: Thomas Gruber (tr), thomas.roehl@googlemail.com +# Project: likwid +# +# Copyright (C) 2015 RRZE, University Erlangen-Nuremberg +# +# This program is free software: you can redistribute it and/or modify it under +# the terms of the GNU General Public License as published by the Free Software +# Foundation, either version 3 of the License, or (at your option) any later +# version. +# +# This program is distributed in the hope that it will be useful, but WITHOUT ANY +# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A +# PARTICULAR PURPOSE. See the GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License along with +# this program. If not, see . +# +# ======================================================================================= + +EVENT_TEMP_CORE 0x00 TMP0 +UMASK_TEMP_CORE 0x00 + +EVENT_PWR_PKG_ENERGY 0x02 PWR0 +UMASK_PWR_PKG_ENERGY 0x00 + +EVENT_PWR_PP0_ENERGY 0x01 PWR1 +UMASK_PWR_PP0_ENERGY 0x00 + +EVENT_PWR_PP1_ENERGY 0x04 PWR2 +UMASK_PWR_PP1_ENERGY 0x00 + +EVENT_PWR_DRAM_ENERGY 0x03 PWR3 +UMASK_PWR_DRAM_ENERGY 0x00 + +EVENT_PWR_PLATFORM_ENERGY 0x05 PWR4 +UMASK_PWR_PLATFORM_ENERGY 0x00 + +EVENT_VOLTAGE_CORE 0x00 VTG0 +UMASK_VOLTAGE_CORE 0x00 + +EVENT_INSTR_RETIRED 0x00 FIXC0 +UMASK_INSTR_RETIRED_ANY 0x01 + +EVENT_CPU_CLK_UNHALTED_CORE 0x00 FIXC1 +UMASK_CPU_CLK_UNHALTED_CORE 0x02 + +EVENT_CPU_CLK_UNHALTED_REF 0x00 FIXC2 +UMASK_CPU_CLK_UNHALTED_REF 0x03 + +EVENT_TOPDOWN_SLOTS 0x00 FIXC3 +UMASK_TOPDOWN_SLOTS 0x04 + +EVENT_RETIRING 0x00 TMA0 +UMASK_RETIRING 0x00 + +EVENT_BAD_SPECULATION 0x00 TMA1 +UMASK_BAD_SPECULATION 0x00 + +EVENT_FRONTEND_BOUND 0x00 TMA2 +UMASK_FRONTEND_BOUND 0x00 + +EVENT_BACKEND_BOUND 0x00 TMA3 +UMASK_BACKEND_BOUND 0x00 + +EVENT_CPU_CLOCK_UNHALTED 0x3C PMC +UMASK_CPU_CLOCK_UNHALTED_THREAD_P 0x00 +UMASK_CPU_CLOCK_UNHALTED_REF_XCLK 0x01 +UMASK_CPU_CLOCK_UNHALTED_ONE_THREAD_ACTIVE 0x02 +UMASK_CPU_CLOCK_UNHALTED_REF_DISTRIBUTED 0x08 +# Added by Thomas Gruber: Idea is to count also in halted state +DEFAULT_OPTIONS_CPU_CLOCK_UNHALTED_TOTAL_CYCLES EVENT_OPTION_THRESHOLD=0xA,EVENT_OPTION_INVERT=1 +UMASK_CPU_CLOCK_UNHALTED_TOTAL_CYCLES 0x00 diff --git a/src/includes/perfmon_types.h b/src/includes/perfmon_types.h index 39f88c7f2..a91ef7dba 100644 --- a/src/includes/perfmon_types.h +++ b/src/includes/perfmon_types.h @@ -283,5 +283,13 @@ extern int perfmon_numCoreCounters; extern int perfmon_numUncoreCounters; extern int perfmon_numArchEvents; +typedef struct { + char* name; + int discovery_type; + int max_devices; + PciDeviceIndex base_device; +} PerfmonUncoreDiscovery; + +//#define PERFMON_UNCORE_DISCOVERY_MAP_GUARD {"INVALID", -1, 0, MSR} #endif /*PERFMON_TYPES_H*/ diff --git a/src/includes/registers_types.h b/src/includes/registers_types.h index 3d6a89c92..88b140858 100644 --- a/src/includes/registers_types.h +++ b/src/includes/registers_types.h @@ -34,135 +34,806 @@ #include typedef enum { - PMC0 = 0, - PMC1, PMC2, PMC3, PMC4, PMC5, PMC6, - PMC7, PMC8, PMC9, PMC10, PMC11, PMC12, - PMC13, PMC14, PMC15, PMC16, PMC17, PMC18, - PMC19, PMC20, PMC21, PMC22, PMC23, PMC24, - PMC25, PMC26, PMC27, PMC28, PMC29, PMC30, - PMC31, PMC32, PMC33, PMC34, PMC35, PMC36, - PMC37, PMC38, PMC39, PMC40, PMC41, PMC42, - PMC43, PMC44, PMC45, PMC46, PMC47, PMC48, - PMC49, PMC50, PMC51, PMC52, PMC53, PMC54, - PMC55, PMC56, PMC57, PMC58, PMC59, PMC60, - PMC61, PMC62, PMC63, PMC64, PMC65, PMC66, - PMC67, PMC68, PMC69, PMC70, PMC71, PMC72, - PMC73, PMC74, PMC75, PMC76, PMC77, PMC78, - PMC79, PMC80, PMC81, PMC82, PMC83, PMC84, - PMC85, PMC86, PMC87, PMC88, PMC89, PMC90, - PMC91, PMC92, PMC93, PMC94, PMC95, PMC96, - PMC97, PMC98, PMC99, PMC100, PMC101, PMC102, - PMC103, PMC104, PMC105, PMC106, PMC107, PMC108, - PMC109, PMC110, PMC111, PMC112, PMC113, PMC114, - PMC115, PMC116, PMC117, PMC118, PMC119, PMC120, - PMC121, PMC122, PMC123, PMC124, PMC125, PMC126, - PMC127, PMC128, PMC129, PMC130, PMC131, PMC132, - PMC133, PMC134, PMC135, PMC136, PMC137, PMC138, - PMC139, PMC140, PMC141, PMC142, PMC143, PMC144, - PMC145, PMC146, PMC147, PMC148, PMC149, PMC150, - PMC151, PMC152, PMC153, PMC154, PMC155, PMC156, - PMC157, PMC158, PMC159, PMC160, PMC161, PMC162, - PMC163, PMC164, PMC165, PMC166, PMC167, PMC168, - PMC169, PMC170, PMC171, PMC172, PMC173, PMC174, - PMC175, PMC176, PMC177, PMC178, PMC179, PMC180, - PMC181, PMC182, PMC183, PMC184, PMC185, PMC186, - PMC187, PMC188, PMC189, PMC190, PMC191, PMC192, - PMC193, PMC194, PMC195, PMC196, PMC197, PMC198, - PMC199, PMC200, PMC201, PMC202, PMC203, PMC204, - PMC205, PMC206, PMC207, PMC208, PMC209, PMC210, - PMC211, PMC212, PMC213, PMC214, PMC215, PMC216, - PMC217, PMC218, PMC219, PMC220, PMC221, PMC222, - PMC223, PMC224, PMC225, PMC226, PMC227, PMC228, - PMC229, PMC230, PMC231, PMC232, PMC233, PMC234, - PMC235, PMC236, PMC237, PMC238, PMC239, PMC240, - PMC241, PMC242, PMC243, PMC244, PMC245, PMC246, - PMC247, PMC248, PMC249, PMC250, PMC251, PMC252, - PMC253, PMC254, PMC255, PMC256, PMC257, PMC258, - PMC259, PMC260, PMC261, PMC262, PMC263, PMC264, - PMC265, PMC266, PMC267, PMC268, PMC269, PMC270, - PMC271, PMC272, PMC273, PMC274, PMC275, PMC276, - PMC277, PMC278, PMC279, PMC280, PMC281, PMC282, - PMC283, PMC284, PMC285, PMC286, PMC287, PMC288, - PMC289, PMC290, PMC291, PMC292, PMC293, PMC294, - PMC295, PMC296, PMC297, PMC298, PMC299, PMC300, - PMC301, PMC302, PMC303, PMC304, PMC305, PMC306, - PMC307, PMC308, PMC309, PMC310, PMC311, PMC312, - PMC313, PMC314, PMC315, PMC316, PMC317, PMC318, - PMC319, PMC320, PMC321, PMC322, PMC323, PMC324, - PMC325, PMC326, PMC327, PMC328, PMC329, PMC330, - PMC331, PMC332, PMC333, PMC334, PMC335, PMC336, - PMC337, PMC338, PMC339, PMC340, PMC341, PMC342, - PMC343, PMC344, PMC345, PMC346, PMC347, PMC348, - PMC349, PMC350, PMC351, PMC352, PMC353, PMC354, - PMC355, PMC356, PMC357, PMC358, PMC359, - PMC360, PMC361, PMC362, PMC363, PMC364, PMC365, PMC366, PMC367, PMC368, PMC369, - PMC370, PMC371, PMC372, PMC373, PMC374, PMC375, PMC376, PMC377, PMC378, PMC379, - PMC380, PMC381, PMC382, PMC383, PMC384, PMC385, PMC386, PMC387, PMC388, PMC389, - PMC390, PMC391, PMC392, PMC393, PMC394, PMC395, PMC396, PMC397, PMC398, PMC399, - PMC400, PMC401, PMC402, PMC403, PMC404, PMC405, PMC406, PMC407, PMC408, PMC409, - PMC410, PMC411, PMC412, PMC413, PMC414, PMC415, PMC416, PMC417, PMC418, PMC419, - PMC420, PMC421, PMC422, PMC423, PMC424, PMC425, PMC426, PMC427, PMC428, PMC429, - PMC430, PMC431, PMC432, PMC433, PMC434, PMC435, PMC436, PMC437, PMC438, PMC439, - PMC440, PMC441, PMC442, PMC443, PMC444, PMC445, PMC446, PMC447, PMC448, PMC449, - PMC450, PMC451, PMC452, PMC453, PMC454, PMC455, PMC456, PMC457, PMC458, PMC459, - PMC460, PMC461, PMC462, PMC463, PMC464, PMC465, PMC466, PMC467, PMC468, PMC469, - PMC470, PMC471, PMC472, PMC473, PMC474, PMC475, PMC476, PMC477, PMC478, PMC479, - PMC480, PMC481, PMC482, PMC483, PMC484, PMC485, PMC486, PMC487, PMC488, PMC489, - PMC490, PMC491, PMC492, PMC493, PMC494, PMC495, PMC496, PMC497, PMC498, PMC499, - PMC500, PMC501, PMC502, PMC503, PMC504, PMC505, PMC506, PMC507, PMC508, PMC509, - PMC510, PMC511, PMC512, PMC513, PMC514, PMC515, PMC516, PMC517, PMC518, PMC519, - PMC520, PMC521, PMC522, PMC523, PMC524, PMC525, PMC526, PMC527, PMC528, PMC529, - PMC530, PMC531, PMC532, PMC533, PMC534, PMC535, PMC536, PMC537, PMC538, PMC539, - PMC540, PMC541, PMC542, PMC543, PMC544, PMC545, PMC546, PMC547, PMC548, PMC549, - PMC550, PMC551, PMC552, PMC553, PMC554, PMC555, PMC556, PMC557, PMC558, PMC559, - PMC560, PMC561, PMC562, PMC563, PMC564, PMC565, PMC566, PMC567, PMC568, PMC569, - PMC570, PMC571, PMC572, PMC573, PMC574, PMC575, PMC576, PMC577, PMC578, PMC579, - PMC580, PMC581, PMC582, PMC583, PMC584, PMC585, PMC586, PMC587, PMC588, PMC589, - PMC590, PMC591, PMC592, PMC593, PMC594, PMC595, PMC596, PMC597, PMC598, PMC599, - PMC600, PMC601, PMC602, PMC603, PMC604, PMC605, PMC606, PMC607, PMC608, PMC609, - PMC610, PMC611, PMC612, PMC613, PMC614, PMC615, PMC616, PMC617, PMC618, PMC619, - PMC620, PMC621, PMC622, PMC623, PMC624, PMC625, PMC626, PMC627, PMC628, PMC629, - PMC630, PMC631, PMC632, PMC633, PMC634, PMC635, PMC636, PMC637, PMC638, PMC639, - PMC640, PMC641, PMC642, PMC643, PMC644, PMC645, PMC646, PMC647, PMC648, PMC649, - PMC650, PMC651, PMC652, PMC653, PMC654, PMC655, PMC656, PMC657, PMC658, PMC659, - PMC660, PMC661, PMC662, PMC663, PMC664, PMC665, PMC666, PMC667, PMC668, PMC669, - PMC670, PMC671, PMC672, PMC673, PMC674, PMC675, PMC676, PMC677, PMC678, PMC679, - PMC680, PMC681, PMC682, PMC683, PMC684, PMC685, PMC686, PMC687, PMC688, PMC689, - PMC690, PMC691, PMC692, PMC693, PMC694, PMC695, PMC696, PMC697, PMC698, PMC699, - PMC700, PMC701, PMC702, PMC703, PMC704, PMC705, PMC706, PMC707, PMC708, PMC709, - PMC710, PMC711, PMC712, PMC713, PMC714, PMC715, PMC716, PMC717, PMC718, PMC719, - PMC720, PMC721, PMC722, PMC723, PMC724, PMC725, PMC726, PMC727, PMC728, PMC729, - PMC730, PMC731, PMC732, PMC733, PMC734, PMC735, PMC736, PMC737, PMC738, PMC739, - PMC740, PMC741, PMC742, PMC743, PMC744, PMC745, PMC746, PMC747, PMC748, PMC749, - PMC750, PMC751, PMC752, PMC753, PMC754, PMC755, PMC756, PMC757, PMC758, PMC759, - PMC760, PMC761, PMC762, PMC763, PMC764, PMC765, PMC766, PMC767, PMC768, PMC769, - PMC770, PMC771, PMC772, PMC773, PMC774, PMC775, PMC776, PMC777, PMC778, PMC779, - PMC780, PMC781, PMC782, PMC783, PMC784, PMC785, PMC786, PMC787, PMC788, PMC789, - PMC790, PMC791, PMC792, PMC793, PMC794, PMC795, PMC796, PMC797, PMC798, PMC799, - PMC800, PMC801, PMC802, PMC803, PMC804, PMC805, PMC806, PMC807, PMC808, PMC809, - PMC810, PMC811, PMC812, PMC813, PMC814, PMC815, PMC816, PMC817, PMC818, PMC819, - PMC820, PMC821, PMC822, PMC823, PMC824, PMC825, PMC826, PMC827, PMC828, PMC829, - PMC830, PMC831, PMC832, PMC833, PMC834, PMC835, PMC836, PMC837, PMC838, PMC839, - PMC840, PMC841, PMC842, PMC843, PMC844, PMC845, PMC846, PMC847, PMC848, PMC849, - PMC850, PMC851, PMC852, PMC853, PMC854, PMC855, PMC856, PMC857, PMC858, PMC859, - PMC860, PMC861, PMC862, PMC863, PMC864, PMC865, PMC866, PMC867, PMC868, PMC869, - PMC870, PMC871, PMC872, PMC873, PMC874, PMC875, PMC876, PMC877, PMC878, PMC879, - PMC880, PMC881, PMC882, PMC883, PMC884, PMC885, PMC886, PMC887, PMC888, PMC889, - PMC890, PMC891, PMC892, PMC893, PMC894, PMC895, PMC896, PMC897, PMC898, PMC899, - PMC900, PMC901, PMC902, PMC903, PMC904, PMC905, PMC906, PMC907, PMC908, PMC909, - PMC910, PMC911, PMC912, PMC913, PMC914, PMC915, PMC916, PMC917, PMC918, PMC919, - PMC920, PMC921, PMC922, PMC923, PMC924, PMC925, PMC926, PMC927, PMC928, PMC929, - PMC930, PMC931, PMC932, PMC933, PMC934, PMC935, PMC936, PMC937, PMC938, PMC939, - PMC940, PMC941, PMC942, PMC943, PMC944, PMC945, PMC946, PMC947, PMC948, PMC949, - PMC950, PMC951, PMC952, PMC953, PMC954, PMC955, PMC956, PMC957, PMC958, PMC959, - PMC960, PMC961, PMC962, PMC963, PMC964, PMC965, PMC966, PMC967, PMC968, PMC969, - PMC970, PMC971, PMC972, PMC973, PMC974, PMC975, PMC976, PMC977, PMC978, PMC979, - PMC980, PMC981, PMC982, PMC983, PMC984, PMC985, PMC986, PMC987, PMC988, PMC989, - PMC990, PMC991, PMC992, PMC993, PMC994, PMC995, PMC996, PMC997, PMC998, PMC999, - PMC1000, PMC1001, PMC1002, PMC1003, PMC1004, PMC1005, PMC1006, PMC1007, PMC1008, PMC1009, - PMC1010, PMC1011, PMC1012, PMC1013, PMC1014, PMC1015, PMC1016, PMC1017, PMC1018, PMC1019, - PMC1020, PMC1021, PMC1022, PMC1023, PMC1024, PMC1025, PMC1026, PMC1027, PMC1028, PMC1029, - + PMC0 = 0, PMC1, PMC2, PMC3, PMC4, PMC5, PMC6, PMC7, PMC8, PMC9, + PMC10, PMC11, PMC12, PMC13, PMC14, PMC15, PMC16, PMC17, PMC18, PMC19, + PMC20, PMC21, PMC22, PMC23, PMC24, PMC25, PMC26, PMC27, PMC28, PMC29, + PMC30, PMC31, PMC32, PMC33, PMC34, PMC35, PMC36, PMC37, PMC38, PMC39, + PMC40, PMC41, PMC42, PMC43, PMC44, PMC45, PMC46, PMC47, PMC48, PMC49, + PMC50, PMC51, PMC52, PMC53, PMC54, PMC55, PMC56, PMC57, PMC58, PMC59, + PMC60, PMC61, PMC62, PMC63, PMC64, PMC65, PMC66, PMC67, PMC68, PMC69, + PMC70, PMC71, PMC72, PMC73, PMC74, PMC75, PMC76, PMC77, PMC78, PMC79, + PMC80, PMC81, PMC82, PMC83, PMC84, PMC85, PMC86, PMC87, PMC88, PMC89, + PMC90, PMC91, PMC92, PMC93, PMC94, PMC95, PMC96, PMC97, PMC98, PMC99, + PMC100, PMC101, PMC102, PMC103, PMC104, PMC105, PMC106, PMC107, PMC108, PMC109, + PMC110, PMC111, PMC112, PMC113, PMC114, PMC115, PMC116, PMC117, PMC118, PMC119, + PMC120, PMC121, PMC122, PMC123, PMC124, PMC125, PMC126, PMC127, PMC128, PMC129, + PMC130, PMC131, PMC132, PMC133, PMC134, PMC135, PMC136, PMC137, PMC138, PMC139, + PMC140, PMC141, PMC142, PMC143, PMC144, PMC145, PMC146, PMC147, PMC148, PMC149, + PMC150, PMC151, PMC152, PMC153, PMC154, PMC155, PMC156, PMC157, PMC158, PMC159, + PMC160, PMC161, PMC162, PMC163, PMC164, PMC165, PMC166, PMC167, PMC168, PMC169, + PMC170, PMC171, PMC172, PMC173, PMC174, PMC175, PMC176, PMC177, PMC178, PMC179, + PMC180, PMC181, PMC182, PMC183, PMC184, PMC185, PMC186, PMC187, PMC188, PMC189, + PMC190, PMC191, PMC192, PMC193, PMC194, PMC195, PMC196, PMC197, PMC198, PMC199, + PMC200, PMC201, PMC202, PMC203, PMC204, PMC205, PMC206, PMC207, PMC208, PMC209, + PMC210, PMC211, PMC212, PMC213, PMC214, PMC215, PMC216, PMC217, PMC218, PMC219, + PMC220, PMC221, PMC222, PMC223, PMC224, PMC225, PMC226, PMC227, PMC228, PMC229, + PMC230, PMC231, PMC232, PMC233, PMC234, PMC235, PMC236, PMC237, PMC238, PMC239, + PMC240, PMC241, PMC242, PMC243, PMC244, PMC245, PMC246, PMC247, PMC248, PMC249, + PMC250, PMC251, PMC252, PMC253, PMC254, PMC255, PMC256, PMC257, PMC258, PMC259, + PMC260, PMC261, PMC262, PMC263, PMC264, PMC265, PMC266, PMC267, PMC268, PMC269, + PMC270, PMC271, PMC272, PMC273, PMC274, PMC275, PMC276, PMC277, PMC278, PMC279, + PMC280, PMC281, PMC282, PMC283, PMC284, PMC285, PMC286, PMC287, PMC288, PMC289, + PMC290, PMC291, PMC292, PMC293, PMC294, PMC295, PMC296, PMC297, PMC298, PMC299, + PMC300, PMC301, PMC302, PMC303, PMC304, PMC305, PMC306, PMC307, PMC308, PMC309, + PMC310, PMC311, PMC312, PMC313, PMC314, PMC315, PMC316, PMC317, PMC318, PMC319, + PMC320, PMC321, PMC322, PMC323, PMC324, PMC325, PMC326, PMC327, PMC328, PMC329, + PMC330, PMC331, PMC332, PMC333, PMC334, PMC335, PMC336, PMC337, PMC338, PMC339, + PMC340, PMC341, PMC342, PMC343, PMC344, PMC345, PMC346, PMC347, PMC348, PMC349, + PMC350, PMC351, PMC352, PMC353, PMC354, PMC355, PMC356, PMC357, PMC358, PMC359, + PMC360, PMC361, PMC362, PMC363, PMC364, PMC365, PMC366, PMC367, PMC368, PMC369, + PMC370, PMC371, PMC372, PMC373, PMC374, PMC375, PMC376, PMC377, PMC378, PMC379, + PMC380, PMC381, PMC382, PMC383, PMC384, PMC385, PMC386, PMC387, PMC388, PMC389, + PMC390, PMC391, PMC392, PMC393, PMC394, PMC395, PMC396, PMC397, PMC398, PMC399, + PMC400, PMC401, PMC402, PMC403, PMC404, PMC405, PMC406, PMC407, PMC408, PMC409, + PMC410, PMC411, PMC412, PMC413, PMC414, PMC415, PMC416, PMC417, PMC418, PMC419, + PMC420, PMC421, PMC422, PMC423, PMC424, PMC425, PMC426, PMC427, PMC428, PMC429, + PMC430, PMC431, PMC432, PMC433, PMC434, PMC435, PMC436, PMC437, PMC438, PMC439, + PMC440, PMC441, PMC442, PMC443, PMC444, PMC445, PMC446, PMC447, PMC448, PMC449, + PMC450, PMC451, PMC452, PMC453, PMC454, PMC455, PMC456, PMC457, PMC458, PMC459, + PMC460, PMC461, PMC462, PMC463, PMC464, PMC465, PMC466, PMC467, PMC468, PMC469, + PMC470, PMC471, PMC472, PMC473, PMC474, PMC475, PMC476, PMC477, PMC478, PMC479, + PMC480, PMC481, PMC482, PMC483, PMC484, PMC485, PMC486, PMC487, PMC488, PMC489, + PMC490, PMC491, PMC492, PMC493, PMC494, PMC495, PMC496, PMC497, PMC498, PMC499, + PMC500, PMC501, PMC502, PMC503, PMC504, PMC505, PMC506, PMC507, PMC508, PMC509, + PMC510, PMC511, PMC512, PMC513, PMC514, PMC515, PMC516, PMC517, PMC518, PMC519, + PMC520, PMC521, PMC522, PMC523, PMC524, PMC525, PMC526, PMC527, PMC528, PMC529, + PMC530, PMC531, PMC532, PMC533, PMC534, PMC535, PMC536, PMC537, PMC538, PMC539, + PMC540, PMC541, PMC542, PMC543, PMC544, PMC545, PMC546, PMC547, PMC548, PMC549, + PMC550, PMC551, PMC552, PMC553, PMC554, PMC555, PMC556, PMC557, PMC558, PMC559, + PMC560, PMC561, PMC562, PMC563, PMC564, PMC565, PMC566, PMC567, PMC568, PMC569, + PMC570, PMC571, PMC572, PMC573, PMC574, PMC575, PMC576, PMC577, PMC578, PMC579, + PMC580, PMC581, PMC582, PMC583, PMC584, PMC585, PMC586, PMC587, PMC588, PMC589, + PMC590, PMC591, PMC592, PMC593, PMC594, PMC595, PMC596, PMC597, PMC598, PMC599, + PMC600, PMC601, PMC602, PMC603, PMC604, PMC605, PMC606, PMC607, PMC608, PMC609, + PMC610, PMC611, PMC612, PMC613, PMC614, PMC615, PMC616, PMC617, PMC618, PMC619, + PMC620, PMC621, PMC622, PMC623, PMC624, PMC625, PMC626, PMC627, PMC628, PMC629, + PMC630, PMC631, PMC632, PMC633, PMC634, PMC635, PMC636, PMC637, PMC638, PMC639, + PMC640, PMC641, PMC642, PMC643, PMC644, PMC645, PMC646, PMC647, PMC648, PMC649, + PMC650, PMC651, PMC652, PMC653, PMC654, PMC655, PMC656, PMC657, PMC658, PMC659, + PMC660, PMC661, PMC662, PMC663, PMC664, PMC665, PMC666, PMC667, PMC668, PMC669, + PMC670, PMC671, PMC672, PMC673, PMC674, PMC675, PMC676, PMC677, PMC678, PMC679, + PMC680, PMC681, PMC682, PMC683, PMC684, PMC685, PMC686, PMC687, PMC688, PMC689, + PMC690, PMC691, PMC692, PMC693, PMC694, PMC695, PMC696, PMC697, PMC698, PMC699, + PMC700, PMC701, PMC702, PMC703, PMC704, PMC705, PMC706, PMC707, PMC708, PMC709, + PMC710, PMC711, PMC712, PMC713, PMC714, PMC715, PMC716, PMC717, PMC718, PMC719, + PMC720, PMC721, PMC722, PMC723, PMC724, PMC725, PMC726, PMC727, PMC728, PMC729, + PMC730, PMC731, PMC732, PMC733, PMC734, PMC735, PMC736, PMC737, PMC738, PMC739, + PMC740, PMC741, PMC742, PMC743, PMC744, PMC745, PMC746, PMC747, PMC748, PMC749, + PMC750, PMC751, PMC752, PMC753, PMC754, PMC755, PMC756, PMC757, PMC758, PMC759, + PMC760, PMC761, PMC762, PMC763, PMC764, PMC765, PMC766, PMC767, PMC768, PMC769, + PMC770, PMC771, PMC772, PMC773, PMC774, PMC775, PMC776, PMC777, PMC778, PMC779, + PMC780, PMC781, PMC782, PMC783, PMC784, PMC785, PMC786, PMC787, PMC788, PMC789, + PMC790, PMC791, PMC792, PMC793, PMC794, PMC795, PMC796, PMC797, PMC798, PMC799, + PMC800, PMC801, PMC802, PMC803, PMC804, PMC805, PMC806, PMC807, PMC808, PMC809, + PMC810, PMC811, PMC812, PMC813, PMC814, PMC815, PMC816, PMC817, PMC818, PMC819, + PMC820, PMC821, PMC822, PMC823, PMC824, PMC825, PMC826, PMC827, PMC828, PMC829, + PMC830, PMC831, PMC832, PMC833, PMC834, PMC835, PMC836, PMC837, PMC838, PMC839, + PMC840, PMC841, PMC842, PMC843, PMC844, PMC845, PMC846, PMC847, PMC848, PMC849, + PMC850, PMC851, PMC852, PMC853, PMC854, PMC855, PMC856, PMC857, PMC858, PMC859, + PMC860, PMC861, PMC862, PMC863, PMC864, PMC865, PMC866, PMC867, PMC868, PMC869, + PMC870, PMC871, PMC872, PMC873, PMC874, PMC875, PMC876, PMC877, PMC878, PMC879, + PMC880, PMC881, PMC882, PMC883, PMC884, PMC885, PMC886, PMC887, PMC888, PMC889, + PMC890, PMC891, PMC892, PMC893, PMC894, PMC895, PMC896, PMC897, PMC898, PMC899, + PMC900, PMC901, PMC902, PMC903, PMC904, PMC905, PMC906, PMC907, PMC908, PMC909, + PMC910, PMC911, PMC912, PMC913, PMC914, PMC915, PMC916, PMC917, PMC918, PMC919, + PMC920, PMC921, PMC922, PMC923, PMC924, PMC925, PMC926, PMC927, PMC928, PMC929, + PMC930, PMC931, PMC932, PMC933, PMC934, PMC935, PMC936, PMC937, PMC938, PMC939, + PMC940, PMC941, PMC942, PMC943, PMC944, PMC945, PMC946, PMC947, PMC948, PMC949, + PMC950, PMC951, PMC952, PMC953, PMC954, PMC955, PMC956, PMC957, PMC958, PMC959, + PMC960, PMC961, PMC962, PMC963, PMC964, PMC965, PMC966, PMC967, PMC968, PMC969, + PMC970, PMC971, PMC972, PMC973, PMC974, PMC975, PMC976, PMC977, PMC978, PMC979, + PMC980, PMC981, PMC982, PMC983, PMC984, PMC985, PMC986, PMC987, PMC988, PMC989, + PMC990, PMC991, PMC992, PMC993, PMC994, PMC995, PMC996, PMC997, PMC998, PMC999, + PMC1000, PMC1001, PMC1002, PMC1003, PMC1004, PMC1005, PMC1006, PMC1007, PMC1008, PMC1009, + PMC1010, PMC1011, PMC1012, PMC1013, PMC1014, PMC1015, PMC1016, PMC1017, PMC1018, PMC1019, + PMC1020, PMC1021, PMC1022, PMC1023, PMC1024, PMC1025, PMC1026, PMC1027, PMC1028, PMC1029, + PMC1030, PMC1031, PMC1032, PMC1033, PMC1034, PMC1035, PMC1036, PMC1037, PMC1038, PMC1039, + PMC1040, PMC1041, PMC1042, PMC1043, PMC1044, PMC1045, PMC1046, PMC1047, PMC1048, PMC1049, + PMC1050, PMC1051, PMC1052, PMC1053, PMC1054, PMC1055, PMC1056, PMC1057, PMC1058, PMC1059, + PMC1060, PMC1061, PMC1062, PMC1063, PMC1064, PMC1065, PMC1066, PMC1067, PMC1068, PMC1069, + PMC1070, PMC1071, PMC1072, PMC1073, PMC1074, PMC1075, PMC1076, PMC1077, PMC1078, PMC1079, + PMC1080, PMC1081, PMC1082, PMC1083, PMC1084, PMC1085, PMC1086, PMC1087, PMC1088, PMC1089, + PMC1090, PMC1091, PMC1092, PMC1093, PMC1094, PMC1095, PMC1096, PMC1097, PMC1098, PMC1099, + PMC1100, PMC1101, PMC1102, PMC1103, PMC1104, PMC1105, PMC1106, PMC1107, PMC1108, PMC1109, + PMC1110, PMC1111, PMC1112, PMC1113, PMC1114, PMC1115, PMC1116, PMC1117, PMC1118, PMC1119, + PMC1120, PMC1121, PMC1122, PMC1123, PMC1124, PMC1125, PMC1126, PMC1127, PMC1128, PMC1129, + PMC1130, PMC1131, PMC1132, PMC1133, PMC1134, PMC1135, PMC1136, PMC1137, PMC1138, PMC1139, + PMC1140, PMC1141, PMC1142, PMC1143, PMC1144, PMC1145, PMC1146, PMC1147, PMC1148, PMC1149, + PMC1150, PMC1151, PMC1152, PMC1153, PMC1154, PMC1155, PMC1156, PMC1157, PMC1158, PMC1159, + PMC1160, PMC1161, PMC1162, PMC1163, PMC1164, PMC1165, PMC1166, PMC1167, PMC1168, PMC1169, + PMC1170, PMC1171, PMC1172, PMC1173, PMC1174, PMC1175, PMC1176, PMC1177, PMC1178, PMC1179, + PMC1180, PMC1181, PMC1182, PMC1183, PMC1184, PMC1185, PMC1186, PMC1187, PMC1188, PMC1189, + PMC1190, PMC1191, PMC1192, PMC1193, PMC1194, PMC1195, PMC1196, PMC1197, PMC1198, PMC1199, + PMC1200, PMC1201, PMC1202, PMC1203, PMC1204, PMC1205, PMC1206, PMC1207, PMC1208, PMC1209, + PMC1210, PMC1211, PMC1212, PMC1213, PMC1214, PMC1215, PMC1216, PMC1217, PMC1218, PMC1219, + PMC1220, PMC1221, PMC1222, PMC1223, PMC1224, PMC1225, PMC1226, PMC1227, PMC1228, PMC1229, + PMC1230, PMC1231, PMC1232, PMC1233, PMC1234, PMC1235, PMC1236, PMC1237, PMC1238, PMC1239, + PMC1240, PMC1241, PMC1242, PMC1243, PMC1244, PMC1245, PMC1246, PMC1247, PMC1248, PMC1249, + PMC1250, PMC1251, PMC1252, PMC1253, PMC1254, PMC1255, PMC1256, PMC1257, PMC1258, PMC1259, + PMC1260, PMC1261, PMC1262, PMC1263, PMC1264, PMC1265, PMC1266, PMC1267, PMC1268, PMC1269, + PMC1270, PMC1271, PMC1272, PMC1273, PMC1274, PMC1275, PMC1276, PMC1277, PMC1278, PMC1279, + PMC1280, PMC1281, PMC1282, PMC1283, PMC1284, PMC1285, PMC1286, PMC1287, PMC1288, PMC1289, + PMC1290, PMC1291, PMC1292, PMC1293, PMC1294, PMC1295, PMC1296, PMC1297, PMC1298, PMC1299, + PMC1300, PMC1301, PMC1302, PMC1303, PMC1304, PMC1305, PMC1306, PMC1307, PMC1308, PMC1309, + PMC1310, PMC1311, PMC1312, PMC1313, PMC1314, PMC1315, PMC1316, PMC1317, PMC1318, PMC1319, + PMC1320, PMC1321, PMC1322, PMC1323, PMC1324, PMC1325, PMC1326, PMC1327, PMC1328, PMC1329, + PMC1330, PMC1331, PMC1332, PMC1333, PMC1334, PMC1335, PMC1336, PMC1337, PMC1338, PMC1339, + PMC1340, PMC1341, PMC1342, PMC1343, PMC1344, PMC1345, PMC1346, PMC1347, PMC1348, PMC1349, + PMC1350, PMC1351, PMC1352, PMC1353, PMC1354, PMC1355, PMC1356, PMC1357, PMC1358, PMC1359, + PMC1360, PMC1361, PMC1362, PMC1363, PMC1364, PMC1365, PMC1366, PMC1367, PMC1368, PMC1369, + PMC1370, PMC1371, PMC1372, PMC1373, PMC1374, PMC1375, PMC1376, PMC1377, PMC1378, PMC1379, + PMC1380, PMC1381, PMC1382, PMC1383, PMC1384, PMC1385, PMC1386, PMC1387, PMC1388, PMC1389, + PMC1390, PMC1391, PMC1392, PMC1393, PMC1394, PMC1395, PMC1396, PMC1397, PMC1398, PMC1399, + PMC1400, PMC1401, PMC1402, PMC1403, PMC1404, PMC1405, PMC1406, PMC1407, PMC1408, PMC1409, + PMC1410, PMC1411, PMC1412, PMC1413, PMC1414, PMC1415, PMC1416, PMC1417, PMC1418, PMC1419, + PMC1420, PMC1421, PMC1422, PMC1423, PMC1424, PMC1425, PMC1426, PMC1427, PMC1428, PMC1429, + PMC1430, PMC1431, PMC1432, PMC1433, PMC1434, PMC1435, PMC1436, PMC1437, PMC1438, PMC1439, + PMC1440, PMC1441, PMC1442, PMC1443, PMC1444, PMC1445, PMC1446, PMC1447, PMC1448, PMC1449, + PMC1450, PMC1451, PMC1452, PMC1453, PMC1454, PMC1455, PMC1456, PMC1457, PMC1458, PMC1459, + PMC1460, PMC1461, PMC1462, PMC1463, PMC1464, PMC1465, PMC1466, PMC1467, PMC1468, PMC1469, + PMC1470, PMC1471, PMC1472, PMC1473, PMC1474, PMC1475, PMC1476, PMC1477, PMC1478, PMC1479, + PMC1480, PMC1481, PMC1482, PMC1483, PMC1484, PMC1485, PMC1486, PMC1487, PMC1488, PMC1489, + PMC1490, PMC1491, PMC1492, PMC1493, PMC1494, PMC1495, PMC1496, PMC1497, PMC1498, PMC1499, + PMC1500, PMC1501, PMC1502, PMC1503, PMC1504, PMC1505, PMC1506, PMC1507, PMC1508, PMC1509, + PMC1510, PMC1511, PMC1512, PMC1513, PMC1514, PMC1515, PMC1516, PMC1517, PMC1518, PMC1519, + PMC1520, PMC1521, PMC1522, PMC1523, PMC1524, PMC1525, PMC1526, PMC1527, PMC1528, PMC1529, + PMC1530, PMC1531, PMC1532, PMC1533, PMC1534, PMC1535, PMC1536, PMC1537, PMC1538, PMC1539, + PMC1540, PMC1541, PMC1542, PMC1543, PMC1544, PMC1545, PMC1546, PMC1547, PMC1548, PMC1549, + PMC1550, PMC1551, PMC1552, PMC1553, PMC1554, PMC1555, PMC1556, PMC1557, PMC1558, PMC1559, + PMC1560, PMC1561, PMC1562, PMC1563, PMC1564, PMC1565, PMC1566, PMC1567, PMC1568, PMC1569, + PMC1570, PMC1571, PMC1572, PMC1573, PMC1574, PMC1575, PMC1576, PMC1577, PMC1578, PMC1579, + PMC1580, PMC1581, PMC1582, PMC1583, PMC1584, PMC1585, PMC1586, PMC1587, PMC1588, PMC1589, + PMC1590, PMC1591, PMC1592, PMC1593, PMC1594, PMC1595, PMC1596, PMC1597, PMC1598, PMC1599, + PMC1600, PMC1601, PMC1602, PMC1603, PMC1604, PMC1605, PMC1606, PMC1607, PMC1608, PMC1609, + PMC1610, PMC1611, PMC1612, PMC1613, PMC1614, PMC1615, PMC1616, PMC1617, PMC1618, PMC1619, + PMC1620, PMC1621, PMC1622, PMC1623, PMC1624, PMC1625, PMC1626, PMC1627, PMC1628, PMC1629, + PMC1630, PMC1631, PMC1632, PMC1633, PMC1634, PMC1635, PMC1636, PMC1637, PMC1638, PMC1639, + PMC1640, PMC1641, PMC1642, PMC1643, PMC1644, PMC1645, PMC1646, PMC1647, PMC1648, PMC1649, + PMC1650, PMC1651, PMC1652, PMC1653, PMC1654, PMC1655, PMC1656, PMC1657, PMC1658, PMC1659, + PMC1660, PMC1661, PMC1662, PMC1663, PMC1664, PMC1665, PMC1666, PMC1667, PMC1668, PMC1669, + PMC1670, PMC1671, PMC1672, PMC1673, PMC1674, PMC1675, PMC1676, PMC1677, PMC1678, PMC1679, + PMC1680, PMC1681, PMC1682, PMC1683, PMC1684, PMC1685, PMC1686, PMC1687, PMC1688, PMC1689, + PMC1690, PMC1691, PMC1692, PMC1693, PMC1694, PMC1695, PMC1696, PMC1697, PMC1698, PMC1699, + PMC1700, PMC1701, PMC1702, PMC1703, PMC1704, PMC1705, PMC1706, PMC1707, PMC1708, PMC1709, + PMC1710, PMC1711, PMC1712, PMC1713, PMC1714, PMC1715, PMC1716, PMC1717, PMC1718, PMC1719, + PMC1720, PMC1721, PMC1722, PMC1723, PMC1724, PMC1725, PMC1726, PMC1727, PMC1728, PMC1729, + PMC1730, PMC1731, PMC1732, PMC1733, PMC1734, PMC1735, PMC1736, PMC1737, PMC1738, PMC1739, + PMC1740, PMC1741, PMC1742, PMC1743, PMC1744, PMC1745, PMC1746, PMC1747, PMC1748, PMC1749, + PMC1750, PMC1751, PMC1752, PMC1753, PMC1754, PMC1755, PMC1756, PMC1757, PMC1758, PMC1759, + PMC1760, PMC1761, PMC1762, PMC1763, PMC1764, PMC1765, PMC1766, PMC1767, PMC1768, PMC1769, + PMC1770, PMC1771, PMC1772, PMC1773, PMC1774, PMC1775, PMC1776, PMC1777, PMC1778, PMC1779, + PMC1780, PMC1781, PMC1782, PMC1783, PMC1784, PMC1785, PMC1786, PMC1787, PMC1788, PMC1789, + PMC1790, PMC1791, PMC1792, PMC1793, PMC1794, PMC1795, PMC1796, PMC1797, PMC1798, PMC1799, + PMC1800, PMC1801, PMC1802, PMC1803, PMC1804, PMC1805, PMC1806, PMC1807, PMC1808, PMC1809, + PMC1810, PMC1811, PMC1812, PMC1813, PMC1814, PMC1815, PMC1816, PMC1817, PMC1818, PMC1819, + PMC1820, PMC1821, PMC1822, PMC1823, PMC1824, PMC1825, PMC1826, PMC1827, PMC1828, PMC1829, + PMC1830, PMC1831, PMC1832, PMC1833, PMC1834, PMC1835, PMC1836, PMC1837, PMC1838, PMC1839, + PMC1840, PMC1841, PMC1842, PMC1843, PMC1844, PMC1845, PMC1846, PMC1847, PMC1848, PMC1849, + PMC1850, PMC1851, PMC1852, PMC1853, PMC1854, PMC1855, PMC1856, PMC1857, PMC1858, PMC1859, + PMC1860, PMC1861, PMC1862, PMC1863, PMC1864, PMC1865, PMC1866, PMC1867, PMC1868, PMC1869, + PMC1870, PMC1871, PMC1872, PMC1873, PMC1874, PMC1875, PMC1876, PMC1877, PMC1878, PMC1879, + PMC1880, PMC1881, PMC1882, PMC1883, PMC1884, PMC1885, PMC1886, PMC1887, PMC1888, PMC1889, + PMC1890, PMC1891, PMC1892, PMC1893, PMC1894, PMC1895, PMC1896, PMC1897, PMC1898, PMC1899, + PMC1900, PMC1901, PMC1902, PMC1903, PMC1904, PMC1905, PMC1906, PMC1907, PMC1908, PMC1909, + PMC1910, PMC1911, PMC1912, PMC1913, PMC1914, PMC1915, PMC1916, PMC1917, PMC1918, PMC1919, + PMC1920, PMC1921, PMC1922, PMC1923, PMC1924, PMC1925, PMC1926, PMC1927, PMC1928, PMC1929, + PMC1930, PMC1931, PMC1932, PMC1933, PMC1934, PMC1935, PMC1936, PMC1937, PMC1938, PMC1939, + PMC1940, PMC1941, PMC1942, PMC1943, PMC1944, PMC1945, PMC1946, PMC1947, PMC1948, PMC1949, + PMC1950, PMC1951, PMC1952, PMC1953, PMC1954, PMC1955, PMC1956, PMC1957, PMC1958, PMC1959, + PMC1960, PMC1961, PMC1962, PMC1963, PMC1964, PMC1965, PMC1966, PMC1967, PMC1968, PMC1969, + PMC1970, PMC1971, PMC1972, PMC1973, PMC1974, PMC1975, PMC1976, PMC1977, PMC1978, PMC1979, + PMC1980, PMC1981, PMC1982, PMC1983, PMC1984, PMC1985, PMC1986, PMC1987, PMC1988, PMC1989, + PMC1990, PMC1991, PMC1992, PMC1993, PMC1994, PMC1995, PMC1996, PMC1997, PMC1998, PMC1999, + PMC2000, PMC2001, PMC2002, PMC2003, PMC2004, PMC2005, PMC2006, PMC2007, PMC2008, PMC2009, + PMC2010, PMC2011, PMC2012, PMC2013, PMC2014, PMC2015, PMC2016, PMC2017, PMC2018, PMC2019, + PMC2020, PMC2021, PMC2022, PMC2023, PMC2024, PMC2025, PMC2026, PMC2027, PMC2028, PMC2029, + PMC2030, PMC2031, PMC2032, PMC2033, PMC2034, PMC2035, PMC2036, PMC2037, PMC2038, PMC2039, + PMC2040, PMC2041, PMC2042, PMC2043, PMC2044, PMC2045, PMC2046, PMC2047, PMC2048, PMC2049, + PMC2050, PMC2051, PMC2052, PMC2053, PMC2054, PMC2055, PMC2056, PMC2057, PMC2058, PMC2059, + PMC2060, PMC2061, PMC2062, PMC2063, PMC2064, PMC2065, PMC2066, PMC2067, PMC2068, PMC2069, + PMC2070, PMC2071, PMC2072, PMC2073, PMC2074, PMC2075, PMC2076, PMC2077, PMC2078, PMC2079, + PMC2080, PMC2081, PMC2082, PMC2083, PMC2084, PMC2085, PMC2086, PMC2087, PMC2088, PMC2089, + PMC2090, PMC2091, PMC2092, PMC2093, PMC2094, PMC2095, PMC2096, PMC2097, PMC2098, PMC2099, + PMC2100, PMC2101, PMC2102, PMC2103, PMC2104, PMC2105, PMC2106, PMC2107, PMC2108, PMC2109, + PMC2110, PMC2111, PMC2112, PMC2113, PMC2114, PMC2115, PMC2116, PMC2117, PMC2118, PMC2119, + PMC2120, PMC2121, PMC2122, PMC2123, PMC2124, PMC2125, PMC2126, PMC2127, PMC2128, PMC2129, + PMC2130, PMC2131, PMC2132, PMC2133, PMC2134, PMC2135, PMC2136, PMC2137, PMC2138, PMC2139, + PMC2140, PMC2141, PMC2142, PMC2143, PMC2144, PMC2145, PMC2146, PMC2147, PMC2148, PMC2149, + PMC2150, PMC2151, PMC2152, PMC2153, PMC2154, PMC2155, PMC2156, PMC2157, PMC2158, PMC2159, + PMC2160, PMC2161, PMC2162, PMC2163, PMC2164, PMC2165, PMC2166, PMC2167, PMC2168, PMC2169, + PMC2170, PMC2171, PMC2172, PMC2173, PMC2174, PMC2175, PMC2176, PMC2177, PMC2178, PMC2179, + PMC2180, PMC2181, PMC2182, PMC2183, PMC2184, PMC2185, PMC2186, PMC2187, PMC2188, PMC2189, + PMC2190, PMC2191, PMC2192, PMC2193, PMC2194, PMC2195, PMC2196, PMC2197, PMC2198, PMC2199, + PMC2200, PMC2201, PMC2202, PMC2203, PMC2204, PMC2205, PMC2206, PMC2207, PMC2208, PMC2209, + PMC2210, PMC2211, PMC2212, PMC2213, PMC2214, PMC2215, PMC2216, PMC2217, PMC2218, PMC2219, + PMC2220, PMC2221, PMC2222, PMC2223, PMC2224, PMC2225, PMC2226, PMC2227, PMC2228, PMC2229, + PMC2230, PMC2231, PMC2232, PMC2233, PMC2234, PMC2235, PMC2236, PMC2237, PMC2238, PMC2239, + PMC2240, PMC2241, PMC2242, PMC2243, PMC2244, PMC2245, PMC2246, PMC2247, PMC2248, PMC2249, + PMC2250, PMC2251, PMC2252, PMC2253, PMC2254, PMC2255, PMC2256, PMC2257, PMC2258, PMC2259, + PMC2260, PMC2261, PMC2262, PMC2263, PMC2264, PMC2265, PMC2266, PMC2267, PMC2268, PMC2269, + PMC2270, PMC2271, PMC2272, PMC2273, PMC2274, PMC2275, PMC2276, PMC2277, PMC2278, PMC2279, + PMC2280, PMC2281, PMC2282, PMC2283, PMC2284, PMC2285, PMC2286, PMC2287, PMC2288, PMC2289, + PMC2290, PMC2291, PMC2292, PMC2293, PMC2294, PMC2295, PMC2296, PMC2297, PMC2298, PMC2299, + PMC2300, PMC2301, PMC2302, PMC2303, PMC2304, PMC2305, PMC2306, PMC2307, PMC2308, PMC2309, + PMC2310, PMC2311, PMC2312, PMC2313, PMC2314, PMC2315, PMC2316, PMC2317, PMC2318, PMC2319, + PMC2320, PMC2321, PMC2322, PMC2323, PMC2324, PMC2325, PMC2326, PMC2327, PMC2328, PMC2329, + PMC2330, PMC2331, PMC2332, PMC2333, PMC2334, PMC2335, PMC2336, PMC2337, PMC2338, PMC2339, + PMC2340, PMC2341, PMC2342, PMC2343, PMC2344, PMC2345, PMC2346, PMC2347, PMC2348, PMC2349, + PMC2350, PMC2351, PMC2352, PMC2353, PMC2354, PMC2355, PMC2356, PMC2357, PMC2358, PMC2359, + PMC2360, PMC2361, PMC2362, PMC2363, PMC2364, PMC2365, PMC2366, PMC2367, PMC2368, PMC2369, + PMC2370, PMC2371, PMC2372, PMC2373, PMC2374, PMC2375, PMC2376, PMC2377, PMC2378, PMC2379, + PMC2380, PMC2381, PMC2382, PMC2383, PMC2384, PMC2385, PMC2386, PMC2387, PMC2388, PMC2389, + PMC2390, PMC2391, PMC2392, PMC2393, PMC2394, PMC2395, PMC2396, PMC2397, PMC2398, PMC2399, + PMC2400, PMC2401, PMC2402, PMC2403, PMC2404, PMC2405, PMC2406, PMC2407, PMC2408, PMC2409, + PMC2410, PMC2411, PMC2412, PMC2413, PMC2414, PMC2415, PMC2416, PMC2417, PMC2418, PMC2419, + PMC2420, PMC2421, PMC2422, PMC2423, PMC2424, PMC2425, PMC2426, PMC2427, PMC2428, PMC2429, + PMC2430, PMC2431, PMC2432, PMC2433, PMC2434, PMC2435, PMC2436, PMC2437, PMC2438, PMC2439, + PMC2440, PMC2441, PMC2442, PMC2443, PMC2444, PMC2445, PMC2446, PMC2447, PMC2448, PMC2449, + PMC2450, PMC2451, PMC2452, PMC2453, PMC2454, PMC2455, PMC2456, PMC2457, PMC2458, PMC2459, + PMC2460, PMC2461, PMC2462, PMC2463, PMC2464, PMC2465, PMC2466, PMC2467, PMC2468, PMC2469, + PMC2470, PMC2471, PMC2472, PMC2473, PMC2474, PMC2475, PMC2476, PMC2477, PMC2478, PMC2479, + PMC2480, PMC2481, PMC2482, PMC2483, PMC2484, PMC2485, PMC2486, PMC2487, PMC2488, PMC2489, + PMC2490, PMC2491, PMC2492, PMC2493, PMC2494, PMC2495, PMC2496, PMC2497, PMC2498, PMC2499, + PMC2500, PMC2501, PMC2502, PMC2503, PMC2504, PMC2505, PMC2506, PMC2507, PMC2508, PMC2509, + PMC2510, PMC2511, PMC2512, PMC2513, PMC2514, PMC2515, PMC2516, PMC2517, PMC2518, PMC2519, + PMC2520, PMC2521, PMC2522, PMC2523, PMC2524, PMC2525, PMC2526, PMC2527, PMC2528, PMC2529, + PMC2530, PMC2531, PMC2532, PMC2533, PMC2534, PMC2535, PMC2536, PMC2537, PMC2538, PMC2539, + PMC2540, PMC2541, PMC2542, PMC2543, PMC2544, PMC2545, PMC2546, PMC2547, PMC2548, PMC2549, + PMC2550, PMC2551, PMC2552, PMC2553, PMC2554, PMC2555, PMC2556, PMC2557, PMC2558, PMC2559, + PMC2560, PMC2561, PMC2562, PMC2563, PMC2564, PMC2565, PMC2566, PMC2567, PMC2568, PMC2569, + PMC2570, PMC2571, PMC2572, PMC2573, PMC2574, PMC2575, PMC2576, PMC2577, PMC2578, PMC2579, + PMC2580, PMC2581, PMC2582, PMC2583, PMC2584, PMC2585, PMC2586, PMC2587, PMC2588, PMC2589, + PMC2590, PMC2591, PMC2592, PMC2593, PMC2594, PMC2595, PMC2596, PMC2597, PMC2598, PMC2599, + PMC2600, PMC2601, PMC2602, PMC2603, PMC2604, PMC2605, PMC2606, PMC2607, PMC2608, PMC2609, + PMC2610, PMC2611, PMC2612, PMC2613, PMC2614, PMC2615, PMC2616, PMC2617, PMC2618, PMC2619, + PMC2620, PMC2621, PMC2622, PMC2623, PMC2624, PMC2625, PMC2626, PMC2627, PMC2628, PMC2629, + PMC2630, PMC2631, PMC2632, PMC2633, PMC2634, PMC2635, PMC2636, PMC2637, PMC2638, PMC2639, + PMC2640, PMC2641, PMC2642, PMC2643, PMC2644, PMC2645, PMC2646, PMC2647, PMC2648, PMC2649, + PMC2650, PMC2651, PMC2652, PMC2653, PMC2654, PMC2655, PMC2656, PMC2657, PMC2658, PMC2659, + PMC2660, PMC2661, PMC2662, PMC2663, PMC2664, PMC2665, PMC2666, PMC2667, PMC2668, PMC2669, + PMC2670, PMC2671, PMC2672, PMC2673, PMC2674, PMC2675, PMC2676, PMC2677, PMC2678, PMC2679, + PMC2680, PMC2681, PMC2682, PMC2683, PMC2684, PMC2685, PMC2686, PMC2687, PMC2688, PMC2689, + PMC2690, PMC2691, PMC2692, PMC2693, PMC2694, PMC2695, PMC2696, PMC2697, PMC2698, PMC2699, + PMC2700, PMC2701, PMC2702, PMC2703, PMC2704, PMC2705, PMC2706, PMC2707, PMC2708, PMC2709, + PMC2710, PMC2711, PMC2712, PMC2713, PMC2714, PMC2715, PMC2716, PMC2717, PMC2718, PMC2719, + PMC2720, PMC2721, PMC2722, PMC2723, PMC2724, PMC2725, PMC2726, PMC2727, PMC2728, PMC2729, + PMC2730, PMC2731, PMC2732, PMC2733, PMC2734, PMC2735, PMC2736, PMC2737, PMC2738, PMC2739, + PMC2740, PMC2741, PMC2742, PMC2743, PMC2744, PMC2745, PMC2746, PMC2747, PMC2748, PMC2749, + PMC2750, PMC2751, PMC2752, PMC2753, PMC2754, PMC2755, PMC2756, PMC2757, PMC2758, PMC2759, + PMC2760, PMC2761, PMC2762, PMC2763, PMC2764, PMC2765, PMC2766, PMC2767, PMC2768, PMC2769, + PMC2770, PMC2771, PMC2772, PMC2773, PMC2774, PMC2775, PMC2776, PMC2777, PMC2778, PMC2779, + PMC2780, PMC2781, PMC2782, PMC2783, PMC2784, PMC2785, PMC2786, PMC2787, PMC2788, PMC2789, + PMC2790, PMC2791, PMC2792, PMC2793, PMC2794, PMC2795, PMC2796, PMC2797, PMC2798, PMC2799, + PMC2800, PMC2801, PMC2802, PMC2803, PMC2804, PMC2805, PMC2806, PMC2807, PMC2808, PMC2809, + PMC2810, PMC2811, PMC2812, PMC2813, PMC2814, PMC2815, PMC2816, PMC2817, PMC2818, PMC2819, + PMC2820, PMC2821, PMC2822, PMC2823, PMC2824, PMC2825, PMC2826, PMC2827, PMC2828, PMC2829, + PMC2830, PMC2831, PMC2832, PMC2833, PMC2834, PMC2835, PMC2836, PMC2837, PMC2838, PMC2839, + PMC2840, PMC2841, PMC2842, PMC2843, PMC2844, PMC2845, PMC2846, PMC2847, PMC2848, PMC2849, + PMC2850, PMC2851, PMC2852, PMC2853, PMC2854, PMC2855, PMC2856, PMC2857, PMC2858, PMC2859, + PMC2860, PMC2861, PMC2862, PMC2863, PMC2864, PMC2865, PMC2866, PMC2867, PMC2868, PMC2869, + PMC2870, PMC2871, PMC2872, PMC2873, PMC2874, PMC2875, PMC2876, PMC2877, PMC2878, PMC2879, + PMC2880, PMC2881, PMC2882, PMC2883, PMC2884, PMC2885, PMC2886, PMC2887, PMC2888, PMC2889, + PMC2890, PMC2891, PMC2892, PMC2893, PMC2894, PMC2895, PMC2896, PMC2897, PMC2898, PMC2899, + PMC2900, PMC2901, PMC2902, PMC2903, PMC2904, PMC2905, PMC2906, PMC2907, PMC2908, PMC2909, + PMC2910, PMC2911, PMC2912, PMC2913, PMC2914, PMC2915, PMC2916, PMC2917, PMC2918, PMC2919, + PMC2920, PMC2921, PMC2922, PMC2923, PMC2924, PMC2925, PMC2926, PMC2927, PMC2928, PMC2929, + PMC2930, PMC2931, PMC2932, PMC2933, PMC2934, PMC2935, PMC2936, PMC2937, PMC2938, PMC2939, + PMC2940, PMC2941, PMC2942, PMC2943, PMC2944, PMC2945, PMC2946, PMC2947, PMC2948, PMC2949, + PMC2950, PMC2951, PMC2952, PMC2953, PMC2954, PMC2955, PMC2956, PMC2957, PMC2958, PMC2959, + PMC2960, PMC2961, PMC2962, PMC2963, PMC2964, PMC2965, PMC2966, PMC2967, PMC2968, PMC2969, + PMC2970, PMC2971, PMC2972, PMC2973, PMC2974, PMC2975, PMC2976, PMC2977, PMC2978, PMC2979, + PMC2980, PMC2981, PMC2982, PMC2983, PMC2984, PMC2985, PMC2986, PMC2987, PMC2988, PMC2989, + PMC2990, PMC2991, PMC2992, PMC2993, PMC2994, PMC2995, PMC2996, PMC2997, PMC2998, PMC2999, + PMC3000, PMC3001, PMC3002, PMC3003, PMC3004, PMC3005, PMC3006, PMC3007, PMC3008, PMC3009, + PMC3010, PMC3011, PMC3012, PMC3013, PMC3014, PMC3015, PMC3016, PMC3017, PMC3018, PMC3019, + PMC3020, PMC3021, PMC3022, PMC3023, PMC3024, PMC3025, PMC3026, PMC3027, PMC3028, PMC3029, + PMC3030, PMC3031, PMC3032, PMC3033, PMC3034, PMC3035, PMC3036, PMC3037, PMC3038, PMC3039, + PMC3040, PMC3041, PMC3042, PMC3043, PMC3044, PMC3045, PMC3046, PMC3047, PMC3048, PMC3049, + PMC3050, PMC3051, PMC3052, PMC3053, PMC3054, PMC3055, PMC3056, PMC3057, PMC3058, PMC3059, + PMC3060, PMC3061, PMC3062, PMC3063, PMC3064, PMC3065, PMC3066, PMC3067, PMC3068, PMC3069, + PMC3070, PMC3071, PMC3072, PMC3073, PMC3074, PMC3075, PMC3076, PMC3077, PMC3078, PMC3079, + PMC3080, PMC3081, PMC3082, PMC3083, PMC3084, PMC3085, PMC3086, PMC3087, PMC3088, PMC3089, + PMC3090, PMC3091, PMC3092, PMC3093, PMC3094, PMC3095, PMC3096, PMC3097, PMC3098, PMC3099, + PMC3100, PMC3101, PMC3102, PMC3103, PMC3104, PMC3105, PMC3106, PMC3107, PMC3108, PMC3109, + PMC3110, PMC3111, PMC3112, PMC3113, PMC3114, PMC3115, PMC3116, PMC3117, PMC3118, PMC3119, + PMC3120, PMC3121, PMC3122, PMC3123, PMC3124, PMC3125, PMC3126, PMC3127, PMC3128, PMC3129, + PMC3130, PMC3131, PMC3132, PMC3133, PMC3134, PMC3135, PMC3136, PMC3137, PMC3138, PMC3139, + PMC3140, PMC3141, PMC3142, PMC3143, PMC3144, PMC3145, PMC3146, PMC3147, PMC3148, PMC3149, + PMC3150, PMC3151, PMC3152, PMC3153, PMC3154, PMC3155, PMC3156, PMC3157, PMC3158, PMC3159, + PMC3160, PMC3161, PMC3162, PMC3163, PMC3164, PMC3165, PMC3166, PMC3167, PMC3168, PMC3169, + PMC3170, PMC3171, PMC3172, PMC3173, PMC3174, PMC3175, PMC3176, PMC3177, PMC3178, PMC3179, + PMC3180, PMC3181, PMC3182, PMC3183, PMC3184, PMC3185, PMC3186, PMC3187, PMC3188, PMC3189, + PMC3190, PMC3191, PMC3192, PMC3193, PMC3194, PMC3195, PMC3196, PMC3197, PMC3198, PMC3199, + PMC3200, PMC3201, PMC3202, PMC3203, PMC3204, PMC3205, PMC3206, PMC3207, PMC3208, PMC3209, + PMC3210, PMC3211, PMC3212, PMC3213, PMC3214, PMC3215, PMC3216, PMC3217, PMC3218, PMC3219, + PMC3220, PMC3221, PMC3222, PMC3223, PMC3224, PMC3225, PMC3226, PMC3227, PMC3228, PMC3229, + PMC3230, PMC3231, PMC3232, PMC3233, PMC3234, PMC3235, PMC3236, PMC3237, PMC3238, PMC3239, + PMC3240, PMC3241, PMC3242, PMC3243, PMC3244, PMC3245, PMC3246, PMC3247, PMC3248, PMC3249, + PMC3250, PMC3251, PMC3252, PMC3253, PMC3254, PMC3255, PMC3256, PMC3257, PMC3258, PMC3259, + PMC3260, PMC3261, PMC3262, PMC3263, PMC3264, PMC3265, PMC3266, PMC3267, PMC3268, PMC3269, + PMC3270, PMC3271, PMC3272, PMC3273, PMC3274, PMC3275, PMC3276, PMC3277, PMC3278, PMC3279, + PMC3280, PMC3281, PMC3282, PMC3283, PMC3284, PMC3285, PMC3286, PMC3287, PMC3288, PMC3289, + PMC3290, PMC3291, PMC3292, PMC3293, PMC3294, PMC3295, PMC3296, PMC3297, PMC3298, PMC3299, + PMC3300, PMC3301, PMC3302, PMC3303, PMC3304, PMC3305, PMC3306, PMC3307, PMC3308, PMC3309, + PMC3310, PMC3311, PMC3312, PMC3313, PMC3314, PMC3315, PMC3316, PMC3317, PMC3318, PMC3319, + PMC3320, PMC3321, PMC3322, PMC3323, PMC3324, PMC3325, PMC3326, PMC3327, PMC3328, PMC3329, + PMC3330, PMC3331, PMC3332, PMC3333, PMC3334, PMC3335, PMC3336, PMC3337, PMC3338, PMC3339, + PMC3340, PMC3341, PMC3342, PMC3343, PMC3344, PMC3345, PMC3346, PMC3347, PMC3348, PMC3349, + PMC3350, PMC3351, PMC3352, PMC3353, PMC3354, PMC3355, PMC3356, PMC3357, PMC3358, PMC3359, + PMC3360, PMC3361, PMC3362, PMC3363, PMC3364, PMC3365, PMC3366, PMC3367, PMC3368, PMC3369, + PMC3370, PMC3371, PMC3372, PMC3373, PMC3374, PMC3375, PMC3376, PMC3377, PMC3378, PMC3379, + PMC3380, PMC3381, PMC3382, PMC3383, PMC3384, PMC3385, PMC3386, PMC3387, PMC3388, PMC3389, + PMC3390, PMC3391, PMC3392, PMC3393, PMC3394, PMC3395, PMC3396, PMC3397, PMC3398, PMC3399, + PMC3400, PMC3401, PMC3402, PMC3403, PMC3404, PMC3405, PMC3406, PMC3407, PMC3408, PMC3409, + PMC3410, PMC3411, PMC3412, PMC3413, PMC3414, PMC3415, PMC3416, PMC3417, PMC3418, PMC3419, + PMC3420, PMC3421, PMC3422, PMC3423, PMC3424, PMC3425, PMC3426, PMC3427, PMC3428, PMC3429, + PMC3430, PMC3431, PMC3432, PMC3433, PMC3434, PMC3435, PMC3436, PMC3437, PMC3438, PMC3439, + PMC3440, PMC3441, PMC3442, PMC3443, PMC3444, PMC3445, PMC3446, PMC3447, PMC3448, PMC3449, + PMC3450, PMC3451, PMC3452, PMC3453, PMC3454, PMC3455, PMC3456, PMC3457, PMC3458, PMC3459, + PMC3460, PMC3461, PMC3462, PMC3463, PMC3464, PMC3465, PMC3466, PMC3467, PMC3468, PMC3469, + PMC3470, PMC3471, PMC3472, PMC3473, PMC3474, PMC3475, PMC3476, PMC3477, PMC3478, PMC3479, + PMC3480, PMC3481, PMC3482, PMC3483, PMC3484, PMC3485, PMC3486, PMC3487, PMC3488, PMC3489, + PMC3490, PMC3491, PMC3492, PMC3493, PMC3494, PMC3495, PMC3496, PMC3497, PMC3498, PMC3499, + PMC3500, PMC3501, PMC3502, PMC3503, PMC3504, PMC3505, PMC3506, PMC3507, PMC3508, PMC3509, + PMC3510, PMC3511, PMC3512, PMC3513, PMC3514, PMC3515, PMC3516, PMC3517, PMC3518, PMC3519, + PMC3520, PMC3521, PMC3522, PMC3523, PMC3524, PMC3525, PMC3526, PMC3527, PMC3528, PMC3529, + PMC3530, PMC3531, PMC3532, PMC3533, PMC3534, PMC3535, PMC3536, PMC3537, PMC3538, PMC3539, + PMC3540, PMC3541, PMC3542, PMC3543, PMC3544, PMC3545, PMC3546, PMC3547, PMC3548, PMC3549, + PMC3550, PMC3551, PMC3552, PMC3553, PMC3554, PMC3555, PMC3556, PMC3557, PMC3558, PMC3559, + PMC3560, PMC3561, PMC3562, PMC3563, PMC3564, PMC3565, PMC3566, PMC3567, PMC3568, PMC3569, + PMC3570, PMC3571, PMC3572, PMC3573, PMC3574, PMC3575, PMC3576, PMC3577, PMC3578, PMC3579, + PMC3580, PMC3581, PMC3582, PMC3583, PMC3584, PMC3585, PMC3586, PMC3587, PMC3588, PMC3589, + PMC3590, PMC3591, PMC3592, PMC3593, PMC3594, PMC3595, PMC3596, PMC3597, PMC3598, PMC3599, + PMC3600, PMC3601, PMC3602, PMC3603, PMC3604, PMC3605, PMC3606, PMC3607, PMC3608, PMC3609, + PMC3610, PMC3611, PMC3612, PMC3613, PMC3614, PMC3615, PMC3616, PMC3617, PMC3618, PMC3619, + PMC3620, PMC3621, PMC3622, PMC3623, PMC3624, PMC3625, PMC3626, PMC3627, PMC3628, PMC3629, + PMC3630, PMC3631, PMC3632, PMC3633, PMC3634, PMC3635, PMC3636, PMC3637, PMC3638, PMC3639, + PMC3640, PMC3641, PMC3642, PMC3643, PMC3644, PMC3645, PMC3646, PMC3647, PMC3648, PMC3649, + PMC3650, PMC3651, PMC3652, PMC3653, PMC3654, PMC3655, PMC3656, PMC3657, PMC3658, PMC3659, + PMC3660, PMC3661, PMC3662, PMC3663, PMC3664, PMC3665, PMC3666, PMC3667, PMC3668, PMC3669, + PMC3670, PMC3671, PMC3672, PMC3673, PMC3674, PMC3675, PMC3676, PMC3677, PMC3678, PMC3679, + PMC3680, PMC3681, PMC3682, PMC3683, PMC3684, PMC3685, PMC3686, PMC3687, PMC3688, PMC3689, + PMC3690, PMC3691, PMC3692, PMC3693, PMC3694, PMC3695, PMC3696, PMC3697, PMC3698, PMC3699, + PMC3700, PMC3701, PMC3702, PMC3703, PMC3704, PMC3705, PMC3706, PMC3707, PMC3708, PMC3709, + PMC3710, PMC3711, PMC3712, PMC3713, PMC3714, PMC3715, PMC3716, PMC3717, PMC3718, PMC3719, + PMC3720, PMC3721, PMC3722, PMC3723, PMC3724, PMC3725, PMC3726, PMC3727, PMC3728, PMC3729, + PMC3730, PMC3731, PMC3732, PMC3733, PMC3734, PMC3735, PMC3736, PMC3737, PMC3738, PMC3739, + PMC3740, PMC3741, PMC3742, PMC3743, PMC3744, PMC3745, PMC3746, PMC3747, PMC3748, PMC3749, + PMC3750, PMC3751, PMC3752, PMC3753, PMC3754, PMC3755, PMC3756, PMC3757, PMC3758, PMC3759, + PMC3760, PMC3761, PMC3762, PMC3763, PMC3764, PMC3765, PMC3766, PMC3767, PMC3768, PMC3769, + PMC3770, PMC3771, PMC3772, PMC3773, PMC3774, PMC3775, PMC3776, PMC3777, PMC3778, PMC3779, + PMC3780, PMC3781, PMC3782, PMC3783, PMC3784, PMC3785, PMC3786, PMC3787, PMC3788, PMC3789, + PMC3790, PMC3791, PMC3792, PMC3793, PMC3794, PMC3795, PMC3796, PMC3797, PMC3798, PMC3799, + PMC3800, PMC3801, PMC3802, PMC3803, PMC3804, PMC3805, PMC3806, PMC3807, PMC3808, PMC3809, + PMC3810, PMC3811, PMC3812, PMC3813, PMC3814, PMC3815, PMC3816, PMC3817, PMC3818, PMC3819, + PMC3820, PMC3821, PMC3822, PMC3823, PMC3824, PMC3825, PMC3826, PMC3827, PMC3828, PMC3829, + PMC3830, PMC3831, PMC3832, PMC3833, PMC3834, PMC3835, PMC3836, PMC3837, PMC3838, PMC3839, + PMC3840, PMC3841, PMC3842, PMC3843, PMC3844, PMC3845, PMC3846, PMC3847, PMC3848, PMC3849, + PMC3850, PMC3851, PMC3852, PMC3853, PMC3854, PMC3855, PMC3856, PMC3857, PMC3858, PMC3859, + PMC3860, PMC3861, PMC3862, PMC3863, PMC3864, PMC3865, PMC3866, PMC3867, PMC3868, PMC3869, + PMC3870, PMC3871, PMC3872, PMC3873, PMC3874, PMC3875, PMC3876, PMC3877, PMC3878, PMC3879, + PMC3880, PMC3881, PMC3882, PMC3883, PMC3884, PMC3885, PMC3886, PMC3887, PMC3888, PMC3889, + PMC3890, PMC3891, PMC3892, PMC3893, PMC3894, PMC3895, PMC3896, PMC3897, PMC3898, PMC3899, + PMC3900, PMC3901, PMC3902, PMC3903, PMC3904, PMC3905, PMC3906, PMC3907, PMC3908, PMC3909, + PMC3910, PMC3911, PMC3912, PMC3913, PMC3914, PMC3915, PMC3916, PMC3917, PMC3918, PMC3919, + PMC3920, PMC3921, PMC3922, PMC3923, PMC3924, PMC3925, PMC3926, PMC3927, PMC3928, PMC3929, + PMC3930, PMC3931, PMC3932, PMC3933, PMC3934, PMC3935, PMC3936, PMC3937, PMC3938, PMC3939, + PMC3940, PMC3941, PMC3942, PMC3943, PMC3944, PMC3945, PMC3946, PMC3947, PMC3948, PMC3949, + PMC3950, PMC3951, PMC3952, PMC3953, PMC3954, PMC3955, PMC3956, PMC3957, PMC3958, PMC3959, + PMC3960, PMC3961, PMC3962, PMC3963, PMC3964, PMC3965, PMC3966, PMC3967, PMC3968, PMC3969, + PMC3970, PMC3971, PMC3972, PMC3973, PMC3974, PMC3975, PMC3976, PMC3977, PMC3978, PMC3979, + PMC3980, PMC3981, PMC3982, PMC3983, PMC3984, PMC3985, PMC3986, PMC3987, PMC3988, PMC3989, + PMC3990, PMC3991, PMC3992, PMC3993, PMC3994, PMC3995, PMC3996, PMC3997, PMC3998, PMC3999, + PMC4000, PMC4001, PMC4002, PMC4003, PMC4004, PMC4005, PMC4006, PMC4007, PMC4008, PMC4009, + PMC4010, PMC4011, PMC4012, PMC4013, PMC4014, PMC4015, PMC4016, PMC4017, PMC4018, PMC4019, + PMC4020, PMC4021, PMC4022, PMC4023, PMC4024, PMC4025, PMC4026, PMC4027, PMC4028, PMC4029, + PMC4030, PMC4031, PMC4032, PMC4033, PMC4034, PMC4035, PMC4036, PMC4037, PMC4038, PMC4039, + PMC4040, PMC4041, PMC4042, PMC4043, PMC4044, PMC4045, PMC4046, PMC4047, PMC4048, PMC4049, + PMC4050, PMC4051, PMC4052, PMC4053, PMC4054, PMC4055, PMC4056, PMC4057, PMC4058, PMC4059, + PMC4060, PMC4061, PMC4062, PMC4063, PMC4064, PMC4065, PMC4066, PMC4067, PMC4068, PMC4069, + PMC4070, PMC4071, PMC4072, PMC4073, PMC4074, PMC4075, PMC4076, PMC4077, PMC4078, PMC4079, + PMC4080, PMC4081, PMC4082, PMC4083, PMC4084, PMC4085, PMC4086, PMC4087, PMC4088, PMC4089, + PMC4090, PMC4091, PMC4092, PMC4093, PMC4094, PMC4095, PMC4096, PMC4097, PMC4098, PMC4099, + PMC4100, PMC4101, PMC4102, PMC4103, PMC4104, PMC4105, PMC4106, PMC4107, PMC4108, PMC4109, + PMC4110, PMC4111, PMC4112, PMC4113, PMC4114, PMC4115, PMC4116, PMC4117, PMC4118, PMC4119, + PMC4120, PMC4121, PMC4122, PMC4123, PMC4124, PMC4125, PMC4126, PMC4127, PMC4128, PMC4129, + PMC4130, PMC4131, PMC4132, PMC4133, PMC4134, PMC4135, PMC4136, PMC4137, PMC4138, PMC4139, + PMC4140, PMC4141, PMC4142, PMC4143, PMC4144, PMC4145, PMC4146, PMC4147, PMC4148, PMC4149, + PMC4150, PMC4151, PMC4152, PMC4153, PMC4154, PMC4155, PMC4156, PMC4157, PMC4158, PMC4159, + PMC4160, PMC4161, PMC4162, PMC4163, PMC4164, PMC4165, PMC4166, PMC4167, PMC4168, PMC4169, + PMC4170, PMC4171, PMC4172, PMC4173, PMC4174, PMC4175, PMC4176, PMC4177, PMC4178, PMC4179, + PMC4180, PMC4181, PMC4182, PMC4183, PMC4184, PMC4185, PMC4186, PMC4187, PMC4188, PMC4189, + PMC4190, PMC4191, PMC4192, PMC4193, PMC4194, PMC4195, PMC4196, PMC4197, PMC4198, PMC4199, + PMC4200, PMC4201, PMC4202, PMC4203, PMC4204, PMC4205, PMC4206, PMC4207, PMC4208, PMC4209, + PMC4210, PMC4211, PMC4212, PMC4213, PMC4214, PMC4215, PMC4216, PMC4217, PMC4218, PMC4219, + PMC4220, PMC4221, PMC4222, PMC4223, PMC4224, PMC4225, PMC4226, PMC4227, PMC4228, PMC4229, + PMC4230, PMC4231, PMC4232, PMC4233, PMC4234, PMC4235, PMC4236, PMC4237, PMC4238, PMC4239, + PMC4240, PMC4241, PMC4242, PMC4243, PMC4244, PMC4245, PMC4246, PMC4247, PMC4248, PMC4249, + PMC4250, PMC4251, PMC4252, PMC4253, PMC4254, PMC4255, PMC4256, PMC4257, PMC4258, PMC4259, + PMC4260, PMC4261, PMC4262, PMC4263, PMC4264, PMC4265, PMC4266, PMC4267, PMC4268, PMC4269, + PMC4270, PMC4271, PMC4272, PMC4273, PMC4274, PMC4275, PMC4276, PMC4277, PMC4278, PMC4279, + PMC4280, PMC4281, PMC4282, PMC4283, PMC4284, PMC4285, PMC4286, PMC4287, PMC4288, PMC4289, + PMC4290, PMC4291, PMC4292, PMC4293, PMC4294, PMC4295, PMC4296, PMC4297, PMC4298, PMC4299, + PMC4300, PMC4301, PMC4302, PMC4303, PMC4304, PMC4305, PMC4306, PMC4307, PMC4308, PMC4309, + PMC4310, PMC4311, PMC4312, PMC4313, PMC4314, PMC4315, PMC4316, PMC4317, PMC4318, PMC4319, + PMC4320, PMC4321, PMC4322, PMC4323, PMC4324, PMC4325, PMC4326, PMC4327, PMC4328, PMC4329, + PMC4330, PMC4331, PMC4332, PMC4333, PMC4334, PMC4335, PMC4336, PMC4337, PMC4338, PMC4339, + PMC4340, PMC4341, PMC4342, PMC4343, PMC4344, PMC4345, PMC4346, PMC4347, PMC4348, PMC4349, + PMC4350, PMC4351, PMC4352, PMC4353, PMC4354, PMC4355, PMC4356, PMC4357, PMC4358, PMC4359, + PMC4360, PMC4361, PMC4362, PMC4363, PMC4364, PMC4365, PMC4366, PMC4367, PMC4368, PMC4369, + PMC4370, PMC4371, PMC4372, PMC4373, PMC4374, PMC4375, PMC4376, PMC4377, PMC4378, PMC4379, + PMC4380, PMC4381, PMC4382, PMC4383, PMC4384, PMC4385, PMC4386, PMC4387, PMC4388, PMC4389, + PMC4390, PMC4391, PMC4392, PMC4393, PMC4394, PMC4395, PMC4396, PMC4397, PMC4398, PMC4399, + PMC4400, PMC4401, PMC4402, PMC4403, PMC4404, PMC4405, PMC4406, PMC4407, PMC4408, PMC4409, + PMC4410, PMC4411, PMC4412, PMC4413, PMC4414, PMC4415, PMC4416, PMC4417, PMC4418, PMC4419, + PMC4420, PMC4421, PMC4422, PMC4423, PMC4424, PMC4425, PMC4426, PMC4427, PMC4428, PMC4429, + PMC4430, PMC4431, PMC4432, PMC4433, PMC4434, PMC4435, PMC4436, PMC4437, PMC4438, PMC4439, + PMC4440, PMC4441, PMC4442, PMC4443, PMC4444, PMC4445, PMC4446, PMC4447, PMC4448, PMC4449, + PMC4450, PMC4451, PMC4452, PMC4453, PMC4454, PMC4455, PMC4456, PMC4457, PMC4458, PMC4459, + PMC4460, PMC4461, PMC4462, PMC4463, PMC4464, PMC4465, PMC4466, PMC4467, PMC4468, PMC4469, + PMC4470, PMC4471, PMC4472, PMC4473, PMC4474, PMC4475, PMC4476, PMC4477, PMC4478, PMC4479, + PMC4480, PMC4481, PMC4482, PMC4483, PMC4484, PMC4485, PMC4486, PMC4487, PMC4488, PMC4489, + PMC4490, PMC4491, PMC4492, PMC4493, PMC4494, PMC4495, PMC4496, PMC4497, PMC4498, PMC4499, + PMC4500, PMC4501, PMC4502, PMC4503, PMC4504, PMC4505, PMC4506, PMC4507, PMC4508, PMC4509, + PMC4510, PMC4511, PMC4512, PMC4513, PMC4514, PMC4515, PMC4516, PMC4517, PMC4518, PMC4519, + PMC4520, PMC4521, PMC4522, PMC4523, PMC4524, PMC4525, PMC4526, PMC4527, PMC4528, PMC4529, + PMC4530, PMC4531, PMC4532, PMC4533, PMC4534, PMC4535, PMC4536, PMC4537, PMC4538, PMC4539, + PMC4540, PMC4541, PMC4542, PMC4543, PMC4544, PMC4545, PMC4546, PMC4547, PMC4548, PMC4549, + PMC4550, PMC4551, PMC4552, PMC4553, PMC4554, PMC4555, PMC4556, PMC4557, PMC4558, PMC4559, + PMC4560, PMC4561, PMC4562, PMC4563, PMC4564, PMC4565, PMC4566, PMC4567, PMC4568, PMC4569, + PMC4570, PMC4571, PMC4572, PMC4573, PMC4574, PMC4575, PMC4576, PMC4577, PMC4578, PMC4579, + PMC4580, PMC4581, PMC4582, PMC4583, PMC4584, PMC4585, PMC4586, PMC4587, PMC4588, PMC4589, + PMC4590, PMC4591, PMC4592, PMC4593, PMC4594, PMC4595, PMC4596, PMC4597, PMC4598, PMC4599, + PMC4600, PMC4601, PMC4602, PMC4603, PMC4604, PMC4605, PMC4606, PMC4607, PMC4608, PMC4609, + PMC4610, PMC4611, PMC4612, PMC4613, PMC4614, PMC4615, PMC4616, PMC4617, PMC4618, PMC4619, + PMC4620, PMC4621, PMC4622, PMC4623, PMC4624, PMC4625, PMC4626, PMC4627, PMC4628, PMC4629, + PMC4630, PMC4631, PMC4632, PMC4633, PMC4634, PMC4635, PMC4636, PMC4637, PMC4638, PMC4639, + PMC4640, PMC4641, PMC4642, PMC4643, PMC4644, PMC4645, PMC4646, PMC4647, PMC4648, PMC4649, + PMC4650, PMC4651, PMC4652, PMC4653, PMC4654, PMC4655, PMC4656, PMC4657, PMC4658, PMC4659, + PMC4660, PMC4661, PMC4662, PMC4663, PMC4664, PMC4665, PMC4666, PMC4667, PMC4668, PMC4669, + PMC4670, PMC4671, PMC4672, PMC4673, PMC4674, PMC4675, PMC4676, PMC4677, PMC4678, PMC4679, + PMC4680, PMC4681, PMC4682, PMC4683, PMC4684, PMC4685, PMC4686, PMC4687, PMC4688, PMC4689, + PMC4690, PMC4691, PMC4692, PMC4693, PMC4694, PMC4695, PMC4696, PMC4697, PMC4698, PMC4699, + PMC4700, PMC4701, PMC4702, PMC4703, PMC4704, PMC4705, PMC4706, PMC4707, PMC4708, PMC4709, + PMC4710, PMC4711, PMC4712, PMC4713, PMC4714, PMC4715, PMC4716, PMC4717, PMC4718, PMC4719, + PMC4720, PMC4721, PMC4722, PMC4723, PMC4724, PMC4725, PMC4726, PMC4727, PMC4728, PMC4729, + PMC4730, PMC4731, PMC4732, PMC4733, PMC4734, PMC4735, PMC4736, PMC4737, PMC4738, PMC4739, + PMC4740, PMC4741, PMC4742, PMC4743, PMC4744, PMC4745, PMC4746, PMC4747, PMC4748, PMC4749, + PMC4750, PMC4751, PMC4752, PMC4753, PMC4754, PMC4755, PMC4756, PMC4757, PMC4758, PMC4759, + PMC4760, PMC4761, PMC4762, PMC4763, PMC4764, PMC4765, PMC4766, PMC4767, PMC4768, PMC4769, + PMC4770, PMC4771, PMC4772, PMC4773, PMC4774, PMC4775, PMC4776, PMC4777, PMC4778, PMC4779, + PMC4780, PMC4781, PMC4782, PMC4783, PMC4784, PMC4785, PMC4786, PMC4787, PMC4788, PMC4789, + PMC4790, PMC4791, PMC4792, PMC4793, PMC4794, PMC4795, PMC4796, PMC4797, PMC4798, PMC4799, + PMC4800, PMC4801, PMC4802, PMC4803, PMC4804, PMC4805, PMC4806, PMC4807, PMC4808, PMC4809, + PMC4810, PMC4811, PMC4812, PMC4813, PMC4814, PMC4815, PMC4816, PMC4817, PMC4818, PMC4819, + PMC4820, PMC4821, PMC4822, PMC4823, PMC4824, PMC4825, PMC4826, PMC4827, PMC4828, PMC4829, + PMC4830, PMC4831, PMC4832, PMC4833, PMC4834, PMC4835, PMC4836, PMC4837, PMC4838, PMC4839, + PMC4840, PMC4841, PMC4842, PMC4843, PMC4844, PMC4845, PMC4846, PMC4847, PMC4848, PMC4849, + PMC4850, PMC4851, PMC4852, PMC4853, PMC4854, PMC4855, PMC4856, PMC4857, PMC4858, PMC4859, + PMC4860, PMC4861, PMC4862, PMC4863, PMC4864, PMC4865, PMC4866, PMC4867, PMC4868, PMC4869, + PMC4870, PMC4871, PMC4872, PMC4873, PMC4874, PMC4875, PMC4876, PMC4877, PMC4878, PMC4879, + PMC4880, PMC4881, PMC4882, PMC4883, PMC4884, PMC4885, PMC4886, PMC4887, PMC4888, PMC4889, + PMC4890, PMC4891, PMC4892, PMC4893, PMC4894, PMC4895, PMC4896, PMC4897, PMC4898, PMC4899, + PMC4900, PMC4901, PMC4902, PMC4903, PMC4904, PMC4905, PMC4906, PMC4907, PMC4908, PMC4909, + PMC4910, PMC4911, PMC4912, PMC4913, PMC4914, PMC4915, PMC4916, PMC4917, PMC4918, PMC4919, + PMC4920, PMC4921, PMC4922, PMC4923, PMC4924, PMC4925, PMC4926, PMC4927, PMC4928, PMC4929, + PMC4930, PMC4931, PMC4932, PMC4933, PMC4934, PMC4935, PMC4936, PMC4937, PMC4938, PMC4939, + PMC4940, PMC4941, PMC4942, PMC4943, PMC4944, PMC4945, PMC4946, PMC4947, PMC4948, PMC4949, + PMC4950, PMC4951, PMC4952, PMC4953, PMC4954, PMC4955, PMC4956, PMC4957, PMC4958, PMC4959, + PMC4960, PMC4961, PMC4962, PMC4963, PMC4964, PMC4965, PMC4966, PMC4967, PMC4968, PMC4969, + PMC4970, PMC4971, PMC4972, PMC4973, PMC4974, PMC4975, PMC4976, PMC4977, PMC4978, PMC4979, + PMC4980, PMC4981, PMC4982, PMC4983, PMC4984, PMC4985, PMC4986, PMC4987, PMC4988, PMC4989, + PMC4990, PMC4991, PMC4992, PMC4993, PMC4994, PMC4995, PMC4996, PMC4997, PMC4998, PMC4999, + PMC5000, PMC5001, PMC5002, PMC5003, PMC5004, PMC5005, PMC5006, PMC5007, PMC5008, PMC5009, + PMC5010, PMC5011, PMC5012, PMC5013, PMC5014, PMC5015, PMC5016, PMC5017, PMC5018, PMC5019, + PMC5020, PMC5021, PMC5022, PMC5023, PMC5024, PMC5025, PMC5026, PMC5027, PMC5028, PMC5029, + PMC5030, PMC5031, PMC5032, PMC5033, PMC5034, PMC5035, PMC5036, PMC5037, PMC5038, PMC5039, + PMC5040, PMC5041, PMC5042, PMC5043, PMC5044, PMC5045, PMC5046, PMC5047, PMC5048, PMC5049, + PMC5050, PMC5051, PMC5052, PMC5053, PMC5054, PMC5055, PMC5056, PMC5057, PMC5058, PMC5059, + PMC5060, PMC5061, PMC5062, PMC5063, PMC5064, PMC5065, PMC5066, PMC5067, PMC5068, PMC5069, + PMC5070, PMC5071, PMC5072, PMC5073, PMC5074, PMC5075, PMC5076, PMC5077, PMC5078, PMC5079, + PMC5080, PMC5081, PMC5082, PMC5083, PMC5084, PMC5085, PMC5086, PMC5087, PMC5088, PMC5089, + PMC5090, PMC5091, PMC5092, PMC5093, PMC5094, PMC5095, PMC5096, PMC5097, PMC5098, PMC5099, + PMC5100, PMC5101, PMC5102, PMC5103, PMC5104, PMC5105, PMC5106, PMC5107, PMC5108, PMC5109, + PMC5110, PMC5111, PMC5112, PMC5113, PMC5114, PMC5115, PMC5116, PMC5117, PMC5118, PMC5119, + PMC5120, PMC5121, PMC5122, PMC5123, PMC5124, PMC5125, PMC5126, PMC5127, PMC5128, PMC5129, + PMC5130, PMC5131, PMC5132, PMC5133, PMC5134, PMC5135, PMC5136, PMC5137, PMC5138, PMC5139, + PMC5140, PMC5141, PMC5142, PMC5143, PMC5144, PMC5145, PMC5146, PMC5147, PMC5148, PMC5149, + PMC5150, PMC5151, PMC5152, PMC5153, PMC5154, PMC5155, PMC5156, PMC5157, PMC5158, PMC5159, + PMC5160, PMC5161, PMC5162, PMC5163, PMC5164, PMC5165, PMC5166, PMC5167, PMC5168, PMC5169, + PMC5170, PMC5171, PMC5172, PMC5173, PMC5174, PMC5175, PMC5176, PMC5177, PMC5178, PMC5179, + PMC5180, PMC5181, PMC5182, PMC5183, PMC5184, PMC5185, PMC5186, PMC5187, PMC5188, PMC5189, + PMC5190, PMC5191, PMC5192, PMC5193, PMC5194, PMC5195, PMC5196, PMC5197, PMC5198, PMC5199, + PMC5200, PMC5201, PMC5202, PMC5203, PMC5204, PMC5205, PMC5206, PMC5207, PMC5208, PMC5209, + PMC5210, PMC5211, PMC5212, PMC5213, PMC5214, PMC5215, PMC5216, PMC5217, PMC5218, PMC5219, + PMC5220, PMC5221, PMC5222, PMC5223, PMC5224, PMC5225, PMC5226, PMC5227, PMC5228, PMC5229, + PMC5230, PMC5231, PMC5232, PMC5233, PMC5234, PMC5235, PMC5236, PMC5237, PMC5238, PMC5239, + PMC5240, PMC5241, PMC5242, PMC5243, PMC5244, PMC5245, PMC5246, PMC5247, PMC5248, PMC5249, + PMC5250, PMC5251, PMC5252, PMC5253, PMC5254, PMC5255, PMC5256, PMC5257, PMC5258, PMC5259, + PMC5260, PMC5261, PMC5262, PMC5263, PMC5264, PMC5265, PMC5266, PMC5267, PMC5268, PMC5269, + PMC5270, PMC5271, PMC5272, PMC5273, PMC5274, PMC5275, PMC5276, PMC5277, PMC5278, PMC5279, + PMC5280, PMC5281, PMC5282, PMC5283, PMC5284, PMC5285, PMC5286, PMC5287, PMC5288, PMC5289, + PMC5290, PMC5291, PMC5292, PMC5293, PMC5294, PMC5295, PMC5296, PMC5297, PMC5298, PMC5299, + PMC5300, PMC5301, PMC5302, PMC5303, PMC5304, PMC5305, PMC5306, PMC5307, PMC5308, PMC5309, + PMC5310, PMC5311, PMC5312, PMC5313, PMC5314, PMC5315, PMC5316, PMC5317, PMC5318, PMC5319, + PMC5320, PMC5321, PMC5322, PMC5323, PMC5324, PMC5325, PMC5326, PMC5327, PMC5328, PMC5329, + PMC5330, PMC5331, PMC5332, PMC5333, PMC5334, PMC5335, PMC5336, PMC5337, PMC5338, PMC5339, + PMC5340, PMC5341, PMC5342, PMC5343, PMC5344, PMC5345, PMC5346, PMC5347, PMC5348, PMC5349, + PMC5350, PMC5351, PMC5352, PMC5353, PMC5354, PMC5355, PMC5356, PMC5357, PMC5358, PMC5359, + PMC5360, PMC5361, PMC5362, PMC5363, PMC5364, PMC5365, PMC5366, PMC5367, PMC5368, PMC5369, + PMC5370, PMC5371, PMC5372, PMC5373, PMC5374, PMC5375, PMC5376, PMC5377, PMC5378, PMC5379, + PMC5380, PMC5381, PMC5382, PMC5383, PMC5384, PMC5385, PMC5386, PMC5387, PMC5388, PMC5389, + PMC5390, PMC5391, PMC5392, PMC5393, PMC5394, PMC5395, PMC5396, PMC5397, PMC5398, PMC5399, + PMC5400, PMC5401, PMC5402, PMC5403, PMC5404, PMC5405, PMC5406, PMC5407, PMC5408, PMC5409, + PMC5410, PMC5411, PMC5412, PMC5413, PMC5414, PMC5415, PMC5416, PMC5417, PMC5418, PMC5419, + PMC5420, PMC5421, PMC5422, PMC5423, PMC5424, PMC5425, PMC5426, PMC5427, PMC5428, PMC5429, + PMC5430, PMC5431, PMC5432, PMC5433, PMC5434, PMC5435, PMC5436, PMC5437, PMC5438, PMC5439, + PMC5440, PMC5441, PMC5442, PMC5443, PMC5444, PMC5445, PMC5446, PMC5447, PMC5448, PMC5449, + PMC5450, PMC5451, PMC5452, PMC5453, PMC5454, PMC5455, PMC5456, PMC5457, PMC5458, PMC5459, + PMC5460, PMC5461, PMC5462, PMC5463, PMC5464, PMC5465, PMC5466, PMC5467, PMC5468, PMC5469, + PMC5470, PMC5471, PMC5472, PMC5473, PMC5474, PMC5475, PMC5476, PMC5477, PMC5478, PMC5479, + PMC5480, PMC5481, PMC5482, PMC5483, PMC5484, PMC5485, PMC5486, PMC5487, PMC5488, PMC5489, + PMC5490, PMC5491, PMC5492, PMC5493, PMC5494, PMC5495, PMC5496, PMC5497, PMC5498, PMC5499, + PMC5500, PMC5501, PMC5502, PMC5503, PMC5504, PMC5505, PMC5506, PMC5507, PMC5508, PMC5509, + PMC5510, PMC5511, PMC5512, PMC5513, PMC5514, PMC5515, PMC5516, PMC5517, PMC5518, PMC5519, + PMC5520, PMC5521, PMC5522, PMC5523, PMC5524, PMC5525, PMC5526, PMC5527, PMC5528, PMC5529, + PMC5530, PMC5531, PMC5532, PMC5533, PMC5534, PMC5535, PMC5536, PMC5537, PMC5538, PMC5539, + PMC5540, PMC5541, PMC5542, PMC5543, PMC5544, PMC5545, PMC5546, PMC5547, PMC5548, PMC5549, + PMC5550, PMC5551, PMC5552, PMC5553, PMC5554, PMC5555, PMC5556, PMC5557, PMC5558, PMC5559, + PMC5560, PMC5561, PMC5562, PMC5563, PMC5564, PMC5565, PMC5566, PMC5567, PMC5568, PMC5569, + PMC5570, PMC5571, PMC5572, PMC5573, PMC5574, PMC5575, PMC5576, PMC5577, PMC5578, PMC5579, + PMC5580, PMC5581, PMC5582, PMC5583, PMC5584, PMC5585, PMC5586, PMC5587, PMC5588, PMC5589, + PMC5590, PMC5591, PMC5592, PMC5593, PMC5594, PMC5595, PMC5596, PMC5597, PMC5598, PMC5599, + PMC5600, PMC5601, PMC5602, PMC5603, PMC5604, PMC5605, PMC5606, PMC5607, PMC5608, PMC5609, + PMC5610, PMC5611, PMC5612, PMC5613, PMC5614, PMC5615, PMC5616, PMC5617, PMC5618, PMC5619, + PMC5620, PMC5621, PMC5622, PMC5623, PMC5624, PMC5625, PMC5626, PMC5627, PMC5628, PMC5629, + PMC5630, PMC5631, PMC5632, PMC5633, PMC5634, PMC5635, PMC5636, PMC5637, PMC5638, PMC5639, + PMC5640, PMC5641, PMC5642, PMC5643, PMC5644, PMC5645, PMC5646, PMC5647, PMC5648, PMC5649, + PMC5650, PMC5651, PMC5652, PMC5653, PMC5654, PMC5655, PMC5656, PMC5657, PMC5658, PMC5659, + PMC5660, PMC5661, PMC5662, PMC5663, PMC5664, PMC5665, PMC5666, PMC5667, PMC5668, PMC5669, + PMC5670, PMC5671, PMC5672, PMC5673, PMC5674, PMC5675, PMC5676, PMC5677, PMC5678, PMC5679, + PMC5680, PMC5681, PMC5682, PMC5683, PMC5684, PMC5685, PMC5686, PMC5687, PMC5688, PMC5689, + PMC5690, PMC5691, PMC5692, PMC5693, PMC5694, PMC5695, PMC5696, PMC5697, PMC5698, PMC5699, + PMC5700, PMC5701, PMC5702, PMC5703, PMC5704, PMC5705, PMC5706, PMC5707, PMC5708, PMC5709, + PMC5710, PMC5711, PMC5712, PMC5713, PMC5714, PMC5715, PMC5716, PMC5717, PMC5718, PMC5719, + PMC5720, PMC5721, PMC5722, PMC5723, PMC5724, PMC5725, PMC5726, PMC5727, PMC5728, PMC5729, + PMC5730, PMC5731, PMC5732, PMC5733, PMC5734, PMC5735, PMC5736, PMC5737, PMC5738, PMC5739, + PMC5740, PMC5741, PMC5742, PMC5743, PMC5744, PMC5745, PMC5746, PMC5747, PMC5748, PMC5749, + PMC5750, PMC5751, PMC5752, PMC5753, PMC5754, PMC5755, PMC5756, PMC5757, PMC5758, PMC5759, + PMC5760, PMC5761, PMC5762, PMC5763, PMC5764, PMC5765, PMC5766, PMC5767, PMC5768, PMC5769, + PMC5770, PMC5771, PMC5772, PMC5773, PMC5774, PMC5775, PMC5776, PMC5777, PMC5778, PMC5779, + PMC5780, PMC5781, PMC5782, PMC5783, PMC5784, PMC5785, PMC5786, PMC5787, PMC5788, PMC5789, + PMC5790, PMC5791, PMC5792, PMC5793, PMC5794, PMC5795, PMC5796, PMC5797, PMC5798, PMC5799, + PMC5800, PMC5801, PMC5802, PMC5803, PMC5804, PMC5805, PMC5806, PMC5807, PMC5808, PMC5809, + PMC5810, PMC5811, PMC5812, PMC5813, PMC5814, PMC5815, PMC5816, PMC5817, PMC5818, PMC5819, + PMC5820, PMC5821, PMC5822, PMC5823, PMC5824, PMC5825, PMC5826, PMC5827, PMC5828, PMC5829, + PMC5830, PMC5831, PMC5832, PMC5833, PMC5834, PMC5835, PMC5836, PMC5837, PMC5838, PMC5839, + PMC5840, PMC5841, PMC5842, PMC5843, PMC5844, PMC5845, PMC5846, PMC5847, PMC5848, PMC5849, + PMC5850, PMC5851, PMC5852, PMC5853, PMC5854, PMC5855, PMC5856, PMC5857, PMC5858, PMC5859, + PMC5860, PMC5861, PMC5862, PMC5863, PMC5864, PMC5865, PMC5866, PMC5867, PMC5868, PMC5869, + PMC5870, PMC5871, PMC5872, PMC5873, PMC5874, PMC5875, PMC5876, PMC5877, PMC5878, PMC5879, + PMC5880, PMC5881, PMC5882, PMC5883, PMC5884, PMC5885, PMC5886, PMC5887, PMC5888, PMC5889, + PMC5890, PMC5891, PMC5892, PMC5893, PMC5894, PMC5895, PMC5896, PMC5897, PMC5898, PMC5899, + PMC5900, PMC5901, PMC5902, PMC5903, PMC5904, PMC5905, PMC5906, PMC5907, PMC5908, PMC5909, + PMC5910, PMC5911, PMC5912, PMC5913, PMC5914, PMC5915, PMC5916, PMC5917, PMC5918, PMC5919, + PMC5920, PMC5921, PMC5922, PMC5923, PMC5924, PMC5925, PMC5926, PMC5927, PMC5928, PMC5929, + PMC5930, PMC5931, PMC5932, PMC5933, PMC5934, PMC5935, PMC5936, PMC5937, PMC5938, PMC5939, + PMC5940, PMC5941, PMC5942, PMC5943, PMC5944, PMC5945, PMC5946, PMC5947, PMC5948, PMC5949, + PMC5950, PMC5951, PMC5952, PMC5953, PMC5954, PMC5955, PMC5956, PMC5957, PMC5958, PMC5959, + PMC5960, PMC5961, PMC5962, PMC5963, PMC5964, PMC5965, PMC5966, PMC5967, PMC5968, PMC5969, + PMC5970, PMC5971, PMC5972, PMC5973, PMC5974, PMC5975, PMC5976, PMC5977, PMC5978, PMC5979, + PMC5980, PMC5981, PMC5982, PMC5983, PMC5984, PMC5985, PMC5986, PMC5987, PMC5988, PMC5989, + PMC5990, PMC5991, PMC5992, PMC5993, PMC5994, PMC5995, PMC5996, PMC5997, PMC5998, PMC5999, + PMC6000, PMC6001, PMC6002, PMC6003, PMC6004, PMC6005, PMC6006, PMC6007, PMC6008, PMC6009, + PMC6010, PMC6011, PMC6012, PMC6013, PMC6014, PMC6015, PMC6016, PMC6017, PMC6018, PMC6019, + PMC6020, PMC6021, PMC6022, PMC6023, PMC6024, PMC6025, PMC6026, PMC6027, PMC6028, PMC6029, + PMC6030, PMC6031, PMC6032, PMC6033, PMC6034, PMC6035, PMC6036, PMC6037, PMC6038, PMC6039, + PMC6040, PMC6041, PMC6042, PMC6043, PMC6044, PMC6045, PMC6046, PMC6047, PMC6048, PMC6049, + PMC6050, PMC6051, PMC6052, PMC6053, PMC6054, PMC6055, PMC6056, PMC6057, PMC6058, PMC6059, + PMC6060, PMC6061, PMC6062, PMC6063, PMC6064, PMC6065, PMC6066, PMC6067, PMC6068, PMC6069, + PMC6070, PMC6071, PMC6072, PMC6073, PMC6074, PMC6075, PMC6076, PMC6077, PMC6078, PMC6079, + PMC6080, PMC6081, PMC6082, PMC6083, PMC6084, PMC6085, PMC6086, PMC6087, PMC6088, PMC6089, + PMC6090, PMC6091, PMC6092, PMC6093, PMC6094, PMC6095, PMC6096, PMC6097, PMC6098, PMC6099, + PMC6100, PMC6101, PMC6102, PMC6103, PMC6104, PMC6105, PMC6106, PMC6107, PMC6108, PMC6109, + PMC6110, PMC6111, PMC6112, PMC6113, PMC6114, PMC6115, PMC6116, PMC6117, PMC6118, PMC6119, + PMC6120, PMC6121, PMC6122, PMC6123, PMC6124, PMC6125, PMC6126, PMC6127, PMC6128, PMC6129, + PMC6130, PMC6131, PMC6132, PMC6133, PMC6134, PMC6135, PMC6136, PMC6137, PMC6138, PMC6139, + PMC6140, PMC6141, PMC6142, PMC6143, PMC6144, PMC6145, PMC6146, PMC6147, PMC6148, PMC6149, + PMC6150, PMC6151, PMC6152, PMC6153, PMC6154, PMC6155, PMC6156, PMC6157, PMC6158, PMC6159, + PMC6160, PMC6161, PMC6162, PMC6163, PMC6164, PMC6165, PMC6166, PMC6167, PMC6168, PMC6169, + PMC6170, PMC6171, PMC6172, PMC6173, PMC6174, PMC6175, PMC6176, PMC6177, PMC6178, PMC6179, + PMC6180, PMC6181, PMC6182, PMC6183, PMC6184, PMC6185, PMC6186, PMC6187, PMC6188, PMC6189, + PMC6190, PMC6191, PMC6192, PMC6193, PMC6194, PMC6195, PMC6196, PMC6197, PMC6198, PMC6199, + PMC6200, PMC6201, PMC6202, PMC6203, PMC6204, PMC6205, PMC6206, PMC6207, PMC6208, PMC6209, + PMC6210, PMC6211, PMC6212, PMC6213, PMC6214, PMC6215, PMC6216, PMC6217, PMC6218, PMC6219, + PMC6220, PMC6221, PMC6222, PMC6223, PMC6224, PMC6225, PMC6226, PMC6227, PMC6228, PMC6229, + PMC6230, PMC6231, PMC6232, PMC6233, PMC6234, PMC6235, PMC6236, PMC6237, PMC6238, PMC6239, + PMC6240, PMC6241, PMC6242, PMC6243, PMC6244, PMC6245, PMC6246, PMC6247, PMC6248, PMC6249, + PMC6250, PMC6251, PMC6252, PMC6253, PMC6254, PMC6255, PMC6256, PMC6257, PMC6258, PMC6259, + PMC6260, PMC6261, PMC6262, PMC6263, PMC6264, PMC6265, PMC6266, PMC6267, PMC6268, PMC6269, + PMC6270, PMC6271, PMC6272, PMC6273, PMC6274, PMC6275, PMC6276, PMC6277, PMC6278, PMC6279, + PMC6280, PMC6281, PMC6282, PMC6283, PMC6284, PMC6285, PMC6286, PMC6287, PMC6288, PMC6289, + PMC6290, PMC6291, PMC6292, PMC6293, PMC6294, PMC6295, PMC6296, PMC6297, PMC6298, PMC6299, + PMC6300, PMC6301, PMC6302, PMC6303, PMC6304, PMC6305, PMC6306, PMC6307, PMC6308, PMC6309, + PMC6310, PMC6311, PMC6312, PMC6313, PMC6314, PMC6315, PMC6316, PMC6317, PMC6318, PMC6319, + PMC6320, PMC6321, PMC6322, PMC6323, PMC6324, PMC6325, PMC6326, PMC6327, PMC6328, PMC6329, + PMC6330, PMC6331, PMC6332, PMC6333, PMC6334, PMC6335, PMC6336, PMC6337, PMC6338, PMC6339, + PMC6340, PMC6341, PMC6342, PMC6343, PMC6344, PMC6345, PMC6346, PMC6347, PMC6348, PMC6349, + PMC6350, PMC6351, PMC6352, PMC6353, PMC6354, PMC6355, PMC6356, PMC6357, PMC6358, PMC6359, + PMC6360, PMC6361, PMC6362, PMC6363, PMC6364, PMC6365, PMC6366, PMC6367, PMC6368, PMC6369, + PMC6370, PMC6371, PMC6372, PMC6373, PMC6374, PMC6375, PMC6376, PMC6377, PMC6378, PMC6379, + PMC6380, PMC6381, PMC6382, PMC6383, PMC6384, PMC6385, PMC6386, PMC6387, PMC6388, PMC6389, + PMC6390, PMC6391, PMC6392, PMC6393, PMC6394, PMC6395, PMC6396, PMC6397, PMC6398, PMC6399, + PMC6400, PMC6401, PMC6402, PMC6403, PMC6404, PMC6405, PMC6406, PMC6407, PMC6408, PMC6409, + PMC6410, PMC6411, PMC6412, PMC6413, PMC6414, PMC6415, PMC6416, PMC6417, PMC6418, PMC6419, + PMC6420, PMC6421, PMC6422, PMC6423, PMC6424, PMC6425, PMC6426, PMC6427, PMC6428, PMC6429, + PMC6430, PMC6431, PMC6432, PMC6433, PMC6434, PMC6435, PMC6436, PMC6437, PMC6438, PMC6439, + PMC6440, PMC6441, PMC6442, PMC6443, PMC6444, PMC6445, PMC6446, PMC6447, PMC6448, PMC6449, + PMC6450, PMC6451, PMC6452, PMC6453, PMC6454, PMC6455, PMC6456, PMC6457, PMC6458, PMC6459, + PMC6460, PMC6461, PMC6462, PMC6463, PMC6464, PMC6465, PMC6466, PMC6467, PMC6468, PMC6469, + PMC6470, PMC6471, PMC6472, PMC6473, PMC6474, PMC6475, PMC6476, PMC6477, PMC6478, PMC6479, + PMC6480, PMC6481, PMC6482, PMC6483, PMC6484, PMC6485, PMC6486, PMC6487, PMC6488, PMC6489, + PMC6490, PMC6491, PMC6492, PMC6493, PMC6494, PMC6495, PMC6496, PMC6497, PMC6498, PMC6499, + PMC6500, PMC6501, PMC6502, PMC6503, PMC6504, PMC6505, PMC6506, PMC6507, PMC6508, PMC6509, + PMC6510, PMC6511, PMC6512, PMC6513, PMC6514, PMC6515, PMC6516, PMC6517, PMC6518, PMC6519, + PMC6520, PMC6521, PMC6522, PMC6523, PMC6524, PMC6525, PMC6526, PMC6527, PMC6528, PMC6529, + PMC6530, PMC6531, PMC6532, PMC6533, PMC6534, PMC6535, PMC6536, PMC6537, PMC6538, PMC6539, + PMC6540, PMC6541, PMC6542, PMC6543, PMC6544, PMC6545, PMC6546, PMC6547, PMC6548, PMC6549, + PMC6550, PMC6551, PMC6552, PMC6553, PMC6554, PMC6555, PMC6556, PMC6557, PMC6558, PMC6559, + PMC6560, PMC6561, PMC6562, PMC6563, PMC6564, PMC6565, PMC6566, PMC6567, PMC6568, PMC6569, + PMC6570, PMC6571, PMC6572, PMC6573, PMC6574, PMC6575, PMC6576, PMC6577, PMC6578, PMC6579, + PMC6580, PMC6581, PMC6582, PMC6583, PMC6584, PMC6585, PMC6586, PMC6587, PMC6588, PMC6589, + PMC6590, PMC6591, PMC6592, PMC6593, PMC6594, PMC6595, PMC6596, PMC6597, PMC6598, PMC6599, + PMC6600, PMC6601, PMC6602, PMC6603, PMC6604, PMC6605, PMC6606, PMC6607, PMC6608, PMC6609, + PMC6610, PMC6611, PMC6612, PMC6613, PMC6614, PMC6615, PMC6616, PMC6617, PMC6618, PMC6619, + PMC6620, PMC6621, PMC6622, PMC6623, PMC6624, PMC6625, PMC6626, PMC6627, PMC6628, PMC6629, + PMC6630, PMC6631, PMC6632, PMC6633, PMC6634, PMC6635, PMC6636, PMC6637, PMC6638, PMC6639, + PMC6640, PMC6641, PMC6642, PMC6643, PMC6644, PMC6645, PMC6646, PMC6647, PMC6648, PMC6649, + PMC6650, PMC6651, PMC6652, PMC6653, PMC6654, PMC6655, PMC6656, PMC6657, PMC6658, PMC6659, + PMC6660, PMC6661, PMC6662, PMC6663, PMC6664, PMC6665, PMC6666, PMC6667, PMC6668, PMC6669, + PMC6670, PMC6671, PMC6672, PMC6673, PMC6674, PMC6675, PMC6676, PMC6677, PMC6678, PMC6679, + PMC6680, PMC6681, PMC6682, PMC6683, PMC6684, PMC6685, PMC6686, PMC6687, PMC6688, PMC6689, + PMC6690, PMC6691, PMC6692, PMC6693, PMC6694, PMC6695, PMC6696, PMC6697, PMC6698, PMC6699, + PMC6700, PMC6701, PMC6702, PMC6703, PMC6704, PMC6705, PMC6706, PMC6707, PMC6708, PMC6709, + PMC6710, PMC6711, PMC6712, PMC6713, PMC6714, PMC6715, PMC6716, PMC6717, PMC6718, PMC6719, + PMC6720, PMC6721, PMC6722, PMC6723, PMC6724, PMC6725, PMC6726, PMC6727, PMC6728, PMC6729, + PMC6730, PMC6731, PMC6732, PMC6733, PMC6734, PMC6735, PMC6736, PMC6737, PMC6738, PMC6739, + PMC6740, PMC6741, PMC6742, PMC6743, PMC6744, PMC6745, PMC6746, PMC6747, PMC6748, PMC6749, + PMC6750, PMC6751, PMC6752, PMC6753, PMC6754, PMC6755, PMC6756, PMC6757, PMC6758, PMC6759, + PMC6760, PMC6761, PMC6762, PMC6763, PMC6764, PMC6765, PMC6766, PMC6767, PMC6768, PMC6769, + PMC6770, PMC6771, PMC6772, PMC6773, PMC6774, PMC6775, PMC6776, PMC6777, PMC6778, PMC6779, + PMC6780, PMC6781, PMC6782, PMC6783, PMC6784, PMC6785, PMC6786, PMC6787, PMC6788, PMC6789, + PMC6790, PMC6791, PMC6792, PMC6793, PMC6794, PMC6795, PMC6796, PMC6797, PMC6798, PMC6799, + PMC6800, PMC6801, PMC6802, PMC6803, PMC6804, PMC6805, PMC6806, PMC6807, PMC6808, PMC6809, + PMC6810, PMC6811, PMC6812, PMC6813, PMC6814, PMC6815, PMC6816, PMC6817, PMC6818, PMC6819, + PMC6820, PMC6821, PMC6822, PMC6823, PMC6824, PMC6825, PMC6826, PMC6827, PMC6828, PMC6829, + PMC6830, PMC6831, PMC6832, PMC6833, PMC6834, PMC6835, PMC6836, PMC6837, PMC6838, PMC6839, + PMC6840, PMC6841, PMC6842, PMC6843, PMC6844, PMC6845, PMC6846, PMC6847, PMC6848, PMC6849, + PMC6850, PMC6851, PMC6852, PMC6853, PMC6854, PMC6855, PMC6856, PMC6857, PMC6858, PMC6859, + PMC6860, PMC6861, PMC6862, PMC6863, PMC6864, PMC6865, PMC6866, PMC6867, PMC6868, PMC6869, + PMC6870, PMC6871, PMC6872, PMC6873, PMC6874, PMC6875, PMC6876, PMC6877, PMC6878, PMC6879, + PMC6880, PMC6881, PMC6882, PMC6883, PMC6884, PMC6885, PMC6886, PMC6887, PMC6888, PMC6889, + PMC6890, PMC6891, PMC6892, PMC6893, PMC6894, PMC6895, PMC6896, PMC6897, PMC6898, PMC6899, + PMC6900, PMC6901, PMC6902, PMC6903, PMC6904, PMC6905, PMC6906, PMC6907, PMC6908, PMC6909, + PMC6910, PMC6911, PMC6912, PMC6913, PMC6914, PMC6915, PMC6916, PMC6917, PMC6918, PMC6919, + PMC6920, PMC6921, PMC6922, PMC6923, PMC6924, PMC6925, PMC6926, PMC6927, PMC6928, PMC6929, + PMC6930, PMC6931, PMC6932, PMC6933, PMC6934, PMC6935, PMC6936, PMC6937, PMC6938, PMC6939, + PMC6940, PMC6941, PMC6942, PMC6943, PMC6944, PMC6945, PMC6946, PMC6947, PMC6948, PMC6949, + PMC6950, PMC6951, PMC6952, PMC6953, PMC6954, PMC6955, PMC6956, PMC6957, PMC6958, PMC6959, + PMC6960, PMC6961, PMC6962, PMC6963, PMC6964, PMC6965, PMC6966, PMC6967, PMC6968, PMC6969, + PMC6970, PMC6971, PMC6972, PMC6973, PMC6974, PMC6975, PMC6976, PMC6977, PMC6978, PMC6979, + PMC6980, PMC6981, PMC6982, PMC6983, PMC6984, PMC6985, PMC6986, PMC6987, PMC6988, PMC6989, + PMC6990, PMC6991, PMC6992, PMC6993, PMC6994, PMC6995, PMC6996, PMC6997, PMC6998, PMC6999, + PMC7000, PMC7001, PMC7002, PMC7003, PMC7004, PMC7005, PMC7006, PMC7007, PMC7008, PMC7009, + PMC7010, PMC7011, PMC7012, PMC7013, PMC7014, PMC7015, PMC7016, PMC7017, PMC7018, PMC7019, + PMC7020, PMC7021, PMC7022, PMC7023, PMC7024, PMC7025, PMC7026, PMC7027, PMC7028, PMC7029, + PMC7030, PMC7031, PMC7032, PMC7033, PMC7034, PMC7035, PMC7036, PMC7037, PMC7038, PMC7039, + PMC7040, PMC7041, PMC7042, PMC7043, PMC7044, PMC7045, PMC7046, PMC7047, PMC7048, PMC7049, + PMC7050, PMC7051, PMC7052, PMC7053, PMC7054, PMC7055, PMC7056, PMC7057, PMC7058, PMC7059, + PMC7060, PMC7061, PMC7062, PMC7063, PMC7064, PMC7065, PMC7066, PMC7067, PMC7068, PMC7069, + PMC7070, PMC7071, PMC7072, PMC7073, PMC7074, PMC7075, PMC7076, PMC7077, PMC7078, PMC7079, + PMC7080, PMC7081, PMC7082, PMC7083, PMC7084, PMC7085, PMC7086, PMC7087, PMC7088, PMC7089, + PMC7090, PMC7091, PMC7092, PMC7093, PMC7094, PMC7095, PMC7096, PMC7097, PMC7098, PMC7099, + PMC7100, PMC7101, PMC7102, PMC7103, PMC7104, PMC7105, PMC7106, PMC7107, PMC7108, PMC7109, + PMC7110, PMC7111, PMC7112, PMC7113, PMC7114, PMC7115, PMC7116, PMC7117, PMC7118, PMC7119, + PMC7120, PMC7121, PMC7122, PMC7123, PMC7124, PMC7125, PMC7126, PMC7127, PMC7128, PMC7129, + PMC7130, PMC7131, PMC7132, PMC7133, PMC7134, PMC7135, PMC7136, PMC7137, PMC7138, PMC7139, + PMC7140, PMC7141, PMC7142, PMC7143, PMC7144, PMC7145, PMC7146, PMC7147, PMC7148, PMC7149, + PMC7150, PMC7151, PMC7152, PMC7153, PMC7154, PMC7155, PMC7156, PMC7157, PMC7158, PMC7159, + PMC7160, PMC7161, PMC7162, PMC7163, PMC7164, PMC7165, PMC7166, PMC7167, PMC7168, PMC7169, + PMC7170, PMC7171, PMC7172, PMC7173, PMC7174, PMC7175, PMC7176, PMC7177, PMC7178, PMC7179, + PMC7180, PMC7181, PMC7182, PMC7183, PMC7184, PMC7185, PMC7186, PMC7187, PMC7188, PMC7189, + PMC7190, PMC7191, PMC7192, PMC7193, PMC7194, PMC7195, PMC7196, PMC7197, PMC7198, PMC7199, + PMC7200, PMC7201, PMC7202, PMC7203, PMC7204, PMC7205, PMC7206, PMC7207, PMC7208, PMC7209, + PMC7210, PMC7211, PMC7212, PMC7213, PMC7214, PMC7215, PMC7216, PMC7217, PMC7218, PMC7219, + PMC7220, PMC7221, PMC7222, PMC7223, PMC7224, PMC7225, PMC7226, PMC7227, PMC7228, PMC7229, + PMC7230, PMC7231, PMC7232, PMC7233, PMC7234, PMC7235, PMC7236, PMC7237, PMC7238, PMC7239, + PMC7240, PMC7241, PMC7242, PMC7243, PMC7244, PMC7245, PMC7246, PMC7247, PMC7248, PMC7249, + PMC7250, PMC7251, PMC7252, PMC7253, PMC7254, PMC7255, PMC7256, PMC7257, PMC7258, PMC7259, + PMC7260, PMC7261, PMC7262, PMC7263, PMC7264, PMC7265, PMC7266, PMC7267, PMC7268, PMC7269, + PMC7270, PMC7271, PMC7272, PMC7273, PMC7274, PMC7275, PMC7276, PMC7277, PMC7278, PMC7279, + PMC7280, PMC7281, PMC7282, PMC7283, PMC7284, PMC7285, PMC7286, PMC7287, PMC7288, PMC7289, + PMC7290, PMC7291, PMC7292, PMC7293, PMC7294, PMC7295, PMC7296, PMC7297, PMC7298, PMC7299, + PMC7300, PMC7301, PMC7302, PMC7303, PMC7304, PMC7305, PMC7306, PMC7307, PMC7308, PMC7309, + PMC7310, PMC7311, PMC7312, PMC7313, PMC7314, PMC7315, PMC7316, PMC7317, PMC7318, PMC7319, + PMC7320, PMC7321, PMC7322, PMC7323, PMC7324, PMC7325, PMC7326, PMC7327, PMC7328, PMC7329, + PMC7330, PMC7331, PMC7332, PMC7333, PMC7334, PMC7335, PMC7336, PMC7337, PMC7338, PMC7339, + PMC7340, PMC7341, PMC7342, PMC7343, PMC7344, PMC7345, PMC7346, PMC7347, PMC7348, PMC7349, + PMC7350, PMC7351, PMC7352, PMC7353, PMC7354, PMC7355, PMC7356, PMC7357, PMC7358, PMC7359, + PMC7360, PMC7361, PMC7362, PMC7363, PMC7364, PMC7365, PMC7366, PMC7367, PMC7368, PMC7369, + PMC7370, PMC7371, PMC7372, PMC7373, PMC7374, PMC7375, PMC7376, PMC7377, PMC7378, PMC7379, + PMC7380, PMC7381, PMC7382, PMC7383, PMC7384, PMC7385, PMC7386, PMC7387, PMC7388, PMC7389, + PMC7390, PMC7391, PMC7392, PMC7393, PMC7394, PMC7395, PMC7396, PMC7397, PMC7398, PMC7399, + PMC7400, PMC7401, PMC7402, PMC7403, PMC7404, PMC7405, PMC7406, PMC7407, PMC7408, PMC7409, + PMC7410, PMC7411, PMC7412, PMC7413, PMC7414, PMC7415, PMC7416, PMC7417, PMC7418, PMC7419, + PMC7420, PMC7421, PMC7422, PMC7423, PMC7424, PMC7425, PMC7426, PMC7427, PMC7428, PMC7429, + PMC7430, PMC7431, PMC7432, PMC7433, PMC7434, PMC7435, PMC7436, PMC7437, PMC7438, PMC7439, + PMC7440, PMC7441, PMC7442, PMC7443, PMC7444, PMC7445, PMC7446, PMC7447, PMC7448, PMC7449, + PMC7450, PMC7451, PMC7452, PMC7453, PMC7454, PMC7455, PMC7456, PMC7457, PMC7458, PMC7459, + PMC7460, PMC7461, PMC7462, PMC7463, PMC7464, PMC7465, PMC7466, PMC7467, PMC7468, PMC7469, + PMC7470, PMC7471, PMC7472, PMC7473, PMC7474, PMC7475, PMC7476, PMC7477, PMC7478, PMC7479, + PMC7480, PMC7481, PMC7482, PMC7483, PMC7484, PMC7485, PMC7486, PMC7487, PMC7488, PMC7489, + PMC7490, PMC7491, PMC7492, PMC7493, PMC7494, PMC7495, PMC7496, PMC7497, PMC7498, PMC7499, + PMC7500, PMC7501, PMC7502, PMC7503, PMC7504, PMC7505, PMC7506, PMC7507, PMC7508, PMC7509, + PMC7510, PMC7511, PMC7512, PMC7513, PMC7514, PMC7515, PMC7516, PMC7517, PMC7518, PMC7519, + PMC7520, PMC7521, PMC7522, PMC7523, PMC7524, PMC7525, PMC7526, PMC7527, PMC7528, PMC7529, + PMC7530, PMC7531, PMC7532, PMC7533, PMC7534, PMC7535, PMC7536, PMC7537, PMC7538, PMC7539, + PMC7540, PMC7541, PMC7542, PMC7543, PMC7544, PMC7545, PMC7546, PMC7547, PMC7548, PMC7549, + PMC7550, PMC7551, PMC7552, PMC7553, PMC7554, PMC7555, PMC7556, PMC7557, PMC7558, PMC7559, + PMC7560, PMC7561, PMC7562, PMC7563, PMC7564, PMC7565, PMC7566, PMC7567, PMC7568, PMC7569, + PMC7570, PMC7571, PMC7572, PMC7573, PMC7574, PMC7575, PMC7576, PMC7577, PMC7578, PMC7579, + PMC7580, PMC7581, PMC7582, PMC7583, PMC7584, PMC7585, PMC7586, PMC7587, PMC7588, PMC7589, + PMC7590, PMC7591, PMC7592, PMC7593, PMC7594, PMC7595, PMC7596, PMC7597, PMC7598, PMC7599, + PMC7600, PMC7601, PMC7602, PMC7603, PMC7604, PMC7605, PMC7606, PMC7607, PMC7608, PMC7609, + PMC7610, PMC7611, PMC7612, PMC7613, PMC7614, PMC7615, PMC7616, PMC7617, PMC7618, PMC7619, + PMC7620, PMC7621, PMC7622, PMC7623, PMC7624, PMC7625, PMC7626, PMC7627, PMC7628, PMC7629, + PMC7630, PMC7631, PMC7632, PMC7633, PMC7634, PMC7635, PMC7636, PMC7637, PMC7638, PMC7639, + PMC7640, PMC7641, PMC7642, PMC7643, PMC7644, PMC7645, PMC7646, PMC7647, PMC7648, PMC7649, + PMC7650, PMC7651, PMC7652, PMC7653, PMC7654, PMC7655, PMC7656, PMC7657, PMC7658, PMC7659, + PMC7660, PMC7661, PMC7662, PMC7663, PMC7664, PMC7665, PMC7666, PMC7667, PMC7668, PMC7669, + PMC7670, PMC7671, PMC7672, PMC7673, PMC7674, PMC7675, PMC7676, PMC7677, PMC7678, PMC7679, + PMC7680, PMC7681, PMC7682, PMC7683, PMC7684, PMC7685, PMC7686, PMC7687, PMC7688, PMC7689, + PMC7690, PMC7691, PMC7692, PMC7693, PMC7694, PMC7695, PMC7696, PMC7697, PMC7698, PMC7699, + PMC7700, PMC7701, PMC7702, PMC7703, PMC7704, PMC7705, PMC7706, PMC7707, PMC7708, PMC7709, + PMC7710, PMC7711, PMC7712, PMC7713, PMC7714, PMC7715, PMC7716, PMC7717, PMC7718, PMC7719, + PMC7720, PMC7721, PMC7722, PMC7723, PMC7724, PMC7725, PMC7726, PMC7727, PMC7728, PMC7729, + PMC7730, PMC7731, PMC7732, PMC7733, PMC7734, PMC7735, PMC7736, PMC7737, PMC7738, PMC7739, + PMC7740, PMC7741, PMC7742, PMC7743, PMC7744, PMC7745, PMC7746, PMC7747, PMC7748, PMC7749, + PMC7750, PMC7751, PMC7752, PMC7753, PMC7754, PMC7755, PMC7756, PMC7757, PMC7758, PMC7759, + PMC7760, PMC7761, PMC7762, PMC7763, PMC7764, PMC7765, PMC7766, PMC7767, PMC7768, PMC7769, + PMC7770, PMC7771, PMC7772, PMC7773, PMC7774, PMC7775, PMC7776, PMC7777, PMC7778, PMC7779, + PMC7780, PMC7781, PMC7782, PMC7783, PMC7784, PMC7785, PMC7786, PMC7787, PMC7788, PMC7789, + PMC7790, PMC7791, PMC7792, PMC7793, PMC7794, PMC7795, PMC7796, PMC7797, PMC7798, PMC7799, + PMC7800, PMC7801, PMC7802, PMC7803, PMC7804, PMC7805, PMC7806, PMC7807, PMC7808, PMC7809, + PMC7810, PMC7811, PMC7812, PMC7813, PMC7814, PMC7815, PMC7816, PMC7817, PMC7818, PMC7819, + PMC7820, PMC7821, PMC7822, PMC7823, PMC7824, PMC7825, PMC7826, PMC7827, PMC7828, PMC7829, + PMC7830, PMC7831, PMC7832, PMC7833, PMC7834, PMC7835, PMC7836, PMC7837, PMC7838, PMC7839, + PMC7840, PMC7841, PMC7842, PMC7843, PMC7844, PMC7845, PMC7846, PMC7847, PMC7848, PMC7849, + PMC7850, PMC7851, PMC7852, PMC7853, PMC7854, PMC7855, PMC7856, PMC7857, PMC7858, PMC7859, + PMC7860, PMC7861, PMC7862, PMC7863, PMC7864, PMC7865, PMC7866, PMC7867, PMC7868, PMC7869, + PMC7870, PMC7871, PMC7872, PMC7873, PMC7874, PMC7875, PMC7876, PMC7877, PMC7878, PMC7879, + PMC7880, PMC7881, PMC7882, PMC7883, PMC7884, PMC7885, PMC7886, PMC7887, PMC7888, PMC7889, + PMC7890, PMC7891, PMC7892, PMC7893, PMC7894, PMC7895, PMC7896, PMC7897, PMC7898, PMC7899, + PMC7900, PMC7901, PMC7902, PMC7903, PMC7904, PMC7905, PMC7906, PMC7907, PMC7908, PMC7909, + PMC7910, PMC7911, PMC7912, PMC7913, PMC7914, PMC7915, PMC7916, PMC7917, PMC7918, PMC7919, + PMC7920, PMC7921, PMC7922, PMC7923, PMC7924, PMC7925, PMC7926, PMC7927, PMC7928, PMC7929, + PMC7930, PMC7931, PMC7932, PMC7933, PMC7934, PMC7935, PMC7936, PMC7937, PMC7938, PMC7939, + PMC7940, PMC7941, PMC7942, PMC7943, PMC7944, PMC7945, PMC7946, PMC7947, PMC7948, PMC7949, + PMC7950, PMC7951, PMC7952, PMC7953, PMC7954, PMC7955, PMC7956, PMC7957, PMC7958, PMC7959, + PMC7960, PMC7961, PMC7962, PMC7963, PMC7964, PMC7965, PMC7966, PMC7967, PMC7968, PMC7969, + PMC7970, PMC7971, PMC7972, PMC7973, PMC7974, PMC7975, PMC7976, PMC7977, PMC7978, PMC7979, + PMC7980, PMC7981, PMC7982, PMC7983, PMC7984, PMC7985, PMC7986, PMC7987, PMC7988, PMC7989, + PMC7990, PMC7991, PMC7992, PMC7993, PMC7994, PMC7995, PMC7996, PMC7997, PMC7998, PMC7999, NUM_PMC } RegisterIndex; @@ -180,39 +851,34 @@ typedef enum { MBOX12FIX, MBOX13FIX, MBOX14FIX, MBOX15FIX, MDEV0, MDEV1, MDEV2, MDEV3, MBOX0TMP, - BBOX0, BBOX1, BBOX2, BBOX3, - BBOX4, BBOX5, BBOX6, BBOX7, - BBOX8, BBOX9, BBOX10, BBOX11, - BBOX12, BBOX13, BBOX14, BBOX15, - BBOX16, BBOX17, BBOX18, BBOX19, - BBOX20, BBOX21, BBOX22, BBOX23, - BBOX24, BBOX25, BBOX26, BBOX27, - BBOX28, BBOX29, BBOX30, BBOX31, - RBOX0, RBOX1, RBOX2, RBOX3, - WBOX, + BBOX0, BBOX1, BBOX2, BBOX3, BBOX4, BBOX5, BBOX6, BBOX7, BBOX8, BBOX9, + BBOX10, BBOX11, BBOX12, BBOX13, BBOX14, BBOX15, BBOX16, BBOX17, BBOX18, BBOX19, + BBOX20, BBOX21, BBOX22, BBOX23, BBOX24, BBOX25, BBOX26, BBOX27, BBOX28, BBOX29, + BBOX30, BBOX31, BBOX32, BBOX33, BBOX34, BBOX35, BBOX36, BBOX37, BBOX38, BBOX39, + BBOX40, BBOX41, BBOX42, BBOX43, BBOX44, BBOX45, BBOX46, BBOX47, BBOX48, BBOX49, + BBOX50, BBOX51, BBOX52, BBOX53, BBOX54, BBOX55, BBOX56, BBOX57, BBOX58, BBOX59, + RBOX0, RBOX1, RBOX2, RBOX3, RBOX4, RBOX5, RBOX6, RBOX7, + WBOX0, WBOX1, WBOX2, WBOX3, WBOX4, WBOX5, WBOX6, WBOX7, WBOX0FIX, WBOX1FIX, WBOX2FIX, WBOX3FIX, SBOX0, SBOX1, SBOX2, SBOX3, SBOX0FIX, SBOX1FIX, SBOX2FIX, SBOX3FIX, - CBOX0, CBOX1, CBOX2, - CBOX3, CBOX4, CBOX5, - CBOX6, CBOX7, CBOX8, - CBOX9, CBOX10, CBOX11, - CBOX12, CBOX13, CBOX14, - CBOX15, CBOX16, CBOX17, - CBOX18, CBOX19, CBOX20, - CBOX21, CBOX22, CBOX23, - CBOX24, CBOX25, CBOX26, - CBOX27, CBOX28, CBOX29, - CBOX30, CBOX31, CBOX32, - CBOX33, CBOX34, CBOX35, - CBOX36, CBOX37, CBOX38, CBOX39, - CBOX40, CBOX41, CBOX42, - CBOX43, CBOX44, CBOX45, - CBOX46, CBOX47, CBOX48, CBOX49, - CBOX50, CBOX51, CBOX52, - CBOX53, CBOX54, CBOX55, - CBOX56, CBOX57, CBOX58, CBOX59, - PBOX, PBOX1, PBOX2, PBOX3, PBOX4, PBOX5, PBOX6, PBOX7, PBOX8, PBOX9, PBOX10, PBOX11, PBOX12, PBOX13, PBOX14, PBOX15, + CBOX0, CBOX1, CBOX2, CBOX3, CBOX4, CBOX5, CBOX6, CBOX7, CBOX8, CBOX9, + CBOX10, CBOX11, CBOX12, CBOX13, CBOX14, CBOX15, CBOX16, CBOX17, CBOX18, CBOX19, + CBOX20, CBOX21, CBOX22, CBOX23, CBOX24, CBOX25, CBOX26, CBOX27, CBOX28, CBOX29, + CBOX30, CBOX31, CBOX32, CBOX33, CBOX34, CBOX35, CBOX36, CBOX37, CBOX38, CBOX39, + CBOX40, CBOX41, CBOX42, CBOX43, CBOX44, CBOX45, CBOX46, CBOX47, CBOX48, CBOX49, + CBOX50, CBOX51, CBOX52, CBOX53, CBOX54, CBOX55, CBOX56, CBOX57, CBOX58, CBOX59, + CBOX60, CBOX61, CBOX62, CBOX63, CBOX64, CBOX65, CBOX66, CBOX67, CBOX68, CBOX69, + CBOX70, CBOX71, CBOX72, CBOX73, CBOX74, CBOX75, CBOX76, CBOX77, CBOX78, CBOX79, + CBOX80, CBOX81, CBOX82, CBOX83, CBOX84, CBOX85, CBOX86, CBOX87, CBOX88, CBOX89, + CBOX90, CBOX91, CBOX92, CBOX93, CBOX94, CBOX95, CBOX96, CBOX97, CBOX98, CBOX99, + CBOX100, CBOX101, CBOX102, CBOX103, CBOX104, CBOX105, CBOX106, CBOX107, CBOX108, CBOX109, + CBOX110, CBOX111, CBOX112, CBOX113, CBOX114, CBOX115, CBOX116, CBOX117, CBOX118, CBOX119, + CBOX120, CBOX121, CBOX122, CBOX123, CBOX124, CBOX125, CBOX126, CBOX127, CBOX128, CBOX129, + PBOX0, PBOX1, PBOX2, PBOX3, PBOX4, PBOX5, PBOX6, PBOX7, PBOX8, PBOX9, + PBOX10, PBOX11, PBOX12, PBOX13, PBOX14, PBOX15, PBOX16, PBOX17, PBOX18, PBOX19, + PBOX20, PBOX21, PBOX22, PBOX23, PBOX24, PBOX25, PBOX26, PBOX27, PBOX28, PBOX29, + PBOX30, PBOX31, PBOX32, PBOX33, PBOX34, PBOX35, PBOX36, PBOX37, PBOX38, PBOX39, UBOX, UBOXFIX, IBOX0, IBOX1, IBOX2, IBOX3, IBOX4, IBOX5, IBOX6, IBOX7, IBOX8, IBOX9, IBOX10, IBOX11, IBOX12, IBOX13, IBOX14, IBOX15, @@ -253,7 +919,8 @@ typedef enum { NUM_UNITS, NOTYPE, MAX_UNITS } RegisterType; -#define PBOX0 PBOX +#define PBOX PBOX0 +#define WBOX WBOX0 static char* RegisterTypeNames[MAX_UNITS] = { [PMC] = "Core-local general purpose counters", diff --git a/src/includes/topology.h b/src/includes/topology.h index 298274a8b..d85a60238 100644 --- a/src/includes/topology.h +++ b/src/includes/topology.h @@ -117,6 +117,8 @@ struct topology_functions { #define ALDERLAKE1 0x97U #define ALDERLAKE2 0x9AU #define ALDERLAKE3 0xBFU +#define GRANITERAPIDS 0xADU +#define SIERRAFORREST 0xAFU /* Intel MIC */ #define XEON_PHI 0x01U diff --git a/src/intel_perfmon_uncore_discovery.c b/src/intel_perfmon_uncore_discovery.c index b7d6fce23..549e91f26 100644 --- a/src/intel_perfmon_uncore_discovery.c +++ b/src/intel_perfmon_uncore_discovery.c @@ -6,11 +6,15 @@ #include #include #include +#include - -#include -#include +#include #include +#include +#include +#include + +static PerfmonUncoreDiscovery* uncore_discovery_map = NULL; /* Functions for the same handling of PCI devices and their memory in user-space as in kernel-space */ @@ -23,7 +27,9 @@ struct pci_dev { int numa_node; }; -static void mymemcpy(void* dest, void* src, int size) +// glibc memcpy uses optimized versions but copies have to be bytewise +// otherwise the data is incorrect. +void mymemcpy(void* dest, void* src, int size) { uint8_t volatile* udest = (uint8_t*)dest; uint8_t volatile* usrc = (uint8_t*)src; @@ -33,37 +39,20 @@ static void mymemcpy(void* dest, void* src, int size) } } - -static int pci_test_bus(int domain, int bus) -{ - char fname[1025]; - int ret = snprintf(fname, 1024, "/sys/class/pci_bus/%.04x:%.02x", domain, bus); - if (ret > 0) - { - fname[ret] = '\0'; - } - else - { - ERROR_PRINT(Cannot format path to PCI bus directory for domain %d and bus %d, domain, bus); - } - return !access(fname, R_OK); -} - -static int pci_read_config_dword(const struct pci_dev *dev, int where, uint32_t *val) +// Read 32bit from PCI device config space +static int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val) { int ret = -1; char path[1025]; ret = snprintf(path, 1024, "/sys/bus/pci/devices/%.04x:%.02x:%.02x.%.01x/config", dev->domain, dev->bus, dev->device, dev->func); if (ret > 0) { path[ret] = '\0'; - ret = -1; if (!access(path, R_OK)) { - //printf("%s\n", path); int fp = open(path, O_RDONLY); if (fp > 0) { - ret = pread(fp, val, sizeof(uint32_t), where); + ret = pread(fp, val, sizeof(u32), where); close(fp); } } @@ -74,13 +63,13 @@ static int pci_read_config_dword(const struct pci_dev *dev, int where, uint32_t static int pci_find_next_ext_capability(struct pci_dev *dev, int start, int cap) { int ret = 0; int offset = PCI_EXT_CAP_BASE_OFFSET + start; - uint32_t cap_data = 0x0; + u32 cap_data = 0x0; do { ret = pci_read_config_dword(dev, offset, &cap_data); if (ret > 0) { - uint16_t cap_id = (cap_data & PCI_EXT_CAP_ID_MASK); + u16 cap_id = (cap_data & PCI_EXT_CAP_ID_MASK); if (cap_id == cap) break; ret = pci_read_config_dword(dev, offset + PCI_EXT_CAP_NEXT_OFFSET, &cap_data); offset = (ret > 0 ? (cap_data >> PCI_EXT_CAP_NEXT_SHIFT & PCI_EXT_CAP_NEXT_MASK) : 0); @@ -91,6 +80,7 @@ static int pci_find_next_ext_capability(struct pci_dev *dev, int start, int cap) return offset; } + /* Helper function to read files from sysfs */ static int file_to_uint(char* path, unsigned int *data) { int ret = -1; @@ -101,7 +91,7 @@ static int file_to_uint(char* path, unsigned int *data) { ret = read(fp, content, 1024 * sizeof(char)); if (ret >= 0) { content[ret] = '\0'; - unsigned int new = 0x0; + u64 new = 0x0; ret = sscanf(content, "0x%x", &new); if (ret == 1) { @@ -124,9 +114,90 @@ static int file_to_uint(char* path, unsigned int *data) { return ret; } +// Test whether PCI domain and bus exist. +static int pci_test_bus(int domain, int bus) +{ + char fname[1025]; + int ret = snprintf(fname, 1024, "/sys/class/pci_bus/%.04x:%.02x", domain, bus); + if (ret > 0) + { + fname[ret] = '\0'; + } + else + { + ERROR_PRINT(Cannot format path to PCI bus directory for domain %d and bus %d, domain, bus); + } + return !access(fname, R_OK); +} + +// commonly only a few PCI domains are populated, so we get the max domain +// to return from PCI device parsing early. Otherwise, we have to search +// 65535 domains. +static int get_max_pci_domain() +{ + int max_dom = 0; + DIR* dir = NULL; + struct dirent* dent = NULL; + + dir = opendir("/sys/class/pci_bus"); + if (!dir) + { + return -errno; + } + while((dent = readdir(dir))) + { + int dom = -1, bus = -1; + int c = sscanf(dent->d_name, "%X:%X", &dom, &bus); + if ((c == 2) && (dom > max_dom)) + { + max_dom = dom; + } + } + + closedir(dir); + return max_dom+1; +} + +// Get the maximal CPU socket ID to stop parsing. This does not work if +// sockets are not numbered consecutively. +static int max_socket_id(int* max_socket) +{ + int num_procs = sysconf (_SC_NPROCESSORS_CONF); + int cur_procs = 0; + int ret = -1; + int cur_max = 0; + char path[1025]; + for (int i = 0; i < 100000 && cur_procs < num_procs; i++) + { + ret = snprintf(path, 1024, "/sys/devices/system/cpu/cpu%d/topology/physical_package_id", i); + if (ret >= 0) + { + path[ret] = '\0'; + int id = 0; + ret = file_to_uint(path, &id); + if (ret == 0 && id > cur_max) + { + cur_max = id; + } + } + } + DEBUG_PRINT(DEBUGLEV_DEVELOP, Found max socket ID %d, cur_max); + *max_socket = cur_max; + return 0; +} + + -struct pci_dev * pci_get_device(unsigned int vendor, unsigned int device, struct pci_dev * from) + +static int _max_pci_domain_id = -1; +// This functions should mimic the behavior of pci_get_device in the kernel +// It searches the whole PCI space for a specific device and defined by vendor +// and device ID. Instead of vendor and device ID, the special PCI_ANY_ID can +// be used to get any device. In order to not start from zero each time, the +// function takes a device as input (from) to start from there. +struct pci_dev * pci_get_device (unsigned int vendor, unsigned int device, struct pci_dev * from) { + //struct pci_dev next = {from->domain, from->bus, from->device, from->func}; int domStart = (from ? from->domain : 0); int busStart = (from ? from->bus : 0); int devStart = (from ? from->device : 0); @@ -134,24 +205,38 @@ struct pci_dev * pci_get_device(unsigned int vendor, unsigned int device, struct char busbase[1025]; char devbase[1025]; char fname[1025]; - if (from) + + if (_max_pci_domain_id < 0) { - domStart = from->domain; - busStart = from->bus; - devStart = from->device; - funcStart = from->func; + int ret = get_max_pci_domain(); + if (ret < 0) + { + return NULL; + } + _max_pci_domain_id = ret; } - for (int dom = domStart; dom < 0xffff; dom++) { + + for (int dom = domStart; dom < _max_pci_domain_id; dom++) { + // if we are beyond the domain given in from, we start with bus=0 again + // instead of the bus given in from + if (from && dom > from->domain) busStart = 0; for (int bus = busStart; bus < 0xff; bus++) { int ret = 0; // Early skip if PCI bus does not exist if (!pci_test_bus(dom, bus)) { + continue; } + // if we are beyond the bus given in from, we start with devid=0 again + // instead of the device given in from + if (from && bus > from->bus) devStart = 0; for (int devid = devStart; devid < 0xff; devid++) { + // if we are beyond the device given in from, we start with func=0 again + // instead of the func given in from + if (from && devid > from->device) funcStart = 0; for (int func = funcStart; func < 0xf; func++) { // Skip the 'from' device - if (from && dom == domStart && bus == busStart && devid == devStart && func == funcStart) + if (from && dom == from->domain && bus == from->bus && devid == from->device && func == from->func) { continue; } @@ -222,7 +307,6 @@ struct pci_dev * pci_get_device(unsigned int vendor, unsigned int device, struct // Reuse space if (from) { - DEBUG_PRINT(DEBUGLEV_DEVELOP, Using discovery entry device %s, devbase); from->domain = dom; from->bus = bus; from->device = devid; @@ -235,7 +319,6 @@ struct pci_dev * pci_get_device(unsigned int vendor, unsigned int device, struct // First find, allocate a new PCI device struct pci_dev* next = malloc(sizeof(struct pci_dev)); if (next) { - DEBUG_PRINT(DEBUGLEV_DEVELOP, Using discovery entry device %s, devbase); next->domain = dom; next->bus = bus; next->device = devid; @@ -243,10 +326,6 @@ struct pci_dev * pci_get_device(unsigned int vendor, unsigned int device, struct next->numa_node = node; return next; } - else - { - ERROR_PRINT(Failed to allocate space for PCI device info); - } } } } @@ -255,172 +334,82 @@ struct pci_dev * pci_get_device(unsigned int vendor, unsigned int device, struct return NULL; } + PciDeviceIndex get_likwid_device(int type, int id) { - //printf("get_likwid_device(%d, %d) = ", type, id); - switch (type) + int i = 0; + while (uncore_discovery_map[i].discovery_type >= 0) { - case DEVICE_ID_CHA: - if (id < 0 || id > 60) - { - ERROR_PRINT(Cannot transform CHa device with ID %d, id); - } - else - { - return MSR_CBOX_DEVICE_C0 + id; - } - break; - case DEVICE_ID_iMC: - if (id < 0 || id > 15) - { - ERROR_PRINT(Cannot transform IMC device with ID %d, id); - } - else - { - return MMIO_IMC_DEVICE_0_CH_0 + id; - } - break; - case DEVICE_ID_M2PCIe: - if (id < 0 || id > 15) - { - ERROR_PRINT(Cannot transform M2PCIe device with ID %d, id); - } - else - { - return PCI_R2PCIE_DEVICE0 + id; - } - break; - case DEVICE_ID_PCU: - if (id < 0 || id > 1) - { - ERROR_PRINT(Cannot transform PCU device with ID %d, id); - } - else - { - return MSR_PCU_DEVICE; - } - break; - case DEVICE_ID_IRP: - if (id >= 0 && id <= 12) - { - return MSR_IRP_DEVICE_0 + id; - } - else - { - ERROR_PRINT(Cannot transform IRP device with ID %d, id); - } - break; - case DEVICE_ID_IIO: - if (id >= 0 && id <= 12) - { - return MSR_IIO_DEVICE_0 + id; - } - else - { - ERROR_PRINT(Cannot transform IIO device with ID %d, id); - } - break; - case DEVICE_ID_UPI: - if (id >= 0 && id <= 3) - { - return PCI_QPI_DEVICE_PORT_0 + id; - } - else - { - ERROR_PRINT(Cannot transform UPI device with ID %d, id); - } - break; - case DEVICE_ID_MDF: - if (id < 0 || id > 49) - { - ERROR_PRINT(Cannot transform MDF device with ID %d, id); - } - else - { - return MSR_MDF_DEVICE_0 + id; - } - break; - case DEVICE_ID_M2M: - if (id < 0 || id > 31) - { - ERROR_PRINT(Cannot transform M2M device with ID %d, id); - return MAX_NUM_PCI_DEVICES; - } - else - { - return PCI_HA_DEVICE_0 + id; - } - break; - case DEVICE_ID_M3UPI: - if (id < 0 || id > 3) - { - ERROR_PRINT(Cannot transform M3UPI device with ID %d, id); - } - else - { - return PCI_R3QPI_DEVICE_LINK_0 + id; - } - break; - case DEVICE_ID_HBM: - if (id < 0 || id > 31) - { - ERROR_PRINT(Cannot transform HBM device with ID %d, id); - } - else + if (uncore_discovery_map[i].discovery_type == type) + { + if (id >= 0 && id <= uncore_discovery_map[i].max_devices) { - return MMIO_HBM_DEVICE_0 + id; + return uncore_discovery_map[i].base_device + id; } - break; - default: - return MAX_NUM_PCI_DEVICES; - break; + } + i++; } + return MAX_NUM_PCI_DEVICES; } static void print_unit(PciDeviceIndex idx, PerfmonDiscoveryUnit* unit) { - DEBUG_PRINT(DEBUGLEV_DEVELOP, PCIIDX %d Access %s NumRegs %d ID %d Type %s(%d) box_ctl 0x%X ctrl_offset 0x%X ctr_offset 0x%X mmap_addr 0x%X mmap_offset 0x%X, idx, AccessTypeNames[unit->access_type], unit->num_regs, unit->box_id, uncore_discovery_box_type_names[unit->box_type], unit->box_type, unit->box_ctl, unit->ctrl_offset, unit->ctr_offset, unit->mmap_addr, unit->mmap_offset); -} + char* name = NULL; + int i = 0; + if (!uncore_discovery_map) return; -int max_socket_id(int* max_socket) -{ - int num_procs = sysconf (_SC_NPROCESSORS_CONF); - int cur_procs = 0; - int ret = -1; - int cur_max = 0; - char path[1025]; - for (int i = 0; i < 100000 && cur_procs < num_procs; i++) + while (uncore_discovery_map[i].discovery_type >= 0) { - ret = snprintf(path, 1024, "/sys/devices/system/cpu/cpu%d/topology/physical_package_id", i); - if (ret >= 0) + if (unit->box_type == uncore_discovery_map[i].discovery_type) { - path[ret] = '\0'; - int id = 0; - ret = file_to_uint(path, &id); - if (ret == 0 && id > cur_max) - { - cur_max = id; - } + name = uncore_discovery_map[i].name; + break; } + i++; + } + if (name != NULL) + { + DEBUG_PRINT(DEBUGLEV_DEVELOP, PCIIDX %d Access %s NumRegs %d ID %d Type %s(%d) box_ctl 0x%X ctrl_offset 0x%X ctr_offset 0x%X mmap_addr 0x%X mmap_offset 0x%X, + idx, AccessTypeNames[unit->access_type], unit->num_regs, unit->box_id, name, unit->box_type, + unit->box_ctl, unit->ctrl_offset, unit->ctr_offset, unit->mmap_addr, unit->mmap_offset); } - DEBUG_PRINT(DEBUGLEV_DEVELOP, Found max socket ID %d, cur_max); - *max_socket = cur_max; - return 0; } -int perfmon_uncore_discovery(PerfmonDiscovery** perfmon) + + +int perfmon_uncore_discovery(int model, PerfmonDiscovery** perfmon) { - int num = 0; int ret = 0; PerfmonDiscoverySocket* socks = NULL; - int socket_id = -1; + int socket_id = 0; struct pci_dev* dev = NULL; struct uncore_global_discovery global; int dvsec = 0; int PAGE_SIZE = sysconf (_SC_PAGESIZE); - void* io_addr = NULL; + void * io_addr = NULL; int max_sockets = 0; + u32 val = 0; + u32 entry_id = 0; + u32 bir; + u32 bar_offset = 0, pci_dword = 0; + u64 addr = 0; + + switch (model) + { + case SAPPHIRERAPIDS: + uncore_discovery_map = sapphirerapids_uncore_discovery_map; + break; + case GRANITERAPIDS: + uncore_discovery_map = graniterapids_uncore_discovery_map; + break; + case SIERRAFORREST: + uncore_discovery_map = sierraforrest_uncore_discovery_map; + break; + default: + ERROR_PRINT(Uncore discovery not supported for model 0x%X, model); + return -1; + } if (max_socket_id(&max_sockets) < 0) { @@ -445,63 +434,81 @@ int perfmon_uncore_discovery(PerfmonDiscovery** perfmon) perf->sockets = NULL; perf->num_sockets = 0; - while (((dev = pci_get_device(0x8086, UNCORE_DISCOVERY_TABLE_DEVICE, dev)) != NULL) && (socket_id < max_sockets)){ - socket_id++; - - PerfmonDiscoverySocket* tmp = realloc(perf->sockets, (num + 1) * sizeof(PerfmonDiscoverySocket)); - if (!tmp) - { - ERROR_PRINT(Cannot enlarge socket device table to %d, num); - if (perf->sockets) free(perf->sockets); - free(perf); - close(pcihandle); - return -ENOMEM; - } - perf->sockets = tmp; - PerfmonDiscoverySocket* cur = &perf->sockets[num]; - - cur->socket_id = socket_id; - memset(cur->units, 0, MAX_NUM_PCI_DEVICES*sizeof(PerfmonDiscoveryUnit)); - + while (((dev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, dev)) != NULL) && (socket_id < max_sockets+1)){ while ((dvsec = pci_find_next_ext_capability(dev, dvsec, UNCORE_EXT_CAP_ID_DISCOVERY))) { /* read the DVSEC_ID (15:0) */ - uint32_t val = 0; + val = 0; ret = pci_read_config_dword(dev, dvsec + UNCORE_DISCOVERY_DVSEC_OFFSET, &val); - if (ret < 0) continue; - uint32_t entry_id = val & UNCORE_DISCOVERY_DVSEC_ID_MASK; - if (entry_id == UNCORE_DISCOVERY_DVSEC_ID_PMON) { - uint32_t bir = 0; + if (ret < 0) + { + ERROR_PRINT(Failed to read DVSEC offset from device %.04x:%.02x:%.02x.%.01x, dev->domain, dev->bus, dev->device, dev->func); + continue; + } + entry_id = val & UNCORE_DISCOVERY_DVSEC_ID_MASK; + if (entry_id == UNCORE_DISCOVERY_DVSEC_ID_PMON) + { + //printf("Socket %d Dev %.04x:%.02x:%.02x.%.01x Node %d\n", socket_id, dev->domain, dev->bus, dev->device, dev->func, dev->numa_node); + bir = 0; ret = pci_read_config_dword(dev, dvsec + UNCORE_DISCOVERY_DVSEC2_OFFSET, &bir); - if (ret < 0) continue; - /* read BIR value (2:0) */ + if (ret < 0) + { + ERROR_PRINT(Failed to read DIR from device %.04x:%.02x:%.02x.%.01x, dev->domain, dev->bus, dev->device, dev->func); + continue; + } + /* read BIR value (2:0) */ bir = bir & UNCORE_DISCOVERY_DVSEC2_BIR_MASK; /* calculate the BAR offset of global discovery table */ - uint32_t bar_offset = UNCORE_DISCOVERY_BIR_BASE + (bir * UNCORE_DISCOVERY_BIR_STEP); + bar_offset = 0x10 + (bir * 4); /* read the BAR address of global discovery table */ - uint32_t pci_dword = 0; ret = pci_read_config_dword(dev, bar_offset, &pci_dword); - if (ret < 0) continue; + if (ret < 0) + { + ERROR_PRINT(Failed to read BAR offset from device %.04x:%.02x:%.02x.%.01x, dev->domain, dev->bus, dev->device, dev->func); + continue; + } /* get page boundary address of pci_dword */ - uint64_t addr = pci_dword & (~(PAGE_SIZE - 1)); + addr = pci_dword & ~(PAGE_SIZE - 1); if ((pci_dword & PCI_BASE_ADDRESS_MEM_TYPE_MASK) == PCI_BASE_ADDRESS_MEM_TYPE_64) { + DEBUG_PRINT(DEBUGLEV_DEVELOP, Mem type 64); uint32_t pci_dword2; ret = pci_read_config_dword(dev, bar_offset + sizeof(uint32_t), &pci_dword2); if (ret > 0) addr |= ((uint64_t)pci_dword2) << 32; } /* Map whole discovery table */ /* User-space version of ioremap */ + //printf("MMap address 0x%lX\n", addr); io_addr = mmap(NULL, UNCORE_DISCOVERY_MAP_SIZE, PROT_READ|PROT_WRITE, MAP_SHARED, pcihandle, addr); if (io_addr == MAP_FAILED) { + ERROR_PRINT(Failed to mmap device %.04x:%.02x:%.02x.%.01x, dev->domain, dev->bus, dev->device, dev->func); continue; } + memset(&global, 0, sizeof(struct uncore_global_discovery)); mymemcpy(&global, io_addr, sizeof(struct uncore_global_discovery)); if (uncore_discovery_invalid_unit(global)) { munmap(io_addr, UNCORE_DISCOVERY_MAP_SIZE); continue; } + //printf("Global 1=0x%lX 2=0x%lX 3=0x%lX\n", global.table1, global.table2, global.table3); + DEBUG_PRINT(DEBUGLEV_DEVELOP, Device %.04x:%.02x:%.02x.%.01x usable with %d units, dev->domain, dev->bus, dev->device, dev->func, global.max_units); + + PerfmonDiscoverySocket* tmp = realloc(perf->sockets, (socket_id + 1) * sizeof(PerfmonDiscoverySocket)); + if (!tmp) + { + ERROR_PRINT(Cannot enlarge socket device table to %d, socket_id); + if (perf->sockets) free(perf->sockets); + free(perf); + close(pcihandle); + munmap(io_addr, UNCORE_DISCOVERY_MAP_SIZE); + return -ENOMEM; + } + perf->sockets = tmp; + PerfmonDiscoverySocket* cur = &perf->sockets[socket_id]; + + cur->socket_id = socket_id; + memset(cur->units, 0, MAX_NUM_PCI_DEVICES*sizeof(PerfmonDiscoveryUnit)); // record stuff from global struct in cur->global cur->global.global_ctl = global.global_ctl; cur->global.access_type = global.access_type; @@ -510,7 +517,11 @@ int perfmon_uncore_discovery(PerfmonDiscovery** perfmon) for (int i = 0; i < global.max_units; i++) { struct uncore_unit_discovery unit; - if ((i + 1) * (global.stride * 8) > UNCORE_DISCOVERY_MAP_SIZE) continue; + if ((i + 1) * (global.stride * 8) > UNCORE_DISCOVERY_MAP_SIZE) + { + //ERROR_PRINT(Access to 0x%X outside of mapped memory, (i + 1) * (global.stride * 8)); + continue; + } mymemcpy(&unit, io_addr + (i + 1) * (global.stride * 8), sizeof(struct uncore_unit_discovery)); if ((uncore_discovery_invalid_unit(unit)) || (unit.num_regs == 0)) { @@ -520,7 +531,7 @@ int perfmon_uncore_discovery(PerfmonDiscovery** perfmon) PciDeviceIndex idx = get_likwid_device(unit.box_type, unit.box_id); if (idx >= 0 && idx < MAX_NUM_PCI_DEVICES) { - cur->units[idx].box_type = (uncore_discovery_box_types) unit.box_type; + cur->units[idx].box_type = unit.box_type; cur->units[idx].box_id = unit.box_id; cur->units[idx].num_regs = unit.num_regs; cur->units[idx].ctrl_offset = unit.ctl_offset; @@ -539,14 +550,22 @@ int perfmon_uncore_discovery(PerfmonDiscovery** perfmon) cur->units[idx].filter_offset = 0x0; cur->units[idx].fixed_ctrl_offset = 0x0; cur->units[idx].fixed_ctr_offset = 0x0; - if (unit.box_type == DEVICE_ID_CHA) + switch (model) { - cur->units[idx].filter_offset = 0xE; - } - else if (unit.box_type == DEVICE_ID_iMC || unit.box_type == DEVICE_ID_HBM) - { - cur->units[idx].fixed_ctrl_offset = 0x54; - cur->units[idx].fixed_ctr_offset = 0x38; + case SAPPHIRERAPIDS: + case GRANITERAPIDS: + if (unit.box_type == SPR_DEVICE_ID_CHA) + { + cur->units[idx].filter_offset = 0xE; + } + else if (unit.box_type == SPR_DEVICE_ID_iMC || (unit.box_type == SPR_DEVICE_ID_HBM && model == SAPPHIRERAPIDS)) + { + cur->units[idx].fixed_ctrl_offset = 0x54; + cur->units[idx].fixed_ctr_offset = 0x38; + } + break; + default: + break; } cur->units[idx].mmap_addr = cur->units[idx].box_ctl & ~(PAGE_SIZE - 1); @@ -558,10 +577,8 @@ int perfmon_uncore_discovery(PerfmonDiscovery** perfmon) } /* Unmap PCI config space */ munmap(io_addr, UNCORE_DISCOVERY_MAP_SIZE); - } - else - { - DEBUG_PRINT(DEBUGLEV_DEVELOP, not the right dvsec); + io_addr = NULL; + socket_id++; } } /* printf("Add M2IOSF devices \n");*/ @@ -583,15 +600,10 @@ int perfmon_uncore_discovery(PerfmonDiscovery** perfmon) /* cur->units[idx].fixed_ctr_offset = 0x0;*/ /* print_unit(idx, &cur->units[idx]);*/ /* }*/ - num++; - } - if (num == 0) - { - ERROR_PRINT(Failed to get any socket device tables); - return -EFAULT; } + if (dev) free(dev); close(pcihandle); - perf->num_sockets = num; + perf->num_sockets = socket_id+1; *perfmon = perf; return 0; } @@ -607,7 +619,7 @@ void perfmon_uncore_discovery_free(PerfmonDiscovery* perfmon) { if (perfmon->sockets[i].units[j].io_addr) { - munmap(perfmon->sockets[i].units[j].io_addr, perfmon->sockets[i].units[j].mmap_size); + munmap((void*)perfmon->sockets[i].units[j].io_addr, perfmon->sockets[i].units[j].mmap_size); perfmon->sockets[i].units[j].io_addr = NULL; } } diff --git a/src/perfgroup.c b/src/perfgroup.c index f3c1385ea..4649904cb 100644 --- a/src/perfgroup.c +++ b/src/perfgroup.c @@ -775,7 +775,7 @@ int perfgroup_customGroup(const char* eventStr, GroupInfo* ginfo) i++; } if ((!has_fix3) && cpuid_info.perf_num_fixed_ctr > 3 && - (cpuid_info.model == ICELAKE1 || cpuid_info.model == ICELAKE2 || cpuid_info.model == ICELAKEX1 || cpuid_info.model == ICELAKEX2 || cpuid_info.model == ROCKETLAKE || cpuid_info.model == SAPPHIRERAPIDS || cpuid_info.model == TIGERLAKE1 || cpuid_info.model == TIGERLAKE2)) + (cpuid_info.model == ICELAKE1 || cpuid_info.model == ICELAKE2 || cpuid_info.model == ICELAKEX1 || cpuid_info.model == ICELAKEX2 || cpuid_info.model == ROCKETLAKE || cpuid_info.model == SAPPHIRERAPIDS || cpuid_info.model == TIGERLAKE1 || cpuid_info.model == TIGERLAKE2 || cpuid_info.model == GRANITERAPIDS)) { ginfo->events[i] = malloc(14 * sizeof(char)); ginfo->counters[i] = malloc(6 * sizeof(char)); diff --git a/src/perfmon.c b/src/perfmon.c index 2322b50a5..5f57306f5 100644 --- a/src/perfmon.c +++ b/src/perfmon.c @@ -89,6 +89,8 @@ #include #include #include +#include +#include #ifdef LIKWID_USE_PERFEVENT #include @@ -777,6 +779,7 @@ perfmon_check_counter_map(int cpu_id) own_hpm = 1; } #endif + DEBUG_PRINT(DEBUGLEV_DEVELOP, Checking %d counters, perfmon_numCounters); int startpmcindex = -1; for (int i=0;ientry[j], bkey) == BSTR_OK) + if (bstrncmp(xlist->entry[j], bkey, blength(xlist->entry[j])) == BSTR_OK) { + DEBUG_PRINT(DEBUGLEV_DEVELOP, Checking counter %s (device %d, HWThread %d), bdata(bkey), counter_map[k].device, cpu_id); #ifndef LIKWID_USE_PERFEVENT if (HPMcheck(counter_map[k].device, cpu_id)) #else @@ -1619,6 +1647,7 @@ perfmon_init_maps(void) perfmon_numArchEvents++; added_generic_event = 1; } + DEBUG_PRINT(DEBUGLEV_DEVELOP, Adding GENERIC_EVENT done); } return err; @@ -1865,6 +1894,28 @@ perfmon_init_funcs(int* init_power, int* init_temp) perfmon_finalizeCountersThread = perfmon_finalizeCountersThread_sapphirerapids; break; + case GRANITERAPIDS: + initialize_power = TRUE; + initialize_thermal = TRUE; + initThreadArch = perfmon_init_graniterapids; + perfmon_startCountersThread = perfmon_startCountersThread_graniterapids; + perfmon_stopCountersThread = perfmon_stopCountersThread_graniterapids; + perfmon_readCountersThread = perfmon_readCountersThread_graniterapids; + perfmon_setupCountersThread = perfmon_setupCounterThread_graniterapids; + perfmon_finalizeCountersThread = perfmon_finalizeCountersThread_graniterapids; + break; + + case SIERRAFORREST: + initialize_power = TRUE; + initialize_thermal = TRUE; + initThreadArch = perfmon_init_sierraforrest; + perfmon_startCountersThread = perfmon_startCountersThread_sierraforrest; + perfmon_stopCountersThread = perfmon_stopCountersThread_sierraforrest; + perfmon_readCountersThread = perfmon_readCountersThread_sierraforrest; + perfmon_setupCountersThread = perfmon_setupCounterThread_sierraforrest; + perfmon_finalizeCountersThread = perfmon_finalizeCountersThread_sierraforrest; + break; + default: ERROR_PLAIN_PRINT(Unsupported Processor); err = -EINVAL; diff --git a/src/power.c b/src/power.c index b223925fa..85442355e 100644 --- a/src/power.c +++ b/src/power.c @@ -141,6 +141,8 @@ power_init(int cpuId) case ICELAKEX1: case ICELAKEX2: case SAPPHIRERAPIDS: + case GRANITERAPIDS: + case SIERRAFORREST: core_limits = 1; power_info.hasRAPL = 1; numDomains = NUM_POWER_DOMAINS; @@ -406,7 +408,8 @@ power_init(int cpuId) (cpuid_info.model == ICELAKEX2) || (cpuid_info.model == SAPPHIRERAPIDS) || (cpuid_info.model == XEON_PHI_KNL) || - (cpuid_info.model == XEON_PHI_KML))) + (cpuid_info.model == XEON_PHI_KML) || + (cpuid_info.model == GRANITERAPIDS))) { power_info.domains[DRAM].energyUnit = 15.3E-6; } diff --git a/src/topology.c b/src/topology.c index e7bbcea35..2c8f66c23 100644 --- a/src/topology.c +++ b/src/topology.c @@ -94,6 +94,8 @@ static char* tigerlake_str = "Intel Tigerlake processor"; static char* icelakesp_str = "Intel Icelake SP processor"; static char* rocketlake_str = "Intel Rocketlake processor"; static char* sapphire_rapids_str = "Intel SapphireRapids processor"; +static char* granite_rapids_str = "Intel GraniteRapids processor"; +static char* sierra_forrest_str = "Intel SierraForrest processor"; //static char* snowridgex_str = "Intel SnowridgeX processor"; static char* barcelona_str = "AMD K10 (Barcelona) processor"; @@ -170,6 +172,8 @@ static char* short_phi2 = "knl"; static char* short_icelake = "ICL"; static char* short_rocketlake = "RKL"; static char* short_icelakesp = "ICX"; +static char* short_granite_rapids = "GNR"; +static char* short_sierra_forrest = "SRF"; //static char* short_snowridgex = "SNR"; static char* short_k8 = "k8"; @@ -1078,6 +1082,20 @@ topology_setName(void) cpuid_info.short_name = short_sapphire_rapids; break; + case GRANITERAPIDS: + cpuid_info.supportUncore = 1; + cpuid_info.supportClientmem = 0; + cpuid_info.name = granite_rapids_str; + cpuid_info.short_name = short_granite_rapids; + break; + + case SIERRAFORREST: + cpuid_info.supportUncore = 0; + cpuid_info.supportClientmem = 0; + cpuid_info.name = sierra_forrest_str; + cpuid_info.short_name = short_sierra_forrest; + break; + default: err = -EFAULT; break;