From fa4d202a2449bf018baefbfe580b1a7d6b6f3930 Mon Sep 17 00:00:00 2001
From: Sleigh-InSPECtor <sleighinspector@outlook.com>
Date: Tue, 30 Jul 2024 20:35:48 +0930
Subject: [PATCH] [msp430] MOV, MOVX, MOVA, and BRA @Rn+ do not correctly order
 opperations

---
 .../TI_MSP430/data/languages/TI430Common.sinc | 16 ++++++----
 .../TI_MSP430/data/languages/TI430X.sinc      | 32 +++++++++++--------
 2 files changed, 29 insertions(+), 19 deletions(-)

diff --git a/Ghidra/Processors/TI_MSP430/data/languages/TI430Common.sinc b/Ghidra/Processors/TI_MSP430/data/languages/TI430Common.sinc
index 91839185239..f67e56fab79 100644
--- a/Ghidra/Processors/TI_MSP430/data/languages/TI430Common.sinc
+++ b/Ghidra/Processors/TI_MSP430/data/languages/TI430Common.sinc
@@ -886,22 +886,26 @@ OFFSET_10BIT: offset10 is off16   [offset10 = inst_start + 2 + off16 * 2; ]
 #------------------
 #	SRC Word
 #------------------
-:MOV^".W" SRC_W_AS, DEST_W_AD is ctx_haveext=0 & (op16_12_4=0x4 & bow=0x0 & tbl_wzero & postIncrementStore) ... & SRC_W_AS ... & DEST_W_AD ... {
-	DEST_W_AD = SRC_W_AS;
+:MOV^".W" SRC_W_AS, DEST_W_AD is ctx_haveext=0 & (op16_12_4=0x4 & bow=0x0 & tbl_wzero & postIncrement & postStorePC) ... & SRC_W_AS ... & DEST_W_AD ... {
+	local tmp:2 = SRC_W_AS;
+	build postIncrement;
+	DEST_W_AD = tmp;
 	build tbl_wzero;
 	#Status bits are not affected
-	build postIncrementStore;
+	build postStorePC;
 }
 
 
 #------------------
 #   SRC Byte
 #------------------
-:MOV^".B" SRC_B_AS, DEST_B_AD is ctx_haveext=0 & (op16_12_4=0x4 & bow=0x1 & tbl_bzero & postIncrementStore) ... & SRC_B_AS ... & DEST_B_AD ... {
-	DEST_B_AD = SRC_B_AS;
+:MOV^".B" SRC_B_AS, DEST_B_AD is ctx_haveext=0 & (op16_12_4=0x4 & bow=0x1 & tbl_bzero & postIncrement & postStorePC) ... & SRC_B_AS ... & DEST_B_AD ... {
+	local tmp:1 = SRC_B_AS;
+	build postIncrement;
+	DEST_B_AD = tmp;
 	build tbl_bzero;
 	#Status bits are not affected
-	build postIncrementStore;
+	build postStorePC;
 }
 
 
diff --git a/Ghidra/Processors/TI_MSP430/data/languages/TI430X.sinc b/Ghidra/Processors/TI_MSP430/data/languages/TI430X.sinc
index 48e812d6053..b809311c71c 100644
--- a/Ghidra/Processors/TI_MSP430/data/languages/TI430X.sinc
+++ b/Ghidra/Processors/TI_MSP430/data/languages/TI430X.sinc
@@ -921,9 +921,9 @@ macro adda(dst, src) {
 }
 
 :MOVA "@"^SRC20_8_4^"+", DST20_0_4			is ctx_haveext=0 & op16_12_4=0 & insid=0x1 & SRC20_8_4 & DST20_0_4 {
-	DST20_0_4 = *[RAM]:$(REG_SIZE) SRC20_8_4 & ~1;
-	DST20_0_4 = sext(DST20_0_4[0,20]);
+	local tmp = *[RAM]:$(REG_SIZE) SRC20_8_4 & ~1;
 	SRC20_8_4 = SRC20_8_4 + 4;
+	DST20_0_4 = zext(tmp[0,20]);
 }
 
 :MOVA "&"^Abs20, DST20_0_4				is ctx_haveext=0 & op16_12_4=0 & insid=0x2 & imm_8_4 & DST20_0_4 ; Abs20 [ctx_ctregdest=imm_8_4;] {
@@ -1029,9 +1029,9 @@ macro suba(dst, src) {
 }
 
 :BRA "@"^SRC20_8_4^"+" 				is ctx_haveext=0 & op16_12_4=0 & insid=0x1 & SRC20_8_4 & dest_0_4=0x0 {
-	PC = *[RAM]:$(REG_SIZE) SRC20_8_4 & 0xffffe;
+	local tmp = *[RAM]:$(REG_SIZE) SRC20_8_4 & 0xffffe;
 	SRC20_8_4 = SRC20_8_4 + 4;
-	goto [PC];
+	goto [tmp];
 }
 
 :BRA "&"^Abs20						is ctx_haveext=0 & op16_12_4=0 & insid=0x2 & imm_8_4 & dest_0_4=0x0; Abs20 [ctx_ctregdest=imm_8_4;] {
@@ -2968,23 +2968,29 @@ define pcodeop bcd_add;
 	build postIncrementStore;
 }
 
-:MOVX.B	XSRC_B_AS, XDEST_B_AD			is ctx_haveext=7 & ctx_al=1 & (op16_12_4=0x4 & bow=1 & tbl_bzero & postIncrementStore) ... & XSRC_B_AS ... & XDEST_B_AD ...  {
-	XDEST_B_AD = XSRC_B_AS;
+:MOVX.B	XSRC_B_AS, XDEST_B_AD			is ctx_haveext=7 & ctx_al=1 & (op16_12_4=0x4 & bow=1 & tbl_bzero & postIncrement & postStorePC) ... & XSRC_B_AS ... & XDEST_B_AD ...  {
+	local tmp:1 = XSRC_B_AS;
+	build postIncrement;
+	XDEST_B_AD = tmp;
 	build tbl_bzero;
 	#Status bits are not affected
-	build postIncrementStore;
+	build postStorePC;
 }
 
-:MOVX.W	XSRC_W_AS, XDEST_W_AD			is ctx_haveext=7 & ctx_al=1 & (op16_12_4=0x4 & bow=0 & tbl_wzero & postIncrementStore) ... & XSRC_W_AS ... & XDEST_W_AD ... {
-	XDEST_W_AD = XSRC_W_AS;
+:MOVX.W	XSRC_W_AS, XDEST_W_AD			is ctx_haveext=7 & ctx_al=1 & (op16_12_4=0x4 & bow=0 & tbl_wzero & postIncrement & postStorePC) ... & XSRC_W_AS ... & XDEST_W_AD ... {
+	local tmp:2 = XSRC_W_AS;
+	build postIncrement;
+	XDEST_W_AD = tmp;
 	build tbl_wzero;
 	#Status bits are not affected
-	build postIncrementStore;
+	build postStorePC;
 }
 
-:MOVX.A	XSRC_A_AS, XDEST_A_AD			is ctx_haveext=7 & ctx_al=0 & (op16_12_4=0x4 & bow=1 & postIncrementStore) ... & XSRC_A_AS ... & XDEST_A_AD ... {
-	XDEST_A_AD = XSRC_A_AS & 0xfffff;
-	build postIncrementStore;
+:MOVX.A	XSRC_A_AS, XDEST_A_AD			is ctx_haveext=7 & ctx_al=0 & (op16_12_4=0x4 & bow=1 & postIncrement & postStorePC) ... & XSRC_A_AS ... & XDEST_A_AD ... {
+	local tmp:$(REG_SIZE) = XSRC_A_AS & 0xfffff;
+	build postIncrement;
+	XDEST_A_AD = tmp;
+	build postStorePC;
 }
 
 :POPX.B	XDEST_B_AD						is ctx_haveext=7 & ctx_al=1 & (op16_12_4=0x4 & src16_8_4=0x1 & as=0x3 & bow=1 & tbl_bzero) ... & XDEST_B_AD ...  {