rcw: add config for serdes 1 protocol 4, not (yet) supported on clear…

…fog-cx
SolidRun · Nov 7, 2024 · 5711ecb · 5711ecb
1 parent 3d4a839
commit 5711ecb
Showing 1 changed file with 50 additions and 0 deletions.
diff --git a/patches/rcw/0017-lx2160acex7-add-configuration-for-serdes-1-protocol-.patch b/patches/rcw/0017-lx2160acex7-add-configuration-for-serdes-1-protocol-.patch
@@ -0,0 +1,50 @@
+From 0d1aa31950f78d41c67a9e63b65c7102e14df1f4 Mon Sep 17 00:00:00 2001
+From: Josua Mayer <josua@solid-run.com>
+Date: Wed, 6 Nov 2024 11:18:12 +0100
+Subject: [PATCH] lx2160acex7: add configuration for serdes 1 protocol 4
+
+This configuration can boot, but currently leads to issues on
+clearfog-cx in linux.
+Therefore no board configuration has been added beyond the include.
+
+Signed-off-by: Josua Mayer <josua@solid-run.com>
+---
+ lx2160acex7/include/SD1_4.rcwi | 26 ++++++++++++++++++++++++++
+ 1 file changed, 26 insertions(+)
+ create mode 100644 lx2160acex7/include/SD1_4.rcwi
+
+diff --git a/lx2160acex7/include/SD1_4.rcwi b/lx2160acex7/include/SD1_4.rcwi
+new file mode 100644
+index 0000000..20de437
+--- /dev/null
++++ b/lx2160acex7/include/SD1_4.rcwi
+@@ -0,0 +1,26 @@
++/*
++ * Serdes 1 Reference Clocks:
++ * - PLLF = 161.1328125MHz
++ * - PLLS = 100MHz
++ */
++
++/* Serdes 1 Protocol 4: 8x1Gbps */
++SRDS_PRTCL_S1=4
++
++/* Disable PLLF */
++SRDS_PLL_PD_PLL1=1
++SRDS_REFCLKF_DIS_S1=1
++
++/* Don't use PLLF for PLLS */
++SRDS_INTRA_REF_CLK_S1=0
++
++/* Enable PLLS */
++SRDS_PLL_PD_PLL2=1
++SRDS_REFCLKF_DIS_S2=0
++
++/*
++ * Select PLLF frequency 100MHz (don't care): Bit 0 = 0
++ * Select PLLS frequency 100MHz: Bit 1 = 0
++ * (See QorIQ LX2160A Reference Manual, Rev. 0, 07/2020, 4.9.8.9 Reset Control Word (RCW) Register Descriptions, Bits 932-933)
++ */
++SRDS_PLL_REF_CLK_SEL_S1=0
+-- 
+2.43.0
+