From c5cc62871e5498c5ba46dc17a37e7845a2be4dd0 Mon Sep 17 00:00:00 2001 From: Josua Mayer Date: Wed, 9 Oct 2024 13:33:20 +0200 Subject: [PATCH] sync with lx2160a_build / generate multi-boot images for SD, eMMC, SPI Signed-off-by: Josua Mayer --- .github/workflows/build.yml | 17 +- README.md | 69 +- conf/machine/lx2160acex7.conf | 9 +- ...t-for-generating-images-without-part.patch | 73 ++ .../0001-plat-nxp-lx2160a-auto-boot.patch | 219 +++++ ...ccount-MEM_PLL_CFG_SHIFT-for-ddr-fre.patch | 85 ++ recipes-bsp/atf/qoriq-atf_2.6.bbappend | 8 + ...-MEM_PLL_CFG-into-ddr-speed-specific.patch | 112 +++ ...separate-configurations-for-flexspi-.patch | 894 ++++++++++++++++++ ...me-sdhc1-config-to-generic-sdhc-for-.patch | 149 +++ ...c-jumpc-and-jump-to-pbi-instructions.patch | 55 ++ ...add-configuration-for-both-sdhc-xspi.patch | 836 ++++++++++++++++ ...ootlocptr-reduce-size-of-pbi-section.patch | 90 ++ ...ge-2.2GHz-configuration-platform-clo.patch | 475 ++++++++++ ...configuration-for-fraction-ddr-speed.patch | 420 ++++++++ recipes-bsp/rcw/rcw_git.bbappend | 8 + ...-calculation-of-ddr-clock-rate-to-in.patch | 63 ++ .../u-boot/u-boot-qoriq_2022.04.bbappend | 1 + ...g-sd.wks.in => lx2160a-bootimg-mmc.wks.in} | 10 +- wic/lx2160a-bootimg-xspi.wks.in | 22 + wic/lx2160a-rootimg.wks.in | 17 + 21 files changed, 3613 insertions(+), 19 deletions(-) create mode 100644 patches/poky/0001-wic-add-supppport-for-generating-images-without-part.patch create mode 100644 recipes-bsp/atf/qoriq-atf-2.6/0001-plat-nxp-lx2160a-auto-boot.patch create mode 100644 recipes-bsp/atf/qoriq-atf-2.6/0002-dcfg-Take-into-account-MEM_PLL_CFG_SHIFT-for-ddr-fre.patch create mode 100644 recipes-bsp/rcw/files/0002-lx2160acex7-move-MEM_PLL_CFG-into-ddr-speed-specific.patch create mode 100644 recipes-bsp/rcw/files/0003-lx2160acex7-add-separate-configurations-for-flexspi-.patch create mode 100644 recipes-bsp/rcw/files/0004-lx2160acex7-rename-sdhc1-config-to-generic-sdhc-for-.patch create mode 100644 recipes-bsp/rcw/files/0005-add-loadc-jumpc-and-jump-to-pbi-instructions.patch create mode 100644 recipes-bsp/rcw/files/0006-lx2160acex7-add-configuration-for-both-sdhc-xspi.patch create mode 100644 recipes-bsp/rcw/files/0007-bootlocptr-reduce-size-of-pbi-section.patch create mode 100644 recipes-bsp/rcw/files/0008-lx2160acex7-change-2.2GHz-configuration-platform-clo.patch create mode 100644 recipes-bsp/rcw/files/0009-lx2160acex7-add-configuration-for-fraction-ddr-speed.patch create mode 100644 recipes-bsp/u-boot/2022.04-solidrun/0004-fsl-lsch3-update-calculation-of-ddr-clock-rate-to-in.patch rename wic/{lx2160a-bootimg-sd.wks.in => lx2160a-bootimg-mmc.wks.in} (77%) create mode 100644 wic/lx2160a-bootimg-xspi.wks.in create mode 100644 wic/lx2160a-rootimg.wks.in diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index aff1a11..469ac71 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -73,6 +73,13 @@ jobs: with: path: sources/meta-solidrun-arm-lx2xxx + - name: Patch dependency layers + shell: bash {0} + run: | + pushd sources/poky + git am ../../meta-solidrun-arm-lx2xxx/patches/poky/0001-wic-add-supppport-for-generating-images-without-part.patch + popd + - name: Get build tag shell: bash {0} id: tag_step @@ -125,7 +132,9 @@ jobs: export BB_ENV_PASSTHROUGH_ADDITIONS="$BB_ENV_PASSTHROUGH_ADDITIONS CACHE_DIR" export MACHINE=lx2160acex7-rev2 bitbake -k fsl-image-networking - wic create lx2160a-bootimg-sd -e fsl-image-networking + wic create lx2160a-bootimg-mmc -e fsl-image-networking + wic create lx2160a-bootimg-xspi -e fsl-image-networking + wic create lx2160a-rootimg -e fsl-image-networking continue-on-error: true - name: Update cache on the server (build may have failed) @@ -160,8 +169,10 @@ jobs: mv $DEPLOY_PATH/device-tree.tgz deploy/ cp -L $DEPLOY_PATH/Image deploy/ cp -L $DEPLOY_PATH/modules-lx2160acex7-rev2.tgz deploy/ - cp build_lx2160acex7-rev2/lx2160a-bootimg-sd.wks*.direct deploy/lx2160a-bootimg-sd.img - xz -9 deploy/lx2160a-bootimg-sd.img + cp build_lx2160acex7-rev2/lx2160a-bootimg-mmc.wks*.direct deploy/lx2160a-bootimg-mmc.img + cp build_lx2160acex7-rev2/lx2160a-bootimg-xspi.wks*.direct deploy/lx2160a-bootimg-xspi.img + cp build_lx2160acex7-rev2/lx2160a-rootimg.wks*.direct deploy/lx2160a-rootimg.img + xz -9 deploy/lx2160a-*.img ls -lh deploy/ - name: Deploy to the local minio storage diff --git a/README.md b/README.md index 0631686..f7c9833 100644 --- a/README.md +++ b/README.md @@ -9,14 +9,24 @@ Start in a **new empty directory** with plenty of free disk space - at least 30G ``` repo init -u https://github.com/nxp-qoriq/yocto-sdk.git -b kirkstone -m ls-5.15.71-2.2.0.xml repo sync - git clone https://github.com/SolidRun/meta-solidrun-arm-lx2xxx.git sources/meta-solidrun-arm-lx2xxx + git clone -b kirkstone https://github.com/SolidRun/meta-solidrun-arm-lx2xxx.git sources/meta-solidrun-arm-lx2xxx ``` -2. Initialise a build directory with example configuration files based on lx2160ardb, and appropriate shell environment variables: +2. apply downstream patches to dependent layers: + + - `poky`: add support for wic images without partition table (for xspi image) + + ``` + pushd sources/poky + git am ../../meta-solidrun-arm-lx2xxx/patches/poky/0001-wic-add-supppport-for-generating-images-without-part.patch + popd + ``` + +3. Initialise a build directory with example configuration files based on lx2160ardb, and appropriate shell environment variables: source ./setup-env -m lx2160ardb-rev2 -b build_lx2160acex7-rev2 -3. Adapt example configuration files for SolidRun LX2160A CEX7: +4. Adapt example configuration files for SolidRun LX2160A CEX7: - edit `build_lx2160acex7-rev2/conf/bblayers.conf`: @@ -35,11 +45,11 @@ Start in a **new empty directory** with plenty of free disk space - at least 30G - See below for additional configuration options. -4. Build nxp image `fsl-image-networking`: +5. Build nxp image `fsl-image-networking`: bitbake fsl-image-networking -5. Generate bootable disk image: +6. Generate bootable disk image: NXP QorIQ Layers by default do not assemble full bootable disk images, users are expected to install all components to various offsets manually. @@ -49,11 +59,26 @@ Start in a **new empty directory** with plenty of free disk space - at least 30G - SD-Card / eMMC (includes rootfs): - wic create lx2160a-bootimg-sd -e fsl-image-networking + wic create lx2160a-bootimg-mmc -e fsl-image-networking - This generates a bootable disk image named `lx2160a-bootimg-sd.wks--mmcblk.direct` that is suitable + This generates a bootable disk image named `lx2160a-bootimg-mmc.wks--mmcblk.direct` that is suitable for writing to SD-Card or eMMC data partition, from the previously built `fsl-image-networking` target. + - SPI Flash (without rootfs): + + wic create lx2160a-bootimg-xspi -e fsl-image-networking + + This generates a bootable spi flash image named `lx2160a-bootimg-xspi.wks--mmcblk.direct` that is suitable + for writing to SPI flash, from the previously built `fsl-image-networking` target's bootloader parts. + + - SD-Card / eMMC / USB / SATA / NVMe (rootfs only): + + wic create lx2160a-rootimg -e fsl-image-networking + + This generates a bootable disk image named `lx2160a-rootimg.wks--mmcblk.direct` that is suitable + for writing to any block storage, from the previously built `fsl-image-networking`. + It comes with kernel + rootfs only, use on separate media, together with an SD or SPI boot image. + Note: The build environment and ability to run `bitbake` is lost when closing the terminal or rebooting. It can be restored at any time by entering the build directory and sourcing the aut-generated `SOURCE_THIS` file: @@ -79,6 +104,7 @@ DDR Clock can be configured in local.conf using `LX2160A_DDR_SPEED`, supported v - `2400` - `2600` +- `2666` - `2900` only for LX2162A, and LX2160A binned 2GHz and higher (default) - `3200` only for LX2160A binned 2.2GHz @@ -94,6 +120,35 @@ CPU (Cortex A72) Clock can be configured in local.conf using `LX2160A_CPU_SPEED` Bus clock can be configured in local.conf using `LX2160A_BUS_SPEED`, supported values are: - `700` only for LX2160A binned 2GHz and higher (default) +- `750` (for over-clocking, or for specifically purchased 2.2GHz binned SoC) + +## Known Issues + +## Failed to spawn fakeroot worker: [Errno 32] Broken pipe + +On systems with glibc newer than 2.36 builds will fail when either: + +- libfakeroot had been built against glibc later than 2.36 +- host system glibc is later than 2.36 + +Yocto uninative package can be updated for glibc-2.40 by cherry-picking a few commits from yocto kirkstone branch into NXPs BSP: + + cd bsp/sources/poky + git cherry-pick 2890968bbce028efc47a19213f4eff2ccaf7b979 + git cherry-pick bba090696873805e44b1f7b3278ef8369763a176 + git cherry-pick aab6fc20de9473d8d7f277332601cbae70c53320 + git cherry-pick 43b94d2b8496eae6e512c6deb291b5908b7ada47 + git cherry-pick b8fded3df36ab206eaf3bc25b75acda2544679c5 + git cherry-pick b4b545cd9d3905253c398a6a42a9bc13c42073be + git cherry-pick ad9420b072896b6a58a571c8123bcb17a813a1e7 + git cherry-pick 529c7c30e6a1b7e1e8a5ba5ba70b8f2f2af770ec + git cherry-pick b36affbe96b2f9063f75e11f64f5a8ead1cb5c55 + git cherry-pick 8190d9c754c9c3a1962123e1e86d99de96c1224c + +Cache must also be cleared before the next build can succeed: + + cd bsp/build + rm -rf tmp sstate-cache cache ## Maintainer Notes diff --git a/conf/machine/lx2160acex7.conf b/conf/machine/lx2160acex7.conf index 2338840..8055572 100644 --- a/conf/machine/lx2160acex7.conf +++ b/conf/machine/lx2160acex7.conf @@ -34,10 +34,11 @@ LX2160A_CPU_SPEED ?= "2000" LX2160A_DDR_SPEED ?= "2900" UEFI_XSPIBOOT ?= "LX2160ARDB_EFI_NORBOOT.fd" -BOOTTYPE ?= "flexspi_nor sd emmc" -RCWXSPI ?= "clearfog-cx/rcw_${LX2160A_CPU_SPEED}_${LX2160A_BUS_SPEED}_${LX2160A_DDR_SPEED}_8_5_2" -RCWSD ?= "clearfog-cx/rcw_${LX2160A_CPU_SPEED}_${LX2160A_BUS_SPEED}_${LX2160A_DDR_SPEED}_8_5_2" -RCWEMMC ?= "clearfog-cx/rcw_${LX2160A_CPU_SPEED}_${LX2160A_BUS_SPEED}_${LX2160A_DDR_SPEED}_8_5_2" +BOOTTYPE ?= "flexspi_nor sd emmc auto" +RCWXSPI ?= "clearfog-cx/rcw_${LX2160A_CPU_SPEED}_${LX2160A_BUS_SPEED}_${LX2160A_DDR_SPEED}_8_5_2_xspi" +RCWSD ?= "clearfog-cx/rcw_${LX2160A_CPU_SPEED}_${LX2160A_BUS_SPEED}_${LX2160A_DDR_SPEED}_8_5_2_sdhc" +RCWEMMC ?= "clearfog-cx/rcw_${LX2160A_CPU_SPEED}_${LX2160A_BUS_SPEED}_${LX2160A_DDR_SPEED}_8_5_2_sdhc" +RCWAUTO ?= "clearfog-cx/rcw_${LX2160A_CPU_SPEED}_${LX2160A_BUS_SPEED}_${LX2160A_DDR_SPEED}_8_5_2_auto" EXTRA_IMAGEDEPENDS += "management-complex mc-utils rcw ls2-phy ddr-phy uefi qoriq-atf inphi" USE_VT = "0" diff --git a/patches/poky/0001-wic-add-supppport-for-generating-images-without-part.patch b/patches/poky/0001-wic-add-supppport-for-generating-images-without-part.patch new file mode 100644 index 0000000..13550be --- /dev/null +++ b/patches/poky/0001-wic-add-supppport-for-generating-images-without-part.patch @@ -0,0 +1,73 @@ +From 4cf3e6792e76c0e2fdc04e9831cd45f2896d22dd Mon Sep 17 00:00:00 2001 +From: Josua Mayer +Date: Wed, 9 Oct 2024 15:18:25 +0200 +Subject: [PATCH] wic: add supppport for generating images without partition + table + +Wic wks files are great for laying out various pieces that go at +offsets or partitions into bootable images not just for standard sotrgae +devices using partition tables - but also for spi flash or emmc boot +partitions which in itself do not have any traditional partition tables. + +Add support for 'bootloader --ptable none' to generate imaegs without a +partition table at sector 0 - neither mbr nor gpt. +This is particularly useful for putting blobs at the first sector. + +Signed-off-by: Josua Mayer +--- + scripts/lib/wic/ksparser.py | 2 +- + scripts/lib/wic/plugins/imager/direct.py | 17 ++++++++++------- + 2 files changed, 11 insertions(+), 8 deletions(-) + +diff --git a/scripts/lib/wic/ksparser.py b/scripts/lib/wic/ksparser.py +index 0df9eb0d05..d26bb05251 100644 +--- a/scripts/lib/wic/ksparser.py ++++ b/scripts/lib/wic/ksparser.py +@@ -190,7 +190,7 @@ class KickStart(): + bootloader = subparsers.add_parser('bootloader') + bootloader.add_argument('--append') + bootloader.add_argument('--configfile') +- bootloader.add_argument('--ptable', choices=('msdos', 'gpt'), ++ bootloader.add_argument('--ptable', choices=('msdos', 'gpt', 'none'), + default='msdos') + bootloader.add_argument('--timeout', type=int) + bootloader.add_argument('--source') +diff --git a/scripts/lib/wic/plugins/imager/direct.py b/scripts/lib/wic/plugins/imager/direct.py +index 4d0b836ef6..c873e72848 100644 +--- a/scripts/lib/wic/plugins/imager/direct.py ++++ b/scripts/lib/wic/plugins/imager/direct.py +@@ -401,6 +401,8 @@ class PartitionedImage(): + overhead = MBR_OVERHEAD + elif self.ptable_format == "gpt": + overhead = GPT_OVERHEAD ++ else: ++ overhead = 0 + + # Skip one sector required for the partitioning scheme overhead + self.offset += overhead +@@ -509,14 +511,15 @@ class PartitionedImage(): + with open(self.path, 'w') as sparse: + os.ftruncate(sparse.fileno(), self.min_size) + +- logger.debug("Initializing partition table for %s", self.path) +- exec_native_cmd("parted -s %s mklabel %s" % +- (self.path, self.ptable_format), self.native_sysroot) ++ if self.ptable_format != "none": ++ logger.debug("Initializing partition table for %s", self.path) ++ exec_native_cmd("parted -s %s mklabel %s" % ++ (self.path, self.ptable_format), self.native_sysroot) + +- logger.debug("Set disk identifier %x", self.identifier) +- with open(self.path, 'r+b') as img: +- img.seek(0x1B8) +- img.write(self.identifier.to_bytes(4, 'little')) ++ logger.debug("Set disk identifier %x", self.identifier) ++ with open(self.path, 'r+b') as img: ++ img.seek(0x1B8) ++ img.write(self.identifier.to_bytes(4, 'little')) + + logger.debug("Creating partitions") + +-- +2.43.0 + diff --git a/recipes-bsp/atf/qoriq-atf-2.6/0001-plat-nxp-lx2160a-auto-boot.patch b/recipes-bsp/atf/qoriq-atf-2.6/0001-plat-nxp-lx2160a-auto-boot.patch new file mode 100644 index 0000000..4b47054 --- /dev/null +++ b/recipes-bsp/atf/qoriq-atf-2.6/0001-plat-nxp-lx2160a-auto-boot.patch @@ -0,0 +1,219 @@ +From 5d13f425bd0dea29912bf253a7be83a7cdca591d Mon Sep 17 00:00:00 2001 +From: Rabeeh Khoury +Date: Sun, 28 Nov 2021 14:00:07 +0200 +Subject: [PATCH] plat/nxp: lx2160a auto boot + +This patch adds support to patch RCW that already has SD/eMMC/SPI boot +support embedded with conditional load and jump. +The idea is to look for SD/eMMC/SPI boot, and modify src/dst/size +address with the correct values; rather than adding blockread at the end +of RCW code. + +With this patch images are unified and can be used to boot from SD / +eMMC and SPI. + +Signed-off-by: Rabeeh Khoury +--- + .../plat_make_helper/plat_common_def.mk | 5 ++ + plat/nxp/soc-lx2160a/lx2160ardb/platform.mk | 3 +- + plat/nxp/soc-lx2160a/soc.mk | 5 ++ + tools/nxp/create_pbl/create_pbl.c | 74 ++++++++++++++++--- + 4 files changed, 76 insertions(+), 11 deletions(-) + +diff --git a/plat/nxp/common/plat_make_helper/plat_common_def.mk b/plat/nxp/common/plat_make_helper/plat_common_def.mk +index 86dacf83d..a1038a073 100644 +--- a/plat/nxp/common/plat_make_helper/plat_common_def.mk ++++ b/plat/nxp/common/plat_make_helper/plat_common_def.mk +@@ -91,6 +91,11 @@ define add_boot_mode_define + else ifeq ($(1),flexspi_nor) + $$(eval $$(call SET_NXP_MAKE_FLAG,XSPI_NEEDED,BL2)) + $$(eval $$(call add_define,FLEXSPI_NOR_BOOT)) ++ else ifeq ($(1),auto) ++ $$(eval $$(call SET_FLAG,SD_MMC_NEEDED,BL2)) ++ $$(eval $$(call add_define,EMMC_BOOT)) ++ $$(eval $$(call SET_FLAG,XSPI_NEEDED,BL2)) ++ $$(eval $$(call add_define,FLEXSPI_NOR_BOOT)) + else + $$(error $(PLAT) Cannot Support Boot Mode: $(BOOT_MODE)) + endif +diff --git a/plat/nxp/soc-lx2160a/lx2160ardb/platform.mk b/plat/nxp/soc-lx2160a/lx2160ardb/platform.mk +index ffb5fadee..09c552c72 100644 +--- a/plat/nxp/soc-lx2160a/lx2160ardb/platform.mk ++++ b/plat/nxp/soc-lx2160a/lx2160ardb/platform.mk +@@ -42,7 +42,8 @@ BL2_SOURCES += ${BOARD_PATH}/ddr_init.c\ + + SUPPORTED_BOOT_MODE := flexspi_nor \ + sd \ +- emmc ++ emmc \ ++ auto + + # Adding platform board build info + include plat/nxp/common/plat_make_helper/plat_common_def.mk +diff --git a/plat/nxp/soc-lx2160a/soc.mk b/plat/nxp/soc-lx2160a/soc.mk +index 239442c20..a72b4113d 100644 +--- a/plat/nxp/soc-lx2160a/soc.mk ++++ b/plat/nxp/soc-lx2160a/soc.mk +@@ -82,6 +82,11 @@ else + ifeq (${BOOT_MODE}, emmc) + $(eval $(call SET_NXP_MAKE_FLAG,SD_MMC_NEEDED,BL2)) + $(eval $(call add_define,EMMC_BOOT)) ++else ifeq (${BOOT_MODE}, auto) ++$(eval $(call SET_NXP_MAKE_FLAG,SD_MMC_NEEDED,BL2)) ++$(eval $(call add_define,EMMC_BOOT)) ++$(eval $(call SET_NXP_MAKE_FLAG,XSPI_NEEDED,BL2)) ++$(eval $(call add_define,FLEXSPI_NOR_BOOT)) + else + $(error Un-supported Boot Mode = ${BOOT_MODE}) + endif +diff --git a/tools/nxp/create_pbl/create_pbl.c b/tools/nxp/create_pbl/create_pbl.c +index 792747f0e..35cd39b61 100644 +--- a/tools/nxp/create_pbl/create_pbl.c ++++ b/tools/nxp/create_pbl/create_pbl.c +@@ -66,6 +66,7 @@ typedef enum { + FLXSPI_NOR_BOOT, + FLXSPI_NAND_BOOT, + FLXSPI_NAND4K_BOOT, ++ AUTO_BOOT, + MAX_BOOT /* must be last item in list */ + } boot_src_t; + +@@ -140,6 +141,7 @@ char *boot_src_string[] = { + "FLXSPI_NOR_BOOT", + "FLXSPI_NAND_BOOT", + "FLXSPI_NAND4K_BOOT", ++ "AUTO_BOOT", + }; + + enum stop_command { +@@ -193,7 +195,7 @@ struct pbl_image { + #define SOC_LS2088 2088 + #define SOC_LX2160 2160 + +-static uint32_t pbl_size; ++static uint32_t pbl_size = 0; + bool sb_flag; + + /*************************************************************************** +@@ -703,6 +705,8 @@ int main(int argc, char **argv) + int ret = FAILURE; + bool bootptr_flag = false; + enum stop_command flag_stop_cmd = CRC_STOP_COMMAND; ++ int skip = 0; ++ uint32_t saved_src; + + /* Initializing the global structure to zero. */ + memset(&pblimg, 0x0, sizeof(struct pbl_image)); +@@ -802,6 +806,8 @@ int main(int argc, char **argv) + pblimg.boot_src = FLXSPI_NAND_BOOT; + } else if (strcmp(optarg, "flexspi_nand2k") == 0) { + pblimg.boot_src = FLXSPI_NAND4K_BOOT; ++ } else if (strcmp(optarg, "auto") == 0) { ++ pblimg.boot_src = AUTO_BOOT; + } else { + printf("CMD Error: Invalid boot source.\n"); + goto exit_main; +@@ -909,13 +915,14 @@ int main(int argc, char **argv) + printf("%s: Error reading PBI Cmd.\n", __func__); + goto exit_main; + } ++ saved_src = pblimg.src_addr; + while (word != 0x808f0000 && word != 0x80ff0000) { + pbl_size++; + /* 11th words in RCW has PBL length. Update it + * with new length. 2 comamnds get added + * Block copy + CCSR Write/CSF header write + */ +- if (pbl_size == 11) { ++ if ((pbl_size == 11) && (pblimg.boot_src != AUTO_BOOT)) { + word_1 = (word & PBI_LEN_MASK) + + (PBI_LEN_ADD << 20); + word = word & ~PBI_LEN_MASK; +@@ -933,8 +940,50 @@ int main(int argc, char **argv) + goto exit_main; + } + } +- if (fwrite(&word, sizeof(word), NUM_MEM_BLOCK, +- fp_rcw_pbi_op) != NUM_MEM_BLOCK) { ++ if (pblimg.boot_src == AUTO_BOOT) { ++ if (word == 0x80000008) { ++ printf ("Found SD boot at %d\n",pbl_size); ++ pblimg.boot_src = SD_BOOT; ++ add_blk_cpy_cmd(fp_rcw_pbi_op, args); ++ skip = 4; // skip original blockcopy ++ pblimg.boot_src = AUTO_BOOT; ++ pblimg.src_addr = saved_src; ++ if (bootptr_flag == true) { ++ add_boot_ptr_cmd(fp_rcw_pbi_op); ++ skip += 2; // skip original bootlocptr write (low byte only) ++ printf("added bootptr\n"); ++ } ++ } ++ if (word == 0x80000009) { ++ printf ("Found eMMC boot at %d\n",pbl_size); ++ pblimg.boot_src = EMMC_BOOT; ++ add_blk_cpy_cmd(fp_rcw_pbi_op, args); ++ skip = 4; // skip original blockcopy ++ pblimg.boot_src = AUTO_BOOT; ++ pblimg.src_addr = saved_src; ++ if (bootptr_flag == true) { ++ add_boot_ptr_cmd(fp_rcw_pbi_op); ++ skip += 2; // skip original bootlocptr write (low byte only) ++ printf("added bootptr\n"); ++ } ++ } ++ if (word == 0x8000000f) { ++ printf ("Found SPI boot at %d\n",pbl_size); ++ pblimg.boot_src = FLXSPI_NOR_BOOT; ++ add_blk_cpy_cmd(fp_rcw_pbi_op, args); ++ skip = 4; // skip original blockcopy ++ pblimg.boot_src = AUTO_BOOT; ++ pblimg.src_addr = saved_src; ++ if (bootptr_flag == true) { ++ add_boot_ptr_cmd(fp_rcw_pbi_op); ++ skip += 2; // skip original bootlocptr write (low byte only) ++ printf("added bootptr\n"); ++ } ++ } ++ } ++ if (!skip && ++ (fwrite(&word, sizeof(word), NUM_MEM_BLOCK, ++ fp_rcw_pbi_op) != NUM_MEM_BLOCK)) { + printf("%s: [CH3] Error in Writing PBI Words\n", + __func__); + goto exit_main; +@@ -951,8 +1000,11 @@ int main(int argc, char **argv) + } else if (word == STOP_CMD_ARM_CH3) { + flag_stop_cmd = STOP_COMMAND; + } ++ ++ if (skip) ++ skip--; + } +- if (bootptr_flag == true) { ++ if ((pblimg.boot_src != AUTO_BOOT) && (bootptr_flag == true)) { + /* Add command to set boot_loc ptr */ + ret = add_boot_ptr_cmd(fp_rcw_pbi_op); + if (ret != SUCCESS) { +@@ -963,11 +1015,13 @@ int main(int argc, char **argv) + } + + /* Write acs write commands to output file */ +- ret = add_blk_cpy_cmd(fp_rcw_pbi_op, args); +- if (ret != SUCCESS) { +- printf("%s: Function add_blk_cpy_cmd return failure.\n", +- __func__); +- goto exit_main; ++ if (pblimg.boot_src != AUTO_BOOT) { ++ ret = add_blk_cpy_cmd(fp_rcw_pbi_op, args); ++ if (ret != SUCCESS) { ++ printf("%s: Function add_blk_cpy_cmd return failure.\n", ++ __func__); ++ goto exit_main; ++ } + } + + /* Add stop command after adding pbi commands */ +-- +2.43.0 + diff --git a/recipes-bsp/atf/qoriq-atf-2.6/0002-dcfg-Take-into-account-MEM_PLL_CFG_SHIFT-for-ddr-fre.patch b/recipes-bsp/atf/qoriq-atf-2.6/0002-dcfg-Take-into-account-MEM_PLL_CFG_SHIFT-for-ddr-fre.patch new file mode 100644 index 0000000..9fb5de8 --- /dev/null +++ b/recipes-bsp/atf/qoriq-atf-2.6/0002-dcfg-Take-into-account-MEM_PLL_CFG_SHIFT-for-ddr-fre.patch @@ -0,0 +1,85 @@ +From f750b41bf323d04791b4b25962f693c1fb43bade Mon Sep 17 00:00:00 2001 +From: Jon Nettleton +Date: Tue, 8 Oct 2024 04:56:45 +0200 +Subject: [PATCH] dcfg: Take into account MEM_PLL_CFG_SHIFT for ddr frequency + +The base ddr clock frequency is 1/4 the speed of the final +ddr clock frequency. By default the RCW config is setting +the CFG_SHIFT to be a 1/4 divider of the memory speed, +i.e. 3200 / 4 (800MHz). The parent DDRCLK is 100MHz so PLL_RAT +needs to be rounded to 100MHz. However using a divider of / 3 for +a lower speed always us to match industry standard ddr4 speeds +2666 and 2933 (2000 / 3 * 4 = 2666.67) + +This patch takes into account the PLL_CFG_SHIFT divider so these +speeds can be configured in the RCW and then updates the helper +function that reports ddr_clk_freq to properly multiply the +clock fed into the DDRC * 4 to properly reflect the actual MTs +that the memory is being configured for. + +Signed-off-by: Jon Nettleton +--- + drivers/nxp/dcfg/dcfg.c | 6 ++++++ + drivers/nxp/ddr/nxp-ddr/utility.c | 6 +++--- + include/drivers/nxp/dcfg/dcfg_lsch3.h | 4 ++++ + 3 files changed, 13 insertions(+), 3 deletions(-) + +diff --git a/drivers/nxp/dcfg/dcfg.c b/drivers/nxp/dcfg/dcfg.c +index e5c4db437..4a5820a64 100644 +--- a/drivers/nxp/dcfg/dcfg.c ++++ b/drivers/nxp/dcfg/dcfg.c +@@ -104,9 +104,15 @@ int get_clocks(struct sysinfo *sys) + sys->freq_ddr_pll0 *= (gur_in32(rcwsr0) >> + RCWSR0_MEM_PLL_RAT_SHIFT) & + RCWSR0_MEM_PLL_RAT_MASK; ++ sys->freq_ddr_pll0 /= ((gur_in32(rcwsr0) >> ++ RCWSR0_MEM_PLL_CFG_SHIFT) & ++ RCWSR0_MEM_PLL_CFG_MASK) + 1; + sys->freq_ddr_pll1 *= (gur_in32(rcwsr0) >> + RCWSR0_MEM2_PLL_RAT_SHIFT) & + RCWSR0_MEM2_PLL_RAT_MASK; ++ sys->freq_ddr_pll1 /= ((gur_in32(rcwsr0) >> ++ RCWSR0_MEM2_PLL_CFG_SHIFT) & ++ RCWSR0_MEM2_PLL_CFG_MASK) + 1; + if (sys->freq_platform == 0) { + return 1; + } else { +diff --git a/drivers/nxp/ddr/nxp-ddr/utility.c b/drivers/nxp/ddr/nxp-ddr/utility.c +index b6dffc872..3920b4488 100644 +--- a/drivers/nxp/ddr/nxp-ddr/utility.c ++++ b/drivers/nxp/ddr/nxp-ddr/utility.c +@@ -47,11 +47,11 @@ unsigned long get_ddr_freq(struct sysinfo *sys, int ctrl_num) + + switch (ctrl_num) { + case 0: +- return sys->freq_ddr_pll0; ++ return sys->freq_ddr_pll0 * 4; + case 1: +- return sys->freq_ddr_pll0; ++ return sys->freq_ddr_pll0 * 4; + case 2: +- return sys->freq_ddr_pll1; ++ return sys->freq_ddr_pll1 * 4; + } + + return 0; +diff --git a/include/drivers/nxp/dcfg/dcfg_lsch3.h b/include/drivers/nxp/dcfg/dcfg_lsch3.h +index cde86fe19..f9409d1a7 100644 +--- a/include/drivers/nxp/dcfg/dcfg_lsch3.h ++++ b/include/drivers/nxp/dcfg/dcfg_lsch3.h +@@ -53,8 +53,12 @@ + #define RCWSR0_OFFSET 0x100 + #define RCWSR0_SYS_PLL_RAT_SHIFT 2 + #define RCWSR0_SYS_PLL_RAT_MASK 0x1f ++#define RCWSR0_MEM_PLL_CFG_SHIFT 8 ++#define RCWSR0_MEM_PLL_CFG_MASK 0x3 + #define RCWSR0_MEM_PLL_RAT_SHIFT 10 + #define RCWSR0_MEM_PLL_RAT_MASK 0x3f ++#define RCWSR0_MEM2_PLL_CFG_SHIFT 16 ++#define RCWSR0_MEM2_PLL_CFG_MASK 0x3 + #define RCWSR0_MEM2_PLL_RAT_SHIFT 18 + #define RCWSR0_MEM2_PLL_RAT_MASK 0x3f + +-- +2.43.0 + diff --git a/recipes-bsp/atf/qoriq-atf_2.6.bbappend b/recipes-bsp/atf/qoriq-atf_2.6.bbappend index 5c1cb9d..3418c28 100644 --- a/recipes-bsp/atf/qoriq-atf_2.6.bbappend +++ b/recipes-bsp/atf/qoriq-atf_2.6.bbappend @@ -1,2 +1,10 @@ +# Add this layer to SRC_URI search path +FILESEXTRAPATHS:prepend := "${THISDIR}/qoriq-atf-2.6:" + +# Add SolidRun patches +SRC_URI += "file://0001-plat-nxp-lx2160a-auto-boot.patch \ + file://0002-dcfg-Take-into-account-MEM_PLL_CFG_SHIFT-for-ddr-fre.patch \ +" + PLATFORM:lx2160acex7 = "lx2160ardb" PLATFORM:lx2160acex7-rev2 = "lx2160ardb" diff --git a/recipes-bsp/rcw/files/0002-lx2160acex7-move-MEM_PLL_CFG-into-ddr-speed-specific.patch b/recipes-bsp/rcw/files/0002-lx2160acex7-move-MEM_PLL_CFG-into-ddr-speed-specific.patch new file mode 100644 index 0000000..1c30978 --- /dev/null +++ b/recipes-bsp/rcw/files/0002-lx2160acex7-move-MEM_PLL_CFG-into-ddr-speed-specific.patch @@ -0,0 +1,112 @@ +From 9d49cf46a3fde08abd3ba48169c7688dfeed74bb Mon Sep 17 00:00:00 2001 +From: Josua Mayer +Date: Fri, 27 Sep 2024 17:58:11 +0200 +Subject: [PATCH] lx2160acex7: move MEM_PLL_CFG into ddr-speed-specific + includes + +Both MEM_PLL_RAT and MEM_PLL_CFG together create the final ddr clock +speed, move the latter from common.rcwi into each speed-specific +include. + +Signed-off-by: Josua Mayer +--- + lx2160acex7/include/common.rcwi | 3 --- + lx2160acex7/include/pll_xxxx_xxx_2400.rcwi | 9 +++++++-- + lx2160acex7/include/pll_xxxx_xxx_2600.rcwi | 9 +++++++-- + lx2160acex7/include/pll_xxxx_xxx_2900.rcwi | 9 +++++++-- + lx2160acex7/include/pll_xxxx_xxx_3200.rcwi | 9 +++++++-- + 5 files changed, 28 insertions(+), 11 deletions(-) + +diff --git a/lx2160acex7/include/common.rcwi b/lx2160acex7/include/common.rcwi +index e8a5660..5523318 100644 +--- a/lx2160acex7/include/common.rcwi ++++ b/lx2160acex7/include/common.rcwi +@@ -2,9 +2,6 @@ + * LX2160A COM-Express Type 7 Common Configuration + */ + +-/* DDR CGU PLL clk out div 4 */ +-MEM_PLL_CFG=3 +-MEM2_PLL_CFG=3 + /* C[5:8]_PLL are CG[5:8] div 1 */ + C5_PLL_SEL=0 + C6_PLL_SEL=0 +diff --git a/lx2160acex7/include/pll_xxxx_xxx_2400.rcwi b/lx2160acex7/include/pll_xxxx_xxx_2400.rcwi +index 9c79664..6356b36 100644 +--- a/lx2160acex7/include/pll_xxxx_xxx_2400.rcwi ++++ b/lx2160acex7/include/pll_xxxx_xxx_2400.rcwi +@@ -1,7 +1,12 @@ + /* + * DDR Rate: 2400MHz ++ * ++ * DDR PHY Clock (half ddr clock, quarter mts rate) ++ * multiplier = 24 (24) ++ * divider = 4 (3) ++ * 100MHz x 24 / 4 = 600MHz (MTS = 4 x 600 = 2400MHz) + */ +- +-/* data rate is reference clock mul 24 = 2400 */ + MEM_PLL_RAT=24 ++MEM_PLL_CFG=3 + MEM2_PLL_RAT=24 ++MEM2_PLL_CFG=3 +diff --git a/lx2160acex7/include/pll_xxxx_xxx_2600.rcwi b/lx2160acex7/include/pll_xxxx_xxx_2600.rcwi +index 404d52a..d72047d 100644 +--- a/lx2160acex7/include/pll_xxxx_xxx_2600.rcwi ++++ b/lx2160acex7/include/pll_xxxx_xxx_2600.rcwi +@@ -1,7 +1,12 @@ + /* + * DDR Rate: 2600MHz ++ * ++ * DDR PHY Clock (half ddr clock, quarter mts rate) ++ * multiplier = 26 (26) ++ * divider = 4 (3) ++ * 100MHz x 26 / 4 = 650MHz (MTS = 4 x 650 = 2600MHz) + */ +- +-/* data rate is reference clock mul 26 = 2600 */ + MEM_PLL_RAT=26 ++MEM_PLL_CFG=3 + MEM2_PLL_RAT=26 ++MEM2_PLL_CFG=3 +diff --git a/lx2160acex7/include/pll_xxxx_xxx_2900.rcwi b/lx2160acex7/include/pll_xxxx_xxx_2900.rcwi +index 2ba2426..9ad274f 100644 +--- a/lx2160acex7/include/pll_xxxx_xxx_2900.rcwi ++++ b/lx2160acex7/include/pll_xxxx_xxx_2900.rcwi +@@ -1,7 +1,12 @@ + /* + * DDR Rate: 2900MHz ++ * ++ * DDR PHY Clock (half ddr clock, quarter mts rate) ++ * multiplier = 29 (29) ++ * divider = 4 (3) ++ * 100MHz x 29 / 4 = 725MHz (MTS = 4 x 725 = 2900MHz) + */ +- +-/* data rate is reference clock mul 29 = 2900 */ + MEM_PLL_RAT=29 ++MEM_PLL_CFG=3 + MEM2_PLL_RAT=29 ++MEM2_PLL_CFG=3 +diff --git a/lx2160acex7/include/pll_xxxx_xxx_3200.rcwi b/lx2160acex7/include/pll_xxxx_xxx_3200.rcwi +index cbc2cf4..abf7e9d 100644 +--- a/lx2160acex7/include/pll_xxxx_xxx_3200.rcwi ++++ b/lx2160acex7/include/pll_xxxx_xxx_3200.rcwi +@@ -1,7 +1,12 @@ + /* + * DDR Rate: 3200MHz ++ * ++ * DDR PHY Clock (half ddr clock, quarter mts rate) ++ * multiplier = 32 (32) ++ * divider = 4 (3) ++ * 100MHz x 32 / 4 = 800MHz (MTS = 4 x 800 = 3200MHz) + */ +- +-/* data rate is reference clock mul 32 = 3200 */ + MEM_PLL_RAT=32 ++MEM_PLL_CFG=3 + MEM2_PLL_RAT=32 ++MEM2_PLL_CFG=3 +-- +2.43.0 + diff --git a/recipes-bsp/rcw/files/0003-lx2160acex7-add-separate-configurations-for-flexspi-.patch b/recipes-bsp/rcw/files/0003-lx2160acex7-add-separate-configurations-for-flexspi-.patch new file mode 100644 index 0000000..58c4f6e --- /dev/null +++ b/recipes-bsp/rcw/files/0003-lx2160acex7-add-separate-configurations-for-flexspi-.patch @@ -0,0 +1,894 @@ +From 229c609e139b5f95ea96c03dc084ba53b4f09d5e Mon Sep 17 00:00:00 2001 +From: Josua Mayer +Date: Sat, 28 Sep 2024 12:24:13 +0200 +Subject: [PATCH] lx2160acex7: add separate configurations for flexspi and + sdhc1 boot + +Signed-off-by: Josua Mayer +--- + .../rcw_2000_700_2400_8_5_2_sdhc1.rcw | 25 +++++++++++++++++++ + ...2.rcw => rcw_2000_700_2400_8_5_2_xspi.rcw} | 2 ++ + .../rcw_2000_700_2600_8_5_2_sdhc1.rcw | 25 +++++++++++++++++++ + ...2.rcw => rcw_2000_700_2600_8_5_2_xspi.rcw} | 2 ++ + .../rcw_2000_700_2900_8_5_2_sdhc1.rcw | 25 +++++++++++++++++++ + ...2.rcw => rcw_2000_700_2900_8_5_2_xspi.rcw} | 2 ++ + .../rcw_2000_700_3200_8_5_2_sdhc1.rcw | 25 +++++++++++++++++++ + ...2.rcw => rcw_2000_700_3200_8_5_2_xspi.rcw} | 2 ++ + .../rcw_2200_700_2400_8_5_2_sdhc1.rcw | 25 +++++++++++++++++++ + ...2.rcw => rcw_2200_700_2400_8_5_2_xspi.rcw} | 2 ++ + .../rcw_2200_700_2600_8_5_2_sdhc1.rcw | 25 +++++++++++++++++++ + ...2.rcw => rcw_2200_700_2600_8_5_2_xspi.rcw} | 2 ++ + .../rcw_2200_700_2900_8_5_2_sdhc1.rcw | 25 +++++++++++++++++++ + ...2.rcw => rcw_2200_700_2900_8_5_2_xspi.rcw} | 2 ++ + .../rcw_2200_700_3200_8_5_2_sdhc1.rcw | 25 +++++++++++++++++++ + ...2.rcw => rcw_2200_700_3200_8_5_2_xspi.rcw} | 2 ++ + lx2160acex7/include/common_pbi.rcwi | 4 +++ + .../rcw_2000_700_2400_8_5_2_sdhc1.rcw | 25 +++++++++++++++++++ + ...2.rcw => rcw_2000_700_2400_8_5_2_xspi.rcw} | 2 ++ + .../rcw_2000_700_2600_8_5_2_sdhc1.rcw | 25 +++++++++++++++++++ + ...2.rcw => rcw_2000_700_2600_8_5_2_xspi.rcw} | 2 ++ + .../rcw_2000_700_2900_8_5_2_sdhc1.rcw | 25 +++++++++++++++++++ + ...2.rcw => rcw_2000_700_2900_8_5_2_xspi.rcw} | 2 ++ + .../rcw_2000_700_3200_8_5_2_sdhc1.rcw | 25 +++++++++++++++++++ + ...2.rcw => rcw_2000_700_3200_8_5_2_xspi.rcw} | 2 ++ + .../rcw_2200_700_2400_8_5_2_sdhc1.rcw | 25 +++++++++++++++++++ + ...2.rcw => rcw_2200_700_2400_8_5_2_xspi.rcw} | 2 ++ + .../rcw_2200_700_2600_8_5_2_sdhc1.rcw | 25 +++++++++++++++++++ + ...2.rcw => rcw_2200_700_2600_8_5_2_xspi.rcw} | 2 ++ + .../rcw_2200_700_2900_8_5_2_sdhc1.rcw | 25 +++++++++++++++++++ + ...2.rcw => rcw_2200_700_2900_8_5_2_xspi.rcw} | 2 ++ + .../rcw_2200_700_3200_8_5_2_sdhc1.rcw | 25 +++++++++++++++++++ + ...2.rcw => rcw_2200_700_3200_8_5_2_xspi.rcw} | 2 ++ + 33 files changed, 436 insertions(+) + create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2400_8_5_2_sdhc1.rcw + rename lx2160acex7/clearfog-cx/{rcw_2000_700_2400_8_5_2.rcw => rcw_2000_700_2400_8_5_2_xspi.rcw} (93%) + create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2600_8_5_2_sdhc1.rcw + rename lx2160acex7/clearfog-cx/{rcw_2000_700_2600_8_5_2.rcw => rcw_2000_700_2600_8_5_2_xspi.rcw} (93%) + create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2900_8_5_2_sdhc1.rcw + rename lx2160acex7/clearfog-cx/{rcw_2000_700_2900_8_5_2.rcw => rcw_2000_700_2900_8_5_2_xspi.rcw} (93%) + create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_3200_8_5_2_sdhc1.rcw + rename lx2160acex7/clearfog-cx/{rcw_2000_700_3200_8_5_2.rcw => rcw_2000_700_3200_8_5_2_xspi.rcw} (93%) + create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_700_2400_8_5_2_sdhc1.rcw + rename lx2160acex7/clearfog-cx/{rcw_2200_700_2400_8_5_2.rcw => rcw_2200_700_2400_8_5_2_xspi.rcw} (93%) + create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_700_2600_8_5_2_sdhc1.rcw + rename lx2160acex7/clearfog-cx/{rcw_2200_700_2600_8_5_2.rcw => rcw_2200_700_2600_8_5_2_xspi.rcw} (93%) + create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_700_2900_8_5_2_sdhc1.rcw + rename lx2160acex7/clearfog-cx/{rcw_2200_700_2900_8_5_2.rcw => rcw_2200_700_2900_8_5_2_xspi.rcw} (93%) + create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_700_3200_8_5_2_sdhc1.rcw + rename lx2160acex7/clearfog-cx/{rcw_2200_700_3200_8_5_2.rcw => rcw_2200_700_3200_8_5_2_xspi.rcw} (93%) + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_8_5_2_sdhc1.rcw + rename lx2160acex7_rev2/clearfog-cx/{rcw_2000_700_2400_8_5_2.rcw => rcw_2000_700_2400_8_5_2_xspi.rcw} (93%) + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_8_5_2_sdhc1.rcw + rename lx2160acex7_rev2/clearfog-cx/{rcw_2000_700_2600_8_5_2.rcw => rcw_2000_700_2600_8_5_2_xspi.rcw} (93%) + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_8_5_2_sdhc1.rcw + rename lx2160acex7_rev2/clearfog-cx/{rcw_2000_700_2900_8_5_2.rcw => rcw_2000_700_2900_8_5_2_xspi.rcw} (93%) + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_8_5_2_sdhc1.rcw + rename lx2160acex7_rev2/clearfog-cx/{rcw_2000_700_3200_8_5_2.rcw => rcw_2000_700_3200_8_5_2_xspi.rcw} (93%) + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2400_8_5_2_sdhc1.rcw + rename lx2160acex7_rev2/clearfog-cx/{rcw_2200_700_2400_8_5_2.rcw => rcw_2200_700_2400_8_5_2_xspi.rcw} (93%) + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2600_8_5_2_sdhc1.rcw + rename lx2160acex7_rev2/clearfog-cx/{rcw_2200_700_2600_8_5_2.rcw => rcw_2200_700_2600_8_5_2_xspi.rcw} (93%) + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2900_8_5_2_sdhc1.rcw + rename lx2160acex7_rev2/clearfog-cx/{rcw_2200_700_2900_8_5_2.rcw => rcw_2200_700_2900_8_5_2_xspi.rcw} (93%) + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_700_3200_8_5_2_sdhc1.rcw + rename lx2160acex7_rev2/clearfog-cx/{rcw_2200_700_3200_8_5_2.rcw => rcw_2200_700_3200_8_5_2_xspi.rcw} (93%) + +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2400_8_5_2_sdhc1.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2400_8_5_2_sdhc1.rcw +new file mode 100644 +index 0000000..0299002 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2400_8_5_2_sdhc1.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2400 MT/s ++ * ++ * Silicon 1.0 ++ * Boot from SDHC1 ++ */ ++ ++#define LX_SR 1 ++#define LX_BOOTSOURCE_SDHC1 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2400_8_5_2.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2400_8_5_2_xspi.rcw +similarity index 93% +rename from lx2160acex7/clearfog-cx/rcw_2000_700_2400_8_5_2.rcw +rename to lx2160acex7/clearfog-cx/rcw_2000_700_2400_8_5_2_xspi.rcw +index ba0f82c..9cb1229 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2000_700_2400_8_5_2.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2400_8_5_2_xspi.rcw +@@ -9,9 +9,11 @@ + * DDR -- 2400 MT/s + * + * Silicon 1.0 ++ * Boot from XSPI + */ + + #define LX_SR 1 ++#define LX_BOOTSOURCE_XSPI + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2600_8_5_2_sdhc1.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2600_8_5_2_sdhc1.rcw +new file mode 100644 +index 0000000..90a27ac +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2600_8_5_2_sdhc1.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2600 MT/s ++ * ++ * Silicon 1.0 ++ * Boot from SDHC1 ++ */ ++ ++#define LX_SR 1 ++#define LX_BOOTSOURCE_SDHC1 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2600_8_5_2.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2600_8_5_2_xspi.rcw +similarity index 93% +rename from lx2160acex7/clearfog-cx/rcw_2000_700_2600_8_5_2.rcw +rename to lx2160acex7/clearfog-cx/rcw_2000_700_2600_8_5_2_xspi.rcw +index b1723d3..5a3f820 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2000_700_2600_8_5_2.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2600_8_5_2_xspi.rcw +@@ -9,9 +9,11 @@ + * DDR -- 2600 MT/s + * + * Silicon 1.0 ++ * Boot from XSPI + */ + + #define LX_SR 1 ++#define LX_BOOTSOURCE_XSPI + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2900_8_5_2_sdhc1.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2900_8_5_2_sdhc1.rcw +new file mode 100644 +index 0000000..3a08744 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2900_8_5_2_sdhc1.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2900 MT/s ++ * ++ * Silicon 1.0 ++ * Boot from SDHC1 ++ */ ++ ++#define LX_SR 1 ++#define LX_BOOTSOURCE_SDHC1 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2900_8_5_2.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2900_8_5_2_xspi.rcw +similarity index 93% +rename from lx2160acex7/clearfog-cx/rcw_2000_700_2900_8_5_2.rcw +rename to lx2160acex7/clearfog-cx/rcw_2000_700_2900_8_5_2_xspi.rcw +index fa59785..ace0f0a 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2000_700_2900_8_5_2.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2900_8_5_2_xspi.rcw +@@ -9,9 +9,11 @@ + * DDR -- 2900 MT/s + * + * Silicon 1.0 ++ * Boot from XSPI + */ + + #define LX_SR 1 ++#define LX_BOOTSOURCE_XSPI + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_3200_8_5_2_sdhc1.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_3200_8_5_2_sdhc1.rcw +new file mode 100644 +index 0000000..19a3af1 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_3200_8_5_2_sdhc1.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 3200 MT/s ++ * ++ * Silicon 1.0 ++ * Boot from SDHC1 ++ */ ++ ++#define LX_SR 1 ++#define LX_BOOTSOURCE_SDHC1 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_3200_8_5_2.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_3200_8_5_2_xspi.rcw +similarity index 93% +rename from lx2160acex7/clearfog-cx/rcw_2000_700_3200_8_5_2.rcw +rename to lx2160acex7/clearfog-cx/rcw_2000_700_3200_8_5_2_xspi.rcw +index 90ac8a4..2c7bbed 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2000_700_3200_8_5_2.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_3200_8_5_2_xspi.rcw +@@ -9,9 +9,11 @@ + * DDR -- 3200 MT/s + * + * Silicon 1.0 ++ * Boot from XSPI + */ + + #define LX_SR 1 ++#define LX_BOOTSOURCE_XSPI + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_700_2400_8_5_2_sdhc1.rcw b/lx2160acex7/clearfog-cx/rcw_2200_700_2400_8_5_2_sdhc1.rcw +new file mode 100644 +index 0000000..bf7af38 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2200_700_2400_8_5_2_sdhc1.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2400 MT/s ++ * ++ * Silicon 1.0 ++ * Boot from SDHC1 ++ */ ++ ++#define LX_SR 1 ++#define LX_BOOTSOURCE_SDHC1 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_700_2400_8_5_2.rcw b/lx2160acex7/clearfog-cx/rcw_2200_700_2400_8_5_2_xspi.rcw +similarity index 93% +rename from lx2160acex7/clearfog-cx/rcw_2200_700_2400_8_5_2.rcw +rename to lx2160acex7/clearfog-cx/rcw_2200_700_2400_8_5_2_xspi.rcw +index 464a285..f23be28 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2200_700_2400_8_5_2.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2200_700_2400_8_5_2_xspi.rcw +@@ -9,9 +9,11 @@ + * DDR -- 2400 MT/s + * + * Silicon 1.0 ++ * Boot from XSPI + */ + + #define LX_SR 1 ++#define LX_BOOTSOURCE_XSPI + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_700_2600_8_5_2_sdhc1.rcw b/lx2160acex7/clearfog-cx/rcw_2200_700_2600_8_5_2_sdhc1.rcw +new file mode 100644 +index 0000000..ff778ec +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2200_700_2600_8_5_2_sdhc1.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2600 MT/s ++ * ++ * Silicon 1.0 ++ * Boot from SDHC1 ++ */ ++ ++#define LX_SR 1 ++#define LX_BOOTSOURCE_SDHC1 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_700_2600_8_5_2.rcw b/lx2160acex7/clearfog-cx/rcw_2200_700_2600_8_5_2_xspi.rcw +similarity index 93% +rename from lx2160acex7/clearfog-cx/rcw_2200_700_2600_8_5_2.rcw +rename to lx2160acex7/clearfog-cx/rcw_2200_700_2600_8_5_2_xspi.rcw +index 1ef7db6..62cf89e 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2200_700_2600_8_5_2.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2200_700_2600_8_5_2_xspi.rcw +@@ -9,9 +9,11 @@ + * DDR -- 2600 MT/s + * + * Silicon 1.0 ++ * Boot from XSPI + */ + + #define LX_SR 1 ++#define LX_BOOTSOURCE_XSPI + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_700_2900_8_5_2_sdhc1.rcw b/lx2160acex7/clearfog-cx/rcw_2200_700_2900_8_5_2_sdhc1.rcw +new file mode 100644 +index 0000000..90cd09c +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2200_700_2900_8_5_2_sdhc1.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2900 MT/s ++ * ++ * Silicon 1.0 ++ * Boot from SDHC1 ++ */ ++ ++#define LX_SR 1 ++#define LX_BOOTSOURCE_SDHC1 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_700_2900_8_5_2.rcw b/lx2160acex7/clearfog-cx/rcw_2200_700_2900_8_5_2_xspi.rcw +similarity index 93% +rename from lx2160acex7/clearfog-cx/rcw_2200_700_2900_8_5_2.rcw +rename to lx2160acex7/clearfog-cx/rcw_2200_700_2900_8_5_2_xspi.rcw +index d021306..13ec066 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2200_700_2900_8_5_2.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2200_700_2900_8_5_2_xspi.rcw +@@ -9,9 +9,11 @@ + * DDR -- 2900 MT/s + * + * Silicon 1.0 ++ * Boot from XSPI + */ + + #define LX_SR 1 ++#define LX_BOOTSOURCE_XSPI + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_700_3200_8_5_2_sdhc1.rcw b/lx2160acex7/clearfog-cx/rcw_2200_700_3200_8_5_2_sdhc1.rcw +new file mode 100644 +index 0000000..88731fa +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2200_700_3200_8_5_2_sdhc1.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 3200 MT/s ++ * ++ * Silicon 1.0 ++ * Boot from SDHC1 ++ */ ++ ++#define LX_SR 1 ++#define LX_BOOTSOURCE_SDHC1 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_700_3200_8_5_2.rcw b/lx2160acex7/clearfog-cx/rcw_2200_700_3200_8_5_2_xspi.rcw +similarity index 93% +rename from lx2160acex7/clearfog-cx/rcw_2200_700_3200_8_5_2.rcw +rename to lx2160acex7/clearfog-cx/rcw_2200_700_3200_8_5_2_xspi.rcw +index bfef1d4..b80f8cb 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2200_700_3200_8_5_2.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2200_700_3200_8_5_2_xspi.rcw +@@ -9,9 +9,11 @@ + * DDR -- 3200 MT/s + * + * Silicon 1.0 ++ * Boot from XSPI + */ + + #define LX_SR 1 ++#define LX_BOOTSOURCE_XSPI + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> +diff --git a/lx2160acex7/include/common_pbi.rcwi b/lx2160acex7/include/common_pbi.rcwi +index 0c28f92..848d48b 100644 +--- a/lx2160acex7/include/common_pbi.rcwi ++++ b/lx2160acex7/include/common_pbi.rcwi +@@ -11,7 +11,11 @@ write 0x2320000,0x20000000 + #include <../lx2160asi/scratchrw1.rcw> + + /* Boot Location Pointer */ ++#if defined(LX_BOOTSOURCE_SDHC1) + #include <../lx2160asi/bootlocptr_sd.rcw> ++#elif defined(LX_BOOTSOURCE_XSPI) ++#include <../lx2160asi/bootlocptr_nor.rcw> ++#endif + + /* Errata for SATA controller */ + #include <../lx2160asi/a010554.rcw> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_8_5_2_sdhc1.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_8_5_2_sdhc1.rcw +new file mode 100644 +index 0000000..b77ed2c +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_8_5_2_sdhc1.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2400 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from SDHC1 ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_SDHC1 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_8_5_2.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_8_5_2_xspi.rcw +similarity index 93% +rename from lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_8_5_2.rcw +rename to lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_8_5_2_xspi.rcw +index 1c23c5c..5c11864 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_8_5_2.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_8_5_2_xspi.rcw +@@ -9,9 +9,11 @@ + * DDR -- 2400 MT/s + * + * Silicon 2.0 ++ * Boot from XSPI + */ + + #define LX_SR 2 ++#define LX_BOOTSOURCE_XSPI + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_8_5_2_sdhc1.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_8_5_2_sdhc1.rcw +new file mode 100644 +index 0000000..2d19602 +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_8_5_2_sdhc1.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2600 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from SDHC1 ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_SDHC1 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_8_5_2.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_8_5_2_xspi.rcw +similarity index 93% +rename from lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_8_5_2.rcw +rename to lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_8_5_2_xspi.rcw +index 87391ab..21df735 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_8_5_2.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_8_5_2_xspi.rcw +@@ -9,9 +9,11 @@ + * DDR -- 2600 MT/s + * + * Silicon 2.0 ++ * Boot from XSPI + */ + + #define LX_SR 2 ++#define LX_BOOTSOURCE_XSPI + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_8_5_2_sdhc1.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_8_5_2_sdhc1.rcw +new file mode 100644 +index 0000000..d141116 +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_8_5_2_sdhc1.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2900 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from SDHC1 ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_SDHC1 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_8_5_2.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_8_5_2_xspi.rcw +similarity index 93% +rename from lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_8_5_2.rcw +rename to lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_8_5_2_xspi.rcw +index 9114f36..d128916 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_8_5_2.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_8_5_2_xspi.rcw +@@ -9,9 +9,11 @@ + * DDR -- 2900 MT/s + * + * Silicon 2.0 ++ * Boot from XSPI + */ + + #define LX_SR 2 ++#define LX_BOOTSOURCE_XSPI + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_8_5_2_sdhc1.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_8_5_2_sdhc1.rcw +new file mode 100644 +index 0000000..8b5ec8d +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_8_5_2_sdhc1.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 3200 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from SDHC1 ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_SDHC1 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_8_5_2.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_8_5_2_xspi.rcw +similarity index 93% +rename from lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_8_5_2.rcw +rename to lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_8_5_2_xspi.rcw +index 7e97984..55d8bc1 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_8_5_2.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_8_5_2_xspi.rcw +@@ -9,9 +9,11 @@ + * DDR -- 3200 MT/s + * + * Silicon 2.0 ++ * Boot from XSPI + */ + + #define LX_SR 2 ++#define LX_BOOTSOURCE_XSPI + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2400_8_5_2_sdhc1.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2400_8_5_2_sdhc1.rcw +new file mode 100644 +index 0000000..7763a4a +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2400_8_5_2_sdhc1.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2400 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from SDHC1 ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_SDHC1 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2400_8_5_2.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2400_8_5_2_xspi.rcw +similarity index 93% +rename from lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2400_8_5_2.rcw +rename to lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2400_8_5_2_xspi.rcw +index d59ceed..9643b52 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2400_8_5_2.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2400_8_5_2_xspi.rcw +@@ -9,9 +9,11 @@ + * DDR -- 2400 MT/s + * + * Silicon 2.0 ++ * Boot from XSPI + */ + + #define LX_SR 2 ++#define LX_BOOTSOURCE_XSPI + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2600_8_5_2_sdhc1.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2600_8_5_2_sdhc1.rcw +new file mode 100644 +index 0000000..b238680 +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2600_8_5_2_sdhc1.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2600 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from SDHC1 ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_SDHC1 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2600_8_5_2.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2600_8_5_2_xspi.rcw +similarity index 93% +rename from lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2600_8_5_2.rcw +rename to lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2600_8_5_2_xspi.rcw +index 1bf815b..79cea0d 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2600_8_5_2.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2600_8_5_2_xspi.rcw +@@ -9,9 +9,11 @@ + * DDR -- 2600 MT/s + * + * Silicon 2.0 ++ * Boot from XSPI + */ + + #define LX_SR 2 ++#define LX_BOOTSOURCE_XSPI + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2900_8_5_2_sdhc1.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2900_8_5_2_sdhc1.rcw +new file mode 100644 +index 0000000..46b16ab +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2900_8_5_2_sdhc1.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2900 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from SDHC1 ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_SDHC1 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2900_8_5_2.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2900_8_5_2_xspi.rcw +similarity index 93% +rename from lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2900_8_5_2.rcw +rename to lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2900_8_5_2_xspi.rcw +index 01138dc..b12898a 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2900_8_5_2.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2900_8_5_2_xspi.rcw +@@ -9,9 +9,11 @@ + * DDR -- 2900 MT/s + * + * Silicon 2.0 ++ * Boot from XSPI + */ + + #define LX_SR 2 ++#define LX_BOOTSOURCE_XSPI + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_3200_8_5_2_sdhc1.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_3200_8_5_2_sdhc1.rcw +new file mode 100644 +index 0000000..dc9180f +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_3200_8_5_2_sdhc1.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 3200 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from SDHC1 ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_SDHC1 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_3200_8_5_2.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_3200_8_5_2_xspi.rcw +similarity index 93% +rename from lx2160acex7_rev2/clearfog-cx/rcw_2200_700_3200_8_5_2.rcw +rename to lx2160acex7_rev2/clearfog-cx/rcw_2200_700_3200_8_5_2_xspi.rcw +index e99a12b..c2ff13a 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_3200_8_5_2.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_3200_8_5_2_xspi.rcw +@@ -9,9 +9,11 @@ + * DDR -- 3200 MT/s + * + * Silicon 2.0 ++ * Boot from XSPI + */ + + #define LX_SR 2 ++#define LX_BOOTSOURCE_XSPI + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> +-- +2.43.0 + diff --git a/recipes-bsp/rcw/files/0004-lx2160acex7-rename-sdhc1-config-to-generic-sdhc-for-.patch b/recipes-bsp/rcw/files/0004-lx2160acex7-rename-sdhc1-config-to-generic-sdhc-for-.patch new file mode 100644 index 0000000..dfdd0b2 --- /dev/null +++ b/recipes-bsp/rcw/files/0004-lx2160acex7-rename-sdhc1-config-to-generic-sdhc-for-.patch @@ -0,0 +1,149 @@ +From 8756b34d63f7357f7309bfa27fd175b198285bae Mon Sep 17 00:00:00 2001 +From: Josua Mayer +Date: Sat, 28 Sep 2024 14:54:36 +0200 +Subject: [PATCH] lx2160acex7: rename sdhc1 config to generic sdhc, for both + sd & emmc + +Both sdhc1 and sdhc2 boot can share same rcw. +They use identical boot location pointer values, differences were only +in old rcw with explicit block-copy from boot media to ocram. + +This block-copy is not required for either spi, emmc or sd boot. + +Signed-off-by: Josua Mayer +--- + ...0_8_5_2_sdhc1.rcw => rcw_2000_700_2400_8_5_2_sdhc.rcw} | 0 + ...0_8_5_2_sdhc1.rcw => rcw_2000_700_2600_8_5_2_sdhc.rcw} | 0 + ...0_8_5_2_sdhc1.rcw => rcw_2000_700_2900_8_5_2_sdhc.rcw} | 0 + ...0_8_5_2_sdhc1.rcw => rcw_2000_700_3200_8_5_2_sdhc.rcw} | 0 + ...0_8_5_2_sdhc1.rcw => rcw_2200_700_2400_8_5_2_sdhc.rcw} | 0 + ...0_8_5_2_sdhc1.rcw => rcw_2200_700_2600_8_5_2_sdhc.rcw} | 0 + ...0_8_5_2_sdhc1.rcw => rcw_2200_700_2900_8_5_2_sdhc.rcw} | 0 + ...0_8_5_2_sdhc1.rcw => rcw_2200_700_3200_8_5_2_sdhc.rcw} | 0 + lx2160acex7/include/common.rcwi | 8 ++++++-- + lx2160acex7/include/common_pbi.rcwi | 2 +- + ...0_8_5_2_sdhc1.rcw => rcw_2000_700_2400_8_5_2_sdhc.rcw} | 0 + ...0_8_5_2_sdhc1.rcw => rcw_2000_700_2600_8_5_2_sdhc.rcw} | 0 + ...0_8_5_2_sdhc1.rcw => rcw_2000_700_2900_8_5_2_sdhc.rcw} | 0 + ...0_8_5_2_sdhc1.rcw => rcw_2000_700_3200_8_5_2_sdhc.rcw} | 0 + ...0_8_5_2_sdhc1.rcw => rcw_2200_700_2400_8_5_2_sdhc.rcw} | 0 + ...0_8_5_2_sdhc1.rcw => rcw_2200_700_2600_8_5_2_sdhc.rcw} | 0 + ...0_8_5_2_sdhc1.rcw => rcw_2200_700_2900_8_5_2_sdhc.rcw} | 0 + ...0_8_5_2_sdhc1.rcw => rcw_2200_700_3200_8_5_2_sdhc.rcw} | 0 + 18 files changed, 7 insertions(+), 3 deletions(-) + rename lx2160acex7/clearfog-cx/{rcw_2000_700_2400_8_5_2_sdhc1.rcw => rcw_2000_700_2400_8_5_2_sdhc.rcw} (100%) + rename lx2160acex7/clearfog-cx/{rcw_2000_700_2600_8_5_2_sdhc1.rcw => rcw_2000_700_2600_8_5_2_sdhc.rcw} (100%) + rename lx2160acex7/clearfog-cx/{rcw_2000_700_2900_8_5_2_sdhc1.rcw => rcw_2000_700_2900_8_5_2_sdhc.rcw} (100%) + rename lx2160acex7/clearfog-cx/{rcw_2000_700_3200_8_5_2_sdhc1.rcw => rcw_2000_700_3200_8_5_2_sdhc.rcw} (100%) + rename lx2160acex7/clearfog-cx/{rcw_2200_700_2400_8_5_2_sdhc1.rcw => rcw_2200_700_2400_8_5_2_sdhc.rcw} (100%) + rename lx2160acex7/clearfog-cx/{rcw_2200_700_2600_8_5_2_sdhc1.rcw => rcw_2200_700_2600_8_5_2_sdhc.rcw} (100%) + rename lx2160acex7/clearfog-cx/{rcw_2200_700_2900_8_5_2_sdhc1.rcw => rcw_2200_700_2900_8_5_2_sdhc.rcw} (100%) + rename lx2160acex7/clearfog-cx/{rcw_2200_700_3200_8_5_2_sdhc1.rcw => rcw_2200_700_3200_8_5_2_sdhc.rcw} (100%) + rename lx2160acex7_rev2/clearfog-cx/{rcw_2000_700_2400_8_5_2_sdhc1.rcw => rcw_2000_700_2400_8_5_2_sdhc.rcw} (100%) + rename lx2160acex7_rev2/clearfog-cx/{rcw_2000_700_2600_8_5_2_sdhc1.rcw => rcw_2000_700_2600_8_5_2_sdhc.rcw} (100%) + rename lx2160acex7_rev2/clearfog-cx/{rcw_2000_700_2900_8_5_2_sdhc1.rcw => rcw_2000_700_2900_8_5_2_sdhc.rcw} (100%) + rename lx2160acex7_rev2/clearfog-cx/{rcw_2000_700_3200_8_5_2_sdhc1.rcw => rcw_2000_700_3200_8_5_2_sdhc.rcw} (100%) + rename lx2160acex7_rev2/clearfog-cx/{rcw_2200_700_2400_8_5_2_sdhc1.rcw => rcw_2200_700_2400_8_5_2_sdhc.rcw} (100%) + rename lx2160acex7_rev2/clearfog-cx/{rcw_2200_700_2600_8_5_2_sdhc1.rcw => rcw_2200_700_2600_8_5_2_sdhc.rcw} (100%) + rename lx2160acex7_rev2/clearfog-cx/{rcw_2200_700_2900_8_5_2_sdhc1.rcw => rcw_2200_700_2900_8_5_2_sdhc.rcw} (100%) + rename lx2160acex7_rev2/clearfog-cx/{rcw_2200_700_3200_8_5_2_sdhc1.rcw => rcw_2200_700_3200_8_5_2_sdhc.rcw} (100%) + +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2400_8_5_2_sdhc1.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2400_8_5_2_sdhc.rcw +similarity index 100% +rename from lx2160acex7/clearfog-cx/rcw_2000_700_2400_8_5_2_sdhc1.rcw +rename to lx2160acex7/clearfog-cx/rcw_2000_700_2400_8_5_2_sdhc.rcw +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2600_8_5_2_sdhc1.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2600_8_5_2_sdhc.rcw +similarity index 100% +rename from lx2160acex7/clearfog-cx/rcw_2000_700_2600_8_5_2_sdhc1.rcw +rename to lx2160acex7/clearfog-cx/rcw_2000_700_2600_8_5_2_sdhc.rcw +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2900_8_5_2_sdhc1.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2900_8_5_2_sdhc.rcw +similarity index 100% +rename from lx2160acex7/clearfog-cx/rcw_2000_700_2900_8_5_2_sdhc1.rcw +rename to lx2160acex7/clearfog-cx/rcw_2000_700_2900_8_5_2_sdhc.rcw +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_3200_8_5_2_sdhc1.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_3200_8_5_2_sdhc.rcw +similarity index 100% +rename from lx2160acex7/clearfog-cx/rcw_2000_700_3200_8_5_2_sdhc1.rcw +rename to lx2160acex7/clearfog-cx/rcw_2000_700_3200_8_5_2_sdhc.rcw +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_700_2400_8_5_2_sdhc1.rcw b/lx2160acex7/clearfog-cx/rcw_2200_700_2400_8_5_2_sdhc.rcw +similarity index 100% +rename from lx2160acex7/clearfog-cx/rcw_2200_700_2400_8_5_2_sdhc1.rcw +rename to lx2160acex7/clearfog-cx/rcw_2200_700_2400_8_5_2_sdhc.rcw +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_700_2600_8_5_2_sdhc1.rcw b/lx2160acex7/clearfog-cx/rcw_2200_700_2600_8_5_2_sdhc.rcw +similarity index 100% +rename from lx2160acex7/clearfog-cx/rcw_2200_700_2600_8_5_2_sdhc1.rcw +rename to lx2160acex7/clearfog-cx/rcw_2200_700_2600_8_5_2_sdhc.rcw +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_700_2900_8_5_2_sdhc1.rcw b/lx2160acex7/clearfog-cx/rcw_2200_700_2900_8_5_2_sdhc.rcw +similarity index 100% +rename from lx2160acex7/clearfog-cx/rcw_2200_700_2900_8_5_2_sdhc1.rcw +rename to lx2160acex7/clearfog-cx/rcw_2200_700_2900_8_5_2_sdhc.rcw +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_700_3200_8_5_2_sdhc1.rcw b/lx2160acex7/clearfog-cx/rcw_2200_700_3200_8_5_2_sdhc.rcw +similarity index 100% +rename from lx2160acex7/clearfog-cx/rcw_2200_700_3200_8_5_2_sdhc1.rcw +rename to lx2160acex7/clearfog-cx/rcw_2200_700_3200_8_5_2_sdhc.rcw +diff --git a/lx2160acex7/include/common.rcwi b/lx2160acex7/include/common.rcwi +index 5523318..c76b174 100644 +--- a/lx2160acex7/include/common.rcwi ++++ b/lx2160acex7/include/common.rcwi +@@ -11,8 +11,12 @@ C8_PLL_SEL=0 + HWA_CGA_M1_CLK_SEL=1 + /* Cluster group B clock is PLL2 div 2 (for DCE) */ + HWA_CGB_M1_CLK_SEL=6 +-/* fall-back boot-mode is ocram, when DCFG bit location pointer registers are null */ +-BOOT_LOC=21 // TODO: test if SPI boot still functional ++/* ++ * fall-back boot-mode when DCFG boot location pointer registers are null ++ * - 0b10101 (21): OCRAM ++ * - 0b11010 (26): XSPI ++ */ ++BOOT_LOC=21 + /* SYSCLK is 100MHz */ + SYSCLK_FREQ=600 + /* USB-3.0 clock is 100MHz */ +diff --git a/lx2160acex7/include/common_pbi.rcwi b/lx2160acex7/include/common_pbi.rcwi +index 848d48b..36b723d 100644 +--- a/lx2160acex7/include/common_pbi.rcwi ++++ b/lx2160acex7/include/common_pbi.rcwi +@@ -10,7 +10,7 @@ write 0x2320000,0x20000000 + /* Errata to write on scratch reg for validation */ + #include <../lx2160asi/scratchrw1.rcw> + +-/* Boot Location Pointer */ ++/* Set Boot Location Pointer (Fall-back when unset is BOOT_LOC) */ + #if defined(LX_BOOTSOURCE_SDHC1) + #include <../lx2160asi/bootlocptr_sd.rcw> + #elif defined(LX_BOOTSOURCE_XSPI) +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_8_5_2_sdhc1.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_8_5_2_sdhc.rcw +similarity index 100% +rename from lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_8_5_2_sdhc1.rcw +rename to lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_8_5_2_sdhc.rcw +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_8_5_2_sdhc1.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_8_5_2_sdhc.rcw +similarity index 100% +rename from lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_8_5_2_sdhc1.rcw +rename to lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_8_5_2_sdhc.rcw +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_8_5_2_sdhc1.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_8_5_2_sdhc.rcw +similarity index 100% +rename from lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_8_5_2_sdhc1.rcw +rename to lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_8_5_2_sdhc.rcw +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_8_5_2_sdhc1.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_8_5_2_sdhc.rcw +similarity index 100% +rename from lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_8_5_2_sdhc1.rcw +rename to lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_8_5_2_sdhc.rcw +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2400_8_5_2_sdhc1.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2400_8_5_2_sdhc.rcw +similarity index 100% +rename from lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2400_8_5_2_sdhc1.rcw +rename to lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2400_8_5_2_sdhc.rcw +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2600_8_5_2_sdhc1.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2600_8_5_2_sdhc.rcw +similarity index 100% +rename from lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2600_8_5_2_sdhc1.rcw +rename to lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2600_8_5_2_sdhc.rcw +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2900_8_5_2_sdhc1.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2900_8_5_2_sdhc.rcw +similarity index 100% +rename from lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2900_8_5_2_sdhc1.rcw +rename to lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2900_8_5_2_sdhc.rcw +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_3200_8_5_2_sdhc1.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_3200_8_5_2_sdhc.rcw +similarity index 100% +rename from lx2160acex7_rev2/clearfog-cx/rcw_2200_700_3200_8_5_2_sdhc1.rcw +rename to lx2160acex7_rev2/clearfog-cx/rcw_2200_700_3200_8_5_2_sdhc.rcw +-- +2.43.0 + diff --git a/recipes-bsp/rcw/files/0005-add-loadc-jumpc-and-jump-to-pbi-instructions.patch b/recipes-bsp/rcw/files/0005-add-loadc-jumpc-and-jump-to-pbi-instructions.patch new file mode 100644 index 0000000..207a4e7 --- /dev/null +++ b/recipes-bsp/rcw/files/0005-add-loadc-jumpc-and-jump-to-pbi-instructions.patch @@ -0,0 +1,55 @@ +From 22e16d5c3969a2fdfdb23423a8d28d5e80eea987 Mon Sep 17 00:00:00 2001 +From: Rabeeh Khoury +Date: Mon, 23 Mar 2020 12:16:13 +0200 +Subject: [PATCH 5/6] add loadc, jumpc and jump to pbi instructions + +Add 'load conditional', 'jump condidional' and 'jump' to PBI +instructions. + +Signed-off-by: Rabeeh Khoury +--- + rcw.py | 28 ++++++++++++++++++++++++++++ + 1 file changed, 28 insertions(+) + +diff --git a/rcw.py b/rcw.py +index e7d3795..bcd088d 100755 +--- a/rcw.py ++++ b/rcw.py +@@ -330,6 +330,34 @@ def build_pbi(lines): + v2 = struct.pack(endianess + 'L', p2) + subsection += v1 + subsection += v2 ++ elif op == 'loadc': ++ if p1 == None or p2 == None: ++ print('Error: "loadc" instruction requires two parameters') ++ return '' ++ v1 = struct.pack(endianess + 'L', 0x80140000) ++ v2 = struct.pack(endianess + 'L', p1) ++ v3 = struct.pack(endianess + 'L', p2) ++ subsection += v1 ++ subsection += v2 ++ subsection += v3 ++ elif op == 'jumpc': ++ if p1 == None or p2 == None: ++ print('Error: "jumpc" instruction requires two parameters') ++ return '' ++ v1 = struct.pack(endianess + 'L', 0x80850000) ++ v2 = struct.pack(endianess + 'L', p1) ++ v3 = struct.pack(endianess + 'L', p2) ++ subsection += v1 ++ subsection += v2 ++ subsection += v3 ++ elif op == 'jump': ++ if p1 == None: ++ print('Error: "jump" instruction requires a parameter') ++ return '' ++ v1 = struct.pack(endianess + 'L', 0x80840000) ++ v2 = struct.pack(endianess + 'L', p1) ++ subsection += v1 ++ subsection += v2 + elif op == 'awrite': + if opsize == '.b5': + # altconfig write with B=5 (16 bytes) +-- +2.43.0 + diff --git a/recipes-bsp/rcw/files/0006-lx2160acex7-add-configuration-for-both-sdhc-xspi.patch b/recipes-bsp/rcw/files/0006-lx2160acex7-add-configuration-for-both-sdhc-xspi.patch new file mode 100644 index 0000000..9c79a80 --- /dev/null +++ b/recipes-bsp/rcw/files/0006-lx2160acex7-add-configuration-for-both-sdhc-xspi.patch @@ -0,0 +1,836 @@ +From ac13e12390764b8770227c0032f62994ece7e17b Mon Sep 17 00:00:00 2001 +From: Josua Mayer +Date: Sat, 28 Sep 2024 17:40:04 +0200 +Subject: [PATCH 6/6] lx2160acex7: add configuration for both sdhc & xspi + +Add "auto" configuration supporting both sdhc and xspi boot sources. +A special pbi section is added setting boot location pointer according +to rcw source. + +Signed-off-by: Josua Mayer +--- + .../rcw_2000_700_2400_8_5_2_auto.rcw | 23 +++++++ + .../rcw_2000_700_2400_8_5_2_sdhc.rcw | 2 +- + .../rcw_2000_700_2600_8_5_2_auto.rcw | 23 +++++++ + .../rcw_2000_700_2600_8_5_2_sdhc.rcw | 2 +- + .../rcw_2000_700_2900_8_5_2_auto.rcw | 23 +++++++ + .../rcw_2000_700_2900_8_5_2_sdhc.rcw | 2 +- + .../rcw_2000_700_3200_8_5_2_auto.rcw | 23 +++++++ + .../rcw_2000_700_3200_8_5_2_sdhc.rcw | 2 +- + .../rcw_2200_700_2400_8_5_2_auto.rcw | 23 +++++++ + .../rcw_2200_700_2400_8_5_2_sdhc.rcw | 2 +- + .../rcw_2200_700_2600_8_5_2_auto.rcw | 23 +++++++ + .../rcw_2200_700_2600_8_5_2_sdhc.rcw | 2 +- + .../rcw_2200_700_2900_8_5_2_auto.rcw | 23 +++++++ + .../rcw_2200_700_2900_8_5_2_sdhc.rcw | 2 +- + .../rcw_2200_700_3200_8_5_2_auto.rcw | 23 +++++++ + .../rcw_2200_700_3200_8_5_2_sdhc.rcw | 2 +- + lx2160acex7/include/common_pbi.rcwi | 16 ++--- + .../rcw_2000_700_2400_8_5_2_auto.rcw | 23 +++++++ + .../rcw_2000_700_2400_8_5_2_sdhc.rcw | 2 +- + .../rcw_2000_700_2600_8_5_2_auto.rcw | 23 +++++++ + .../rcw_2000_700_2600_8_5_2_sdhc.rcw | 2 +- + .../rcw_2000_700_2900_8_5_2_auto.rcw | 23 +++++++ + .../rcw_2000_700_2900_8_5_2_sdhc.rcw | 2 +- + .../rcw_2000_700_3200_8_5_2_auto.rcw | 23 +++++++ + .../rcw_2000_700_3200_8_5_2_sdhc.rcw | 2 +- + .../rcw_2200_700_2400_8_5_2_auto.rcw | 23 +++++++ + .../rcw_2200_700_2400_8_5_2_sdhc.rcw | 2 +- + .../rcw_2200_700_2600_8_5_2_auto.rcw | 23 +++++++ + .../rcw_2200_700_2600_8_5_2_sdhc.rcw | 2 +- + .../rcw_2200_700_2900_8_5_2_auto.rcw | 23 +++++++ + .../rcw_2200_700_2900_8_5_2_sdhc.rcw | 2 +- + .../rcw_2200_700_3200_8_5_2_auto.rcw | 23 +++++++ + .../rcw_2200_700_3200_8_5_2_sdhc.rcw | 2 +- + lx2160asi/bootlocptr_auto.rcw | 60 +++++++++++++++++++ + 34 files changed, 453 insertions(+), 23 deletions(-) + create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2400_8_5_2_auto.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2600_8_5_2_auto.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2900_8_5_2_auto.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_3200_8_5_2_auto.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_700_2400_8_5_2_auto.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_700_2600_8_5_2_auto.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_700_2900_8_5_2_auto.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_700_3200_8_5_2_auto.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_8_5_2_auto.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_8_5_2_auto.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_8_5_2_auto.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_8_5_2_auto.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2400_8_5_2_auto.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2600_8_5_2_auto.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2900_8_5_2_auto.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_700_3200_8_5_2_auto.rcw + create mode 100644 lx2160asi/bootlocptr_auto.rcw + +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2400_8_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2400_8_5_2_auto.rcw +new file mode 100644 +index 0000000..ba0f82c +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2400_8_5_2_auto.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2400 MT/s ++ * ++ * Silicon 1.0 ++ */ ++ ++#define LX_SR 1 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2400_8_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2400_8_5_2_sdhc.rcw +index 0299002..4d67915 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2000_700_2400_8_5_2_sdhc.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2400_8_5_2_sdhc.rcw +@@ -13,7 +13,7 @@ + */ + + #define LX_SR 1 +-#define LX_BOOTSOURCE_SDHC1 ++#define LX_BOOTSOURCE_SDHC + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2600_8_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2600_8_5_2_auto.rcw +new file mode 100644 +index 0000000..b1723d3 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2600_8_5_2_auto.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2600 MT/s ++ * ++ * Silicon 1.0 ++ */ ++ ++#define LX_SR 1 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2600_8_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2600_8_5_2_sdhc.rcw +index 90a27ac..0424418 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2000_700_2600_8_5_2_sdhc.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2600_8_5_2_sdhc.rcw +@@ -13,7 +13,7 @@ + */ + + #define LX_SR 1 +-#define LX_BOOTSOURCE_SDHC1 ++#define LX_BOOTSOURCE_SDHC + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2900_8_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2900_8_5_2_auto.rcw +new file mode 100644 +index 0000000..fa59785 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2900_8_5_2_auto.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2900 MT/s ++ * ++ * Silicon 1.0 ++ */ ++ ++#define LX_SR 1 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2900_8_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2900_8_5_2_sdhc.rcw +index 3a08744..be0d219 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2000_700_2900_8_5_2_sdhc.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2900_8_5_2_sdhc.rcw +@@ -13,7 +13,7 @@ + */ + + #define LX_SR 1 +-#define LX_BOOTSOURCE_SDHC1 ++#define LX_BOOTSOURCE_SDHC + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_3200_8_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_3200_8_5_2_auto.rcw +new file mode 100644 +index 0000000..90ac8a4 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_3200_8_5_2_auto.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 3200 MT/s ++ * ++ * Silicon 1.0 ++ */ ++ ++#define LX_SR 1 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_3200_8_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_3200_8_5_2_sdhc.rcw +index 19a3af1..e1f9092 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2000_700_3200_8_5_2_sdhc.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_3200_8_5_2_sdhc.rcw +@@ -13,7 +13,7 @@ + */ + + #define LX_SR 1 +-#define LX_BOOTSOURCE_SDHC1 ++#define LX_BOOTSOURCE_SDHC + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_700_2400_8_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2200_700_2400_8_5_2_auto.rcw +new file mode 100644 +index 0000000..464a285 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2200_700_2400_8_5_2_auto.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2400 MT/s ++ * ++ * Silicon 1.0 ++ */ ++ ++#define LX_SR 1 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_700_2400_8_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2200_700_2400_8_5_2_sdhc.rcw +index bf7af38..6f696f5 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2200_700_2400_8_5_2_sdhc.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2200_700_2400_8_5_2_sdhc.rcw +@@ -13,7 +13,7 @@ + */ + + #define LX_SR 1 +-#define LX_BOOTSOURCE_SDHC1 ++#define LX_BOOTSOURCE_SDHC + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_700_2600_8_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2200_700_2600_8_5_2_auto.rcw +new file mode 100644 +index 0000000..1ef7db6 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2200_700_2600_8_5_2_auto.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2600 MT/s ++ * ++ * Silicon 1.0 ++ */ ++ ++#define LX_SR 1 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_700_2600_8_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2200_700_2600_8_5_2_sdhc.rcw +index ff778ec..46d84cb 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2200_700_2600_8_5_2_sdhc.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2200_700_2600_8_5_2_sdhc.rcw +@@ -13,7 +13,7 @@ + */ + + #define LX_SR 1 +-#define LX_BOOTSOURCE_SDHC1 ++#define LX_BOOTSOURCE_SDHC + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_700_2900_8_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2200_700_2900_8_5_2_auto.rcw +new file mode 100644 +index 0000000..d021306 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2200_700_2900_8_5_2_auto.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2900 MT/s ++ * ++ * Silicon 1.0 ++ */ ++ ++#define LX_SR 1 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_700_2900_8_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2200_700_2900_8_5_2_sdhc.rcw +index 90cd09c..55e6b2b 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2200_700_2900_8_5_2_sdhc.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2200_700_2900_8_5_2_sdhc.rcw +@@ -13,7 +13,7 @@ + */ + + #define LX_SR 1 +-#define LX_BOOTSOURCE_SDHC1 ++#define LX_BOOTSOURCE_SDHC + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_700_3200_8_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2200_700_3200_8_5_2_auto.rcw +new file mode 100644 +index 0000000..bfef1d4 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2200_700_3200_8_5_2_auto.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 3200 MT/s ++ * ++ * Silicon 1.0 ++ */ ++ ++#define LX_SR 1 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_700_3200_8_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2200_700_3200_8_5_2_sdhc.rcw +index 88731fa..2978d72 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2200_700_3200_8_5_2_sdhc.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2200_700_3200_8_5_2_sdhc.rcw +@@ -13,7 +13,7 @@ + */ + + #define LX_SR 1 +-#define LX_BOOTSOURCE_SDHC1 ++#define LX_BOOTSOURCE_SDHC + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> +diff --git a/lx2160acex7/include/common_pbi.rcwi b/lx2160acex7/include/common_pbi.rcwi +index 36b723d..7dd4be7 100644 +--- a/lx2160acex7/include/common_pbi.rcwi ++++ b/lx2160acex7/include/common_pbi.rcwi +@@ -10,13 +10,6 @@ write 0x2320000,0x20000000 + /* Errata to write on scratch reg for validation */ + #include <../lx2160asi/scratchrw1.rcw> + +-/* Set Boot Location Pointer (Fall-back when unset is BOOT_LOC) */ +-#if defined(LX_BOOTSOURCE_SDHC1) +-#include <../lx2160asi/bootlocptr_sd.rcw> +-#elif defined(LX_BOOTSOURCE_XSPI) +-#include <../lx2160asi/bootlocptr_nor.rcw> +-#endif +- + /* Errata for SATA controller */ + #include <../lx2160asi/a010554.rcw> + +@@ -57,3 +50,12 @@ write 0x2320000,0x20000000 + .pbi + write 0x1e00900,0x00000014 + .end ++ ++/* Set Boot Location Pointer (Fall-back when unset is BOOT_LOC) */ ++#if defined(LX_BOOTSOURCE_SDHC) ++#include <../lx2160asi/bootlocptr_sd.rcw> ++#elif defined(LX_BOOTSOURCE_XSPI) ++#include <../lx2160asi/bootlocptr_nor.rcw> ++#else ++#include <../lx2160asi/bootlocptr_auto.rcw> ++#endif +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_8_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_8_5_2_auto.rcw +new file mode 100644 +index 0000000..1c23c5c +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_8_5_2_auto.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2400 MT/s ++ * ++ * Silicon 2.0 ++ */ ++ ++#define LX_SR 2 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_8_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_8_5_2_sdhc.rcw +index b77ed2c..c7b307e 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_8_5_2_sdhc.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2400_8_5_2_sdhc.rcw +@@ -13,7 +13,7 @@ + */ + + #define LX_SR 2 +-#define LX_BOOTSOURCE_SDHC1 ++#define LX_BOOTSOURCE_SDHC + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_8_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_8_5_2_auto.rcw +new file mode 100644 +index 0000000..87391ab +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_8_5_2_auto.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2600 MT/s ++ * ++ * Silicon 2.0 ++ */ ++ ++#define LX_SR 2 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_8_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_8_5_2_sdhc.rcw +index 2d19602..a4c254c 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_8_5_2_sdhc.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2600_8_5_2_sdhc.rcw +@@ -13,7 +13,7 @@ + */ + + #define LX_SR 2 +-#define LX_BOOTSOURCE_SDHC1 ++#define LX_BOOTSOURCE_SDHC + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_8_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_8_5_2_auto.rcw +new file mode 100644 +index 0000000..9114f36 +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_8_5_2_auto.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2900 MT/s ++ * ++ * Silicon 2.0 ++ */ ++ ++#define LX_SR 2 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_8_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_8_5_2_sdhc.rcw +index d141116..88ea5f2 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_8_5_2_sdhc.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2900_8_5_2_sdhc.rcw +@@ -13,7 +13,7 @@ + */ + + #define LX_SR 2 +-#define LX_BOOTSOURCE_SDHC1 ++#define LX_BOOTSOURCE_SDHC + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_8_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_8_5_2_auto.rcw +new file mode 100644 +index 0000000..7e97984 +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_8_5_2_auto.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 3200 MT/s ++ * ++ * Silicon 2.0 ++ */ ++ ++#define LX_SR 2 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_8_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_8_5_2_sdhc.rcw +index 8b5ec8d..486ade8 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_8_5_2_sdhc.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_3200_8_5_2_sdhc.rcw +@@ -13,7 +13,7 @@ + */ + + #define LX_SR 2 +-#define LX_BOOTSOURCE_SDHC1 ++#define LX_BOOTSOURCE_SDHC + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2400_8_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2400_8_5_2_auto.rcw +new file mode 100644 +index 0000000..d59ceed +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2400_8_5_2_auto.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2400 MT/s ++ * ++ * Silicon 2.0 ++ */ ++ ++#define LX_SR 2 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2400_8_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2400_8_5_2_sdhc.rcw +index 7763a4a..20f7d58 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2400_8_5_2_sdhc.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2400_8_5_2_sdhc.rcw +@@ -13,7 +13,7 @@ + */ + + #define LX_SR 2 +-#define LX_BOOTSOURCE_SDHC1 ++#define LX_BOOTSOURCE_SDHC + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2600_8_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2600_8_5_2_auto.rcw +new file mode 100644 +index 0000000..1bf815b +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2600_8_5_2_auto.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2600 MT/s ++ * ++ * Silicon 2.0 ++ */ ++ ++#define LX_SR 2 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2600_8_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2600_8_5_2_sdhc.rcw +index b238680..0f93cf2 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2600_8_5_2_sdhc.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2600_8_5_2_sdhc.rcw +@@ -13,7 +13,7 @@ + */ + + #define LX_SR 2 +-#define LX_BOOTSOURCE_SDHC1 ++#define LX_BOOTSOURCE_SDHC + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2900_8_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2900_8_5_2_auto.rcw +new file mode 100644 +index 0000000..01138dc +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2900_8_5_2_auto.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2900 MT/s ++ * ++ * Silicon 2.0 ++ */ ++ ++#define LX_SR 2 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2900_8_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2900_8_5_2_sdhc.rcw +index 46b16ab..a06759e 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2900_8_5_2_sdhc.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2900_8_5_2_sdhc.rcw +@@ -13,7 +13,7 @@ + */ + + #define LX_SR 2 +-#define LX_BOOTSOURCE_SDHC1 ++#define LX_BOOTSOURCE_SDHC + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_3200_8_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_3200_8_5_2_auto.rcw +new file mode 100644 +index 0000000..e99a12b +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_3200_8_5_2_auto.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 3200 MT/s ++ * ++ * Silicon 2.0 ++ */ ++ ++#define LX_SR 2 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_3200_8_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_3200_8_5_2_sdhc.rcw +index dc9180f..dbc0a91 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_3200_8_5_2_sdhc.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_3200_8_5_2_sdhc.rcw +@@ -13,7 +13,7 @@ + */ + + #define LX_SR 2 +-#define LX_BOOTSOURCE_SDHC1 ++#define LX_BOOTSOURCE_SDHC + #include <../lx2160asi/lx2160a.rcwi> + #include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> +diff --git a/lx2160asi/bootlocptr_auto.rcw b/lx2160asi/bootlocptr_auto.rcw +new file mode 100644 +index 0000000..24c7286 +--- /dev/null ++++ b/lx2160asi/bootlocptr_auto.rcw +@@ -0,0 +1,60 @@ ++/* ++ * Generic code for auto booting. ++ * ++ * For each boot source test rcw source, and set bootlocl/h accordingly. ++ * ++ * For single boot-source atf create_pbl adds block copy commands ++ * and sets boot location pointer. ++ * Automatic boot relies on rcw to include those commands; ++ * create_pbl merely replaces their arguments. ++ * ++ * Copyright 2020 Rabeeh Khoury ++ * Copyright 2024 Josua Mayer ++ * ++ * Changelog: ++ * - 28/09/2024: changed formatting and comments ++ */ ++.pbi ++/* Load condition PORSR1 and mask RCW_SRC */ ++loadc 0x01e00000,0x07800000 ++ ++/* If it is 0x8 << 23 (SDHC1) then skip the following jump command */ ++jumpc 0x00000014,0x04000000 ++ ++/* skip sdhc1 boot */ ++jump 0x28 /* this jump + blockcopy + write = (4+4+4+4)+(4+4)+2x(4+4)=40 bytes */ ++/* copy blocks from sdhc1 (atf create_pbl will fixup arguments) */ ++blockcopy 0x08,0x0000a000,0x1800d000,0x00020000 ++ ++/* set boot location pointer for sdhc */ ++write 0x01e00400,0x1800d000 ++write 0x01e00404,0x00000000 ++ ++/* If it is 0x9 << 23 (SDHC2) then skip the following jump command */ ++loadc 0x01e00000,0x07800000 ++jumpc 0x00000014,0x04800000 ++ ++/* skip sdhc2 boot */ ++jump 0x28 /* this jump + blockcopy + write = (4+4+4+4)+(4+4)+2x(4+4)=40 bytes */ ++ ++/* copy blocks from sdhc1 (atf create_pbl will fixup arguments) */ ++blockcopy 0x09,0x0000a000,0x1800d000,0x00020000 ++ ++/* set boot location pointer for sdhc */ ++write 0x01e00400,0x1800d000 ++write 0x01e00404,0x00000000 ++ ++/* If it is 0xf << 23 (XSPI) then skip the following jump command */ ++loadc 0x01e00000,0x07800000 ++jumpc 0x00000014,0x07800000 ++ ++/* skip xspi boot */ ++jump 0x28 /* this jump + blockcopy + write = (4+4+4+4)+(4+4)+2x(4+4)=40 bytes */ ++ ++/* copy blocks from xspi (atf create_pbl will fixup arguments) */ ++blockcopy 0x0f,0x20009000,0x1800d000,0x00020000 ++ ++/* set boot location pointer for xspi */ ++write 0x01e00400,0x20100000 ++write 0x01e00404,0x00000000 ++.end +-- +2.43.0 + diff --git a/recipes-bsp/rcw/files/0007-bootlocptr-reduce-size-of-pbi-section.patch b/recipes-bsp/rcw/files/0007-bootlocptr-reduce-size-of-pbi-section.patch new file mode 100644 index 0000000..7ca4db4 --- /dev/null +++ b/recipes-bsp/rcw/files/0007-bootlocptr-reduce-size-of-pbi-section.patch @@ -0,0 +1,90 @@ +From 86b80b4442027c2fa4f22bb3aa602abb0e15ff85 Mon Sep 17 00:00:00 2001 +From: Josua Mayer +Date: Mon, 7 Oct 2024 14:37:13 +0200 +Subject: [PATCH] bootlocptr: reduce size of pbi section + +- Remove duplicate 'loadc' commands, the condition register value is not + affected by 'jump' and 'jumpc'. Saves 6 words. +- Remove 'write' command for bootlocptr high byte, its value zero is + shared by all boot sources and implicitly initialised. Saves 6 words. + +Signed-off-by: Josua Mayer +--- + lx2160asi/bootlocptr_auto.rcw | 31 +++++++++++-------------------- + 1 file changed, 11 insertions(+), 20 deletions(-) + +diff --git a/lx2160asi/bootlocptr_auto.rcw b/lx2160asi/bootlocptr_auto.rcw +index 24c7286..08e7916 100644 +--- a/lx2160asi/bootlocptr_auto.rcw ++++ b/lx2160asi/bootlocptr_auto.rcw +@@ -5,56 +5,47 @@ + * + * For single boot-source atf create_pbl adds block copy commands + * and sets boot location pointer. +- * Automatic boot relies on rcw to include those commands; +- * create_pbl merely replaces their arguments. ++ * Automatic boot relies on rcw to include the blockcopy and bootlocptr ++ * commands, create_pbl then replaces their arguments. + * + * Copyright 2020 Rabeeh Khoury + * Copyright 2024 Josua Mayer + * + * Changelog: + * - 28/09/2024: changed formatting and comments ++ * - 07/10/2024: removed unnecessary commands to reduce size + */ + .pbi + /* Load condition PORSR1 and mask RCW_SRC */ + loadc 0x01e00000,0x07800000 + +-/* If it is 0x8 << 23 (SDHC1) then skip the following jump command */ ++/* If condition is 0x8 << 23 (SDHC1) then skip the following jump command */ + jumpc 0x00000014,0x04000000 + + /* skip sdhc1 boot */ +-jump 0x28 /* this jump + blockcopy + write = (4+4+4+4)+(4+4)+2x(4+4)=40 bytes */ ++jump 0x20 /* this jump + blockcopy = (4+4+4+4)+(4+4)=24 bytes */ ++ + /* copy blocks from sdhc1 (atf create_pbl will fixup arguments) */ + blockcopy 0x08,0x0000a000,0x1800d000,0x00020000 +- +-/* set boot location pointer for sdhc */ + write 0x01e00400,0x1800d000 +-write 0x01e00404,0x00000000 + +-/* If it is 0x9 << 23 (SDHC2) then skip the following jump command */ +-loadc 0x01e00000,0x07800000 ++/* If condition is 0x9 << 23 (SDHC2) then skip the following jump command */ + jumpc 0x00000014,0x04800000 + + /* skip sdhc2 boot */ +-jump 0x28 /* this jump + blockcopy + write = (4+4+4+4)+(4+4)+2x(4+4)=40 bytes */ ++jump 0x20 /* this jump + blockcopy = (4+4+4+4)+(4+4)=24 bytes */ + + /* copy blocks from sdhc1 (atf create_pbl will fixup arguments) */ + blockcopy 0x09,0x0000a000,0x1800d000,0x00020000 +- +-/* set boot location pointer for sdhc */ + write 0x01e00400,0x1800d000 +-write 0x01e00404,0x00000000 + +-/* If it is 0xf << 23 (XSPI) then skip the following jump command */ +-loadc 0x01e00000,0x07800000 ++/* If condition is 0xf << 23 (XSPI) then skip the following jump command */ + jumpc 0x00000014,0x07800000 + + /* skip xspi boot */ +-jump 0x28 /* this jump + blockcopy + write = (4+4+4+4)+(4+4)+2x(4+4)=40 bytes */ ++jump 0x20 /* this jump + blockcopy = (4+4+4+4)+(4+4)=24 bytes */ + + /* copy blocks from xspi (atf create_pbl will fixup arguments) */ + blockcopy 0x0f,0x20009000,0x1800d000,0x00020000 +- +-/* set boot location pointer for xspi */ +-write 0x01e00400,0x20100000 +-write 0x01e00404,0x00000000 ++write 0x01e00400,0x1800d000 + .end +-- +2.43.0 + diff --git a/recipes-bsp/rcw/files/0008-lx2160acex7-change-2.2GHz-configuration-platform-clo.patch b/recipes-bsp/rcw/files/0008-lx2160acex7-change-2.2GHz-configuration-platform-clo.patch new file mode 100644 index 0000000..fbbbdff --- /dev/null +++ b/recipes-bsp/rcw/files/0008-lx2160acex7-change-2.2GHz-configuration-platform-clo.patch @@ -0,0 +1,475 @@ +From 7ef0c57ae7c852bb8f35310b0bd5708bb2a98c4a Mon Sep 17 00:00:00 2001 +From: Josua Mayer +Date: Tue, 8 Oct 2024 12:30:42 +0200 +Subject: [PATCH 8/9] lx2160acex7: change 2.2GHz configuration platform clock + to 750MHz + +2.2GHz cpu clock is only for accordingly binned part number from NXP. +These parts support platform clock up to 750MHz. + +Update the configuration accordingly to 2200_750_xxxx and drop the +combination with 2200_700. + +Signed-off-by: Josua Mayer +--- + ...2400_8_5_2_auto.rcw => rcw_2200_750_2400_8_5_2_auto.rcw} | 2 +- + ...2400_8_5_2_sdhc.rcw => rcw_2200_750_2400_8_5_2_sdhc.rcw} | 2 +- + ...2400_8_5_2_xspi.rcw => rcw_2200_750_2400_8_5_2_xspi.rcw} | 2 +- + ...2600_8_5_2_auto.rcw => rcw_2200_750_2600_8_5_2_auto.rcw} | 2 +- + ...2600_8_5_2_sdhc.rcw => rcw_2200_750_2600_8_5_2_sdhc.rcw} | 2 +- + ...2600_8_5_2_xspi.rcw => rcw_2200_750_2600_8_5_2_xspi.rcw} | 2 +- + ...2900_8_5_2_auto.rcw => rcw_2200_750_2900_8_5_2_auto.rcw} | 2 +- + ...2900_8_5_2_sdhc.rcw => rcw_2200_750_2900_8_5_2_sdhc.rcw} | 2 +- + ...2900_8_5_2_xspi.rcw => rcw_2200_750_2900_8_5_2_xspi.rcw} | 2 +- + ...3200_8_5_2_auto.rcw => rcw_2200_750_3200_8_5_2_auto.rcw} | 2 +- + ...3200_8_5_2_sdhc.rcw => rcw_2200_750_3200_8_5_2_sdhc.rcw} | 2 +- + ...3200_8_5_2_xspi.rcw => rcw_2200_750_3200_8_5_2_xspi.rcw} | 2 +- + .../{pll_2200_700_xxxx.rcwi => pll_2200_750_xxxx.rcwi} | 6 +++--- + ...2400_8_5_2_auto.rcw => rcw_2200_750_2400_8_5_2_auto.rcw} | 2 +- + ...2400_8_5_2_sdhc.rcw => rcw_2200_750_2400_8_5_2_sdhc.rcw} | 2 +- + ...2400_8_5_2_xspi.rcw => rcw_2200_750_2400_8_5_2_xspi.rcw} | 2 +- + ...2600_8_5_2_auto.rcw => rcw_2200_750_2600_8_5_2_auto.rcw} | 2 +- + ...2600_8_5_2_sdhc.rcw => rcw_2200_750_2600_8_5_2_sdhc.rcw} | 2 +- + ...2600_8_5_2_xspi.rcw => rcw_2200_750_2600_8_5_2_xspi.rcw} | 2 +- + ...2900_8_5_2_auto.rcw => rcw_2200_750_2900_8_5_2_auto.rcw} | 2 +- + ...2900_8_5_2_sdhc.rcw => rcw_2200_750_2900_8_5_2_sdhc.rcw} | 2 +- + ...2900_8_5_2_xspi.rcw => rcw_2200_750_2900_8_5_2_xspi.rcw} | 2 +- + ...3200_8_5_2_auto.rcw => rcw_2200_750_3200_8_5_2_auto.rcw} | 2 +- + ...3200_8_5_2_sdhc.rcw => rcw_2200_750_3200_8_5_2_sdhc.rcw} | 2 +- + ...3200_8_5_2_xspi.rcw => rcw_2200_750_3200_8_5_2_xspi.rcw} | 2 +- + 25 files changed, 27 insertions(+), 27 deletions(-) + rename lx2160acex7/clearfog-cx/{rcw_2200_700_2400_8_5_2_auto.rcw => rcw_2200_750_2400_8_5_2_auto.rcw} (91%) + rename lx2160acex7/clearfog-cx/{rcw_2200_700_2400_8_5_2_sdhc.rcw => rcw_2200_750_2400_8_5_2_sdhc.rcw} (91%) + rename lx2160acex7/clearfog-cx/{rcw_2200_700_2400_8_5_2_xspi.rcw => rcw_2200_750_2400_8_5_2_xspi.rcw} (91%) + rename lx2160acex7/clearfog-cx/{rcw_2200_700_2600_8_5_2_auto.rcw => rcw_2200_750_2600_8_5_2_auto.rcw} (91%) + rename lx2160acex7/clearfog-cx/{rcw_2200_700_2600_8_5_2_sdhc.rcw => rcw_2200_750_2600_8_5_2_sdhc.rcw} (91%) + rename lx2160acex7/clearfog-cx/{rcw_2200_700_2600_8_5_2_xspi.rcw => rcw_2200_750_2600_8_5_2_xspi.rcw} (91%) + rename lx2160acex7/clearfog-cx/{rcw_2200_700_2900_8_5_2_auto.rcw => rcw_2200_750_2900_8_5_2_auto.rcw} (91%) + rename lx2160acex7/clearfog-cx/{rcw_2200_700_2900_8_5_2_sdhc.rcw => rcw_2200_750_2900_8_5_2_sdhc.rcw} (91%) + rename lx2160acex7/clearfog-cx/{rcw_2200_700_2900_8_5_2_xspi.rcw => rcw_2200_750_2900_8_5_2_xspi.rcw} (91%) + rename lx2160acex7/clearfog-cx/{rcw_2200_700_3200_8_5_2_auto.rcw => rcw_2200_750_3200_8_5_2_auto.rcw} (91%) + rename lx2160acex7/clearfog-cx/{rcw_2200_700_3200_8_5_2_sdhc.rcw => rcw_2200_750_3200_8_5_2_sdhc.rcw} (91%) + rename lx2160acex7/clearfog-cx/{rcw_2200_700_3200_8_5_2_xspi.rcw => rcw_2200_750_3200_8_5_2_xspi.rcw} (91%) + rename lx2160acex7/include/{pll_2200_700_xxxx.rcwi => pll_2200_750_xxxx.rcwi} (61%) + rename lx2160acex7_rev2/clearfog-cx/{rcw_2200_700_2400_8_5_2_auto.rcw => rcw_2200_750_2400_8_5_2_auto.rcw} (91%) + rename lx2160acex7_rev2/clearfog-cx/{rcw_2200_700_2400_8_5_2_sdhc.rcw => rcw_2200_750_2400_8_5_2_sdhc.rcw} (91%) + rename lx2160acex7_rev2/clearfog-cx/{rcw_2200_700_2400_8_5_2_xspi.rcw => rcw_2200_750_2400_8_5_2_xspi.rcw} (91%) + rename lx2160acex7_rev2/clearfog-cx/{rcw_2200_700_2600_8_5_2_auto.rcw => rcw_2200_750_2600_8_5_2_auto.rcw} (91%) + rename lx2160acex7_rev2/clearfog-cx/{rcw_2200_700_2600_8_5_2_sdhc.rcw => rcw_2200_750_2600_8_5_2_sdhc.rcw} (91%) + rename lx2160acex7_rev2/clearfog-cx/{rcw_2200_700_2600_8_5_2_xspi.rcw => rcw_2200_750_2600_8_5_2_xspi.rcw} (91%) + rename lx2160acex7_rev2/clearfog-cx/{rcw_2200_700_2900_8_5_2_auto.rcw => rcw_2200_750_2900_8_5_2_auto.rcw} (91%) + rename lx2160acex7_rev2/clearfog-cx/{rcw_2200_700_2900_8_5_2_sdhc.rcw => rcw_2200_750_2900_8_5_2_sdhc.rcw} (91%) + rename lx2160acex7_rev2/clearfog-cx/{rcw_2200_700_2900_8_5_2_xspi.rcw => rcw_2200_750_2900_8_5_2_xspi.rcw} (91%) + rename lx2160acex7_rev2/clearfog-cx/{rcw_2200_700_3200_8_5_2_auto.rcw => rcw_2200_750_3200_8_5_2_auto.rcw} (91%) + rename lx2160acex7_rev2/clearfog-cx/{rcw_2200_700_3200_8_5_2_sdhc.rcw => rcw_2200_750_3200_8_5_2_sdhc.rcw} (91%) + rename lx2160acex7_rev2/clearfog-cx/{rcw_2200_700_3200_8_5_2_xspi.rcw => rcw_2200_750_3200_8_5_2_xspi.rcw} (91%) + +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_700_2400_8_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2400_8_5_2_auto.rcw +similarity index 91% +rename from lx2160acex7/clearfog-cx/rcw_2200_700_2400_8_5_2_auto.rcw +rename to lx2160acex7/clearfog-cx/rcw_2200_750_2400_8_5_2_auto.rcw +index 464a285..533fba1 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2200_700_2400_8_5_2_auto.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2400_8_5_2_auto.rcw +@@ -13,7 +13,7 @@ + + #define LX_SR 1 + #include <../lx2160asi/lx2160a.rcwi> +-#include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> + #include <../lx2160acex7/include/common.rcwi> + #include <../lx2160acex7/include/SD1_8.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_700_2400_8_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2400_8_5_2_sdhc.rcw +similarity index 91% +rename from lx2160acex7/clearfog-cx/rcw_2200_700_2400_8_5_2_sdhc.rcw +rename to lx2160acex7/clearfog-cx/rcw_2200_750_2400_8_5_2_sdhc.rcw +index 6f696f5..845ab35 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2200_700_2400_8_5_2_sdhc.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2400_8_5_2_sdhc.rcw +@@ -15,7 +15,7 @@ + #define LX_SR 1 + #define LX_BOOTSOURCE_SDHC + #include <../lx2160asi/lx2160a.rcwi> +-#include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> + #include <../lx2160acex7/include/common.rcwi> + #include <../lx2160acex7/include/SD1_8.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_700_2400_8_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2400_8_5_2_xspi.rcw +similarity index 91% +rename from lx2160acex7/clearfog-cx/rcw_2200_700_2400_8_5_2_xspi.rcw +rename to lx2160acex7/clearfog-cx/rcw_2200_750_2400_8_5_2_xspi.rcw +index f23be28..765758e 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2200_700_2400_8_5_2_xspi.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2400_8_5_2_xspi.rcw +@@ -15,7 +15,7 @@ + #define LX_SR 1 + #define LX_BOOTSOURCE_XSPI + #include <../lx2160asi/lx2160a.rcwi> +-#include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> + #include <../lx2160acex7/include/common.rcwi> + #include <../lx2160acex7/include/SD1_8.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_700_2600_8_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2600_8_5_2_auto.rcw +similarity index 91% +rename from lx2160acex7/clearfog-cx/rcw_2200_700_2600_8_5_2_auto.rcw +rename to lx2160acex7/clearfog-cx/rcw_2200_750_2600_8_5_2_auto.rcw +index 1ef7db6..c09807c 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2200_700_2600_8_5_2_auto.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2600_8_5_2_auto.rcw +@@ -13,7 +13,7 @@ + + #define LX_SR 1 + #include <../lx2160asi/lx2160a.rcwi> +-#include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> + #include <../lx2160acex7/include/common.rcwi> + #include <../lx2160acex7/include/SD1_8.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_700_2600_8_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2600_8_5_2_sdhc.rcw +similarity index 91% +rename from lx2160acex7/clearfog-cx/rcw_2200_700_2600_8_5_2_sdhc.rcw +rename to lx2160acex7/clearfog-cx/rcw_2200_750_2600_8_5_2_sdhc.rcw +index 46d84cb..7808b12 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2200_700_2600_8_5_2_sdhc.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2600_8_5_2_sdhc.rcw +@@ -15,7 +15,7 @@ + #define LX_SR 1 + #define LX_BOOTSOURCE_SDHC + #include <../lx2160asi/lx2160a.rcwi> +-#include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> + #include <../lx2160acex7/include/common.rcwi> + #include <../lx2160acex7/include/SD1_8.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_700_2600_8_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2600_8_5_2_xspi.rcw +similarity index 91% +rename from lx2160acex7/clearfog-cx/rcw_2200_700_2600_8_5_2_xspi.rcw +rename to lx2160acex7/clearfog-cx/rcw_2200_750_2600_8_5_2_xspi.rcw +index 62cf89e..33bef8b 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2200_700_2600_8_5_2_xspi.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2600_8_5_2_xspi.rcw +@@ -15,7 +15,7 @@ + #define LX_SR 1 + #define LX_BOOTSOURCE_XSPI + #include <../lx2160asi/lx2160a.rcwi> +-#include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> + #include <../lx2160acex7/include/common.rcwi> + #include <../lx2160acex7/include/SD1_8.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_700_2900_8_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2900_8_5_2_auto.rcw +similarity index 91% +rename from lx2160acex7/clearfog-cx/rcw_2200_700_2900_8_5_2_auto.rcw +rename to lx2160acex7/clearfog-cx/rcw_2200_750_2900_8_5_2_auto.rcw +index d021306..0f3d8a3 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2200_700_2900_8_5_2_auto.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2900_8_5_2_auto.rcw +@@ -13,7 +13,7 @@ + + #define LX_SR 1 + #include <../lx2160asi/lx2160a.rcwi> +-#include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> + #include <../lx2160acex7/include/common.rcwi> + #include <../lx2160acex7/include/SD1_8.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_700_2900_8_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2900_8_5_2_sdhc.rcw +similarity index 91% +rename from lx2160acex7/clearfog-cx/rcw_2200_700_2900_8_5_2_sdhc.rcw +rename to lx2160acex7/clearfog-cx/rcw_2200_750_2900_8_5_2_sdhc.rcw +index 55e6b2b..68452e0 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2200_700_2900_8_5_2_sdhc.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2900_8_5_2_sdhc.rcw +@@ -15,7 +15,7 @@ + #define LX_SR 1 + #define LX_BOOTSOURCE_SDHC + #include <../lx2160asi/lx2160a.rcwi> +-#include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> + #include <../lx2160acex7/include/common.rcwi> + #include <../lx2160acex7/include/SD1_8.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_700_2900_8_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2900_8_5_2_xspi.rcw +similarity index 91% +rename from lx2160acex7/clearfog-cx/rcw_2200_700_2900_8_5_2_xspi.rcw +rename to lx2160acex7/clearfog-cx/rcw_2200_750_2900_8_5_2_xspi.rcw +index 13ec066..0069109 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2200_700_2900_8_5_2_xspi.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2900_8_5_2_xspi.rcw +@@ -15,7 +15,7 @@ + #define LX_SR 1 + #define LX_BOOTSOURCE_XSPI + #include <../lx2160asi/lx2160a.rcwi> +-#include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> + #include <../lx2160acex7/include/common.rcwi> + #include <../lx2160acex7/include/SD1_8.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_700_3200_8_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_3200_8_5_2_auto.rcw +similarity index 91% +rename from lx2160acex7/clearfog-cx/rcw_2200_700_3200_8_5_2_auto.rcw +rename to lx2160acex7/clearfog-cx/rcw_2200_750_3200_8_5_2_auto.rcw +index bfef1d4..aa2fb4b 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2200_700_3200_8_5_2_auto.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_3200_8_5_2_auto.rcw +@@ -13,7 +13,7 @@ + + #define LX_SR 1 + #include <../lx2160asi/lx2160a.rcwi> +-#include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> + #include <../lx2160acex7/include/common.rcwi> + #include <../lx2160acex7/include/SD1_8.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_700_3200_8_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_3200_8_5_2_sdhc.rcw +similarity index 91% +rename from lx2160acex7/clearfog-cx/rcw_2200_700_3200_8_5_2_sdhc.rcw +rename to lx2160acex7/clearfog-cx/rcw_2200_750_3200_8_5_2_sdhc.rcw +index 2978d72..6f06730 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2200_700_3200_8_5_2_sdhc.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_3200_8_5_2_sdhc.rcw +@@ -15,7 +15,7 @@ + #define LX_SR 1 + #define LX_BOOTSOURCE_SDHC + #include <../lx2160asi/lx2160a.rcwi> +-#include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> + #include <../lx2160acex7/include/common.rcwi> + #include <../lx2160acex7/include/SD1_8.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_700_3200_8_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_3200_8_5_2_xspi.rcw +similarity index 91% +rename from lx2160acex7/clearfog-cx/rcw_2200_700_3200_8_5_2_xspi.rcw +rename to lx2160acex7/clearfog-cx/rcw_2200_750_3200_8_5_2_xspi.rcw +index b80f8cb..94dcc9b 100644 +--- a/lx2160acex7/clearfog-cx/rcw_2200_700_3200_8_5_2_xspi.rcw ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_3200_8_5_2_xspi.rcw +@@ -15,7 +15,7 @@ + #define LX_SR 1 + #define LX_BOOTSOURCE_XSPI + #include <../lx2160asi/lx2160a.rcwi> +-#include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> + #include <../lx2160acex7/include/common.rcwi> + #include <../lx2160acex7/include/SD1_8.rcwi> +diff --git a/lx2160acex7/include/pll_2200_700_xxxx.rcwi b/lx2160acex7/include/pll_2200_750_xxxx.rcwi +similarity index 61% +rename from lx2160acex7/include/pll_2200_700_xxxx.rcwi +rename to lx2160acex7/include/pll_2200_750_xxxx.rcwi +index 91d1a9b..0f57b67 100644 +--- a/lx2160acex7/include/pll_2200_700_xxxx.rcwi ++++ b/lx2160acex7/include/pll_2200_750_xxxx.rcwi +@@ -1,11 +1,11 @@ + /* + * Core and Platform Clocks: +- * - Platform: 700MHz ++ * - Platform: 750MHz + * - Core: 2200MHz + */ + +-/* platform clock is system clock mul 14 div 2 = 700 */ +-SYS_PLL_RAT=14 ++/* platform clock is system clock mul 15 div 2 = 750 */ ++SYS_PLL_RAT=15 + + /* core clocks are 2200 */ + CGA_PLL1_RAT=22 +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2400_8_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_8_5_2_auto.rcw +similarity index 91% +rename from lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2400_8_5_2_auto.rcw +rename to lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_8_5_2_auto.rcw +index d59ceed..4185ea6 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2400_8_5_2_auto.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_8_5_2_auto.rcw +@@ -13,7 +13,7 @@ + + #define LX_SR 2 + #include <../lx2160asi/lx2160a.rcwi> +-#include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> + #include <../lx2160acex7/include/common.rcwi> + #include <../lx2160acex7/include/SD1_8.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2400_8_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_8_5_2_sdhc.rcw +similarity index 91% +rename from lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2400_8_5_2_sdhc.rcw +rename to lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_8_5_2_sdhc.rcw +index 20f7d58..93b10d2 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2400_8_5_2_sdhc.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_8_5_2_sdhc.rcw +@@ -15,7 +15,7 @@ + #define LX_SR 2 + #define LX_BOOTSOURCE_SDHC + #include <../lx2160asi/lx2160a.rcwi> +-#include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> + #include <../lx2160acex7/include/common.rcwi> + #include <../lx2160acex7/include/SD1_8.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2400_8_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_8_5_2_xspi.rcw +similarity index 91% +rename from lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2400_8_5_2_xspi.rcw +rename to lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_8_5_2_xspi.rcw +index 9643b52..feb3e42 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2400_8_5_2_xspi.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2400_8_5_2_xspi.rcw +@@ -15,7 +15,7 @@ + #define LX_SR 2 + #define LX_BOOTSOURCE_XSPI + #include <../lx2160asi/lx2160a.rcwi> +-#include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2400.rcwi> + #include <../lx2160acex7/include/common.rcwi> + #include <../lx2160acex7/include/SD1_8.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2600_8_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_8_5_2_auto.rcw +similarity index 91% +rename from lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2600_8_5_2_auto.rcw +rename to lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_8_5_2_auto.rcw +index 1bf815b..e04fcfb 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2600_8_5_2_auto.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_8_5_2_auto.rcw +@@ -13,7 +13,7 @@ + + #define LX_SR 2 + #include <../lx2160asi/lx2160a.rcwi> +-#include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> + #include <../lx2160acex7/include/common.rcwi> + #include <../lx2160acex7/include/SD1_8.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2600_8_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_8_5_2_sdhc.rcw +similarity index 91% +rename from lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2600_8_5_2_sdhc.rcw +rename to lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_8_5_2_sdhc.rcw +index 0f93cf2..32225fe 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2600_8_5_2_sdhc.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_8_5_2_sdhc.rcw +@@ -15,7 +15,7 @@ + #define LX_SR 2 + #define LX_BOOTSOURCE_SDHC + #include <../lx2160asi/lx2160a.rcwi> +-#include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> + #include <../lx2160acex7/include/common.rcwi> + #include <../lx2160acex7/include/SD1_8.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2600_8_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_8_5_2_xspi.rcw +similarity index 91% +rename from lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2600_8_5_2_xspi.rcw +rename to lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_8_5_2_xspi.rcw +index 79cea0d..6fbba40 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2600_8_5_2_xspi.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2600_8_5_2_xspi.rcw +@@ -15,7 +15,7 @@ + #define LX_SR 2 + #define LX_BOOTSOURCE_XSPI + #include <../lx2160asi/lx2160a.rcwi> +-#include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2600.rcwi> + #include <../lx2160acex7/include/common.rcwi> + #include <../lx2160acex7/include/SD1_8.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2900_8_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_8_5_2_auto.rcw +similarity index 91% +rename from lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2900_8_5_2_auto.rcw +rename to lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_8_5_2_auto.rcw +index 01138dc..b9797ca 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2900_8_5_2_auto.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_8_5_2_auto.rcw +@@ -13,7 +13,7 @@ + + #define LX_SR 2 + #include <../lx2160asi/lx2160a.rcwi> +-#include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> + #include <../lx2160acex7/include/common.rcwi> + #include <../lx2160acex7/include/SD1_8.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2900_8_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_8_5_2_sdhc.rcw +similarity index 91% +rename from lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2900_8_5_2_sdhc.rcw +rename to lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_8_5_2_sdhc.rcw +index a06759e..a7b5bd2 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2900_8_5_2_sdhc.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_8_5_2_sdhc.rcw +@@ -15,7 +15,7 @@ + #define LX_SR 2 + #define LX_BOOTSOURCE_SDHC + #include <../lx2160asi/lx2160a.rcwi> +-#include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> + #include <../lx2160acex7/include/common.rcwi> + #include <../lx2160acex7/include/SD1_8.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2900_8_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_8_5_2_xspi.rcw +similarity index 91% +rename from lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2900_8_5_2_xspi.rcw +rename to lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_8_5_2_xspi.rcw +index b12898a..273d91c 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_2900_8_5_2_xspi.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2900_8_5_2_xspi.rcw +@@ -15,7 +15,7 @@ + #define LX_SR 2 + #define LX_BOOTSOURCE_XSPI + #include <../lx2160asi/lx2160a.rcwi> +-#include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi> + #include <../lx2160acex7/include/common.rcwi> + #include <../lx2160acex7/include/SD1_8.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_3200_8_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_8_5_2_auto.rcw +similarity index 91% +rename from lx2160acex7_rev2/clearfog-cx/rcw_2200_700_3200_8_5_2_auto.rcw +rename to lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_8_5_2_auto.rcw +index e99a12b..046adc8 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_3200_8_5_2_auto.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_8_5_2_auto.rcw +@@ -13,7 +13,7 @@ + + #define LX_SR 2 + #include <../lx2160asi/lx2160a.rcwi> +-#include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> + #include <../lx2160acex7/include/common.rcwi> + #include <../lx2160acex7/include/SD1_8.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_3200_8_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_8_5_2_sdhc.rcw +similarity index 91% +rename from lx2160acex7_rev2/clearfog-cx/rcw_2200_700_3200_8_5_2_sdhc.rcw +rename to lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_8_5_2_sdhc.rcw +index dbc0a91..9798b74 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_3200_8_5_2_sdhc.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_8_5_2_sdhc.rcw +@@ -15,7 +15,7 @@ + #define LX_SR 2 + #define LX_BOOTSOURCE_SDHC + #include <../lx2160asi/lx2160a.rcwi> +-#include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> + #include <../lx2160acex7/include/common.rcwi> + #include <../lx2160acex7/include/SD1_8.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_3200_8_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_8_5_2_xspi.rcw +similarity index 91% +rename from lx2160acex7_rev2/clearfog-cx/rcw_2200_700_3200_8_5_2_xspi.rcw +rename to lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_8_5_2_xspi.rcw +index c2ff13a..6b875e7 100644 +--- a/lx2160acex7_rev2/clearfog-cx/rcw_2200_700_3200_8_5_2_xspi.rcw ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_3200_8_5_2_xspi.rcw +@@ -15,7 +15,7 @@ + #define LX_SR 2 + #define LX_BOOTSOURCE_XSPI + #include <../lx2160asi/lx2160a.rcwi> +-#include <../lx2160acex7/include/pll_2200_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> + #include <../lx2160acex7/include/pll_xxxx_xxx_3200.rcwi> + #include <../lx2160acex7/include/common.rcwi> + #include <../lx2160acex7/include/SD1_8.rcwi> +-- +2.43.0 + diff --git a/recipes-bsp/rcw/files/0009-lx2160acex7-add-configuration-for-fraction-ddr-speed.patch b/recipes-bsp/rcw/files/0009-lx2160acex7-add-configuration-for-fraction-ddr-speed.patch new file mode 100644 index 0000000..0e68066 --- /dev/null +++ b/recipes-bsp/rcw/files/0009-lx2160acex7-add-configuration-for-fraction-ddr-speed.patch @@ -0,0 +1,420 @@ +From 51af4e2a98e234e27a0127b2455b6049ce8097e2 Mon Sep 17 00:00:00 2001 +From: Josua Mayer +Date: Tue, 8 Oct 2024 12:44:10 +0200 +Subject: [PATCH] lx2160acex7: add configuration for fraction ddr speed 2666 + +Signed-off-by: Josua Mayer +--- + .../rcw_2000_700_2666_8_5_2_auto.rcw | 23 +++++++++++++++++ + .../rcw_2000_700_2666_8_5_2_sdhc.rcw | 25 +++++++++++++++++++ + .../rcw_2000_700_2666_8_5_2_xspi.rcw | 25 +++++++++++++++++++ + .../rcw_2200_750_2666_8_5_2_auto.rcw | 23 +++++++++++++++++ + .../rcw_2200_750_2666_8_5_2_sdhc.rcw | 25 +++++++++++++++++++ + .../rcw_2200_750_2666_8_5_2_xspi.rcw | 25 +++++++++++++++++++ + lx2160acex7/include/pll_xxxx_xxx_2666.rcwi | 12 +++++++++ + .../rcw_2000_700_2666_8_5_2_auto.rcw | 23 +++++++++++++++++ + .../rcw_2000_700_2666_8_5_2_sdhc.rcw | 25 +++++++++++++++++++ + .../rcw_2000_700_2666_8_5_2_xspi.rcw | 25 +++++++++++++++++++ + .../rcw_2200_750_2666_8_5_2_auto.rcw | 23 +++++++++++++++++ + .../rcw_2200_750_2666_8_5_2_sdhc.rcw | 25 +++++++++++++++++++ + .../rcw_2200_750_2666_8_5_2_xspi.rcw | 25 +++++++++++++++++++ + 13 files changed, 304 insertions(+) + create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2666_8_5_2_auto.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2666_8_5_2_sdhc.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2000_700_2666_8_5_2_xspi.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2666_8_5_2_auto.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2666_8_5_2_sdhc.rcw + create mode 100644 lx2160acex7/clearfog-cx/rcw_2200_750_2666_8_5_2_xspi.rcw + create mode 100644 lx2160acex7/include/pll_xxxx_xxx_2666.rcwi + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_8_5_2_auto.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_8_5_2_sdhc.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_8_5_2_xspi.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_8_5_2_auto.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_8_5_2_sdhc.rcw + create mode 100644 lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_8_5_2_xspi.rcw + +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2666_8_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2666_8_5_2_auto.rcw +new file mode 100644 +index 0000000..8178257 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2666_8_5_2_auto.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2666 MT/s ++ * ++ * Silicon 1.0 ++ */ ++ ++#define LX_SR 1 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2666_8_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2666_8_5_2_sdhc.rcw +new file mode 100644 +index 0000000..6f362cf +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2666_8_5_2_sdhc.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2666 MT/s ++ * ++ * Silicon 1.0 ++ * Boot from SDHC1 ++ */ ++ ++#define LX_SR 1 ++#define LX_BOOTSOURCE_SDHC ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2000_700_2666_8_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2000_700_2666_8_5_2_xspi.rcw +new file mode 100644 +index 0000000..cb6614a +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2000_700_2666_8_5_2_xspi.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2666 MT/s ++ * ++ * Silicon 1.0 ++ * Boot from XSPI ++ */ ++ ++#define LX_SR 1 ++#define LX_BOOTSOURCE_XSPI ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2666_8_5_2_auto.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2666_8_5_2_auto.rcw +new file mode 100644 +index 0000000..6822342 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2666_8_5_2_auto.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2666 MT/s ++ * ++ * Silicon 1.0 ++ */ ++ ++#define LX_SR 1 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2666_8_5_2_sdhc.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2666_8_5_2_sdhc.rcw +new file mode 100644 +index 0000000..f111731 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2666_8_5_2_sdhc.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2666 MT/s ++ * ++ * Silicon 1.0 ++ * Boot from SDHC1 ++ */ ++ ++#define LX_SR 1 ++#define LX_BOOTSOURCE_SDHC ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/clearfog-cx/rcw_2200_750_2666_8_5_2_xspi.rcw b/lx2160acex7/clearfog-cx/rcw_2200_750_2666_8_5_2_xspi.rcw +new file mode 100644 +index 0000000..112f017 +--- /dev/null ++++ b/lx2160acex7/clearfog-cx/rcw_2200_750_2666_8_5_2_xspi.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2666 MT/s ++ * ++ * Silicon 1.0 ++ * Boot from XSPI ++ */ ++ ++#define LX_SR 1 ++#define LX_BOOTSOURCE_XSPI ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7/include/pll_xxxx_xxx_2666.rcwi b/lx2160acex7/include/pll_xxxx_xxx_2666.rcwi +new file mode 100644 +index 0000000..06d3da1 +--- /dev/null ++++ b/lx2160acex7/include/pll_xxxx_xxx_2666.rcwi +@@ -0,0 +1,12 @@ ++/* ++ * DDR Rate: 2666MHz ++ * ++ * DDR PHY Clock (half ddr clock, quarter mts rate) ++ * multiplier = 20 (20) ++ * divider = 3 (2) ++ * 100MHz x 20 / 3 = 666MHz (MTS = 4 x 666 = 2666MHz) ++ */ ++MEM_PLL_RAT=20 ++MEM_PLL_CFG=2 ++MEM2_PLL_RAT=20 ++MEM2_PLL_CFG=2 +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_8_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_8_5_2_auto.rcw +new file mode 100644 +index 0000000..73efdfa +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_8_5_2_auto.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2666 MT/s ++ * ++ * Silicon 2.0 ++ */ ++ ++#define LX_SR 2 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_8_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_8_5_2_sdhc.rcw +new file mode 100644 +index 0000000..5ac0305 +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_8_5_2_sdhc.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2666 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from SDHC1 ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_SDHC ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_8_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_8_5_2_xspi.rcw +new file mode 100644 +index 0000000..ffc7388 +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2000_700_2666_8_5_2_xspi.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2000 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2666 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from XSPI ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_XSPI ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2000_700_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_8_5_2_auto.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_8_5_2_auto.rcw +new file mode 100644 +index 0000000..0206680 +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_8_5_2_auto.rcw +@@ -0,0 +1,23 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2666 MT/s ++ * ++ * Silicon 2.0 ++ */ ++ ++#define LX_SR 2 ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_8_5_2_sdhc.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_8_5_2_sdhc.rcw +new file mode 100644 +index 0000000..0213f6c +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_8_5_2_sdhc.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2666 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from SDHC1 ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_SDHC ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +diff --git a/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_8_5_2_xspi.rcw b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_8_5_2_xspi.rcw +new file mode 100644 +index 0000000..d31d063 +--- /dev/null ++++ b/lx2160acex7_rev2/clearfog-cx/rcw_2200_750_2666_8_5_2_xspi.rcw +@@ -0,0 +1,25 @@ ++/* ++ * SerDes Protocol 1 - 8 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 2200 MHz ++ * Platform -- 700 MHz ++ * DDR -- 2666 MT/s ++ * ++ * Silicon 2.0 ++ * Boot from XSPI ++ */ ++ ++#define LX_SR 2 ++#define LX_BOOTSOURCE_XSPI ++#include <../lx2160asi/lx2160a.rcwi> ++#include <../lx2160acex7/include/pll_2200_750_xxxx.rcwi> ++#include <../lx2160acex7/include/pll_xxxx_xxx_2666.rcwi> ++#include <../lx2160acex7/include/common.rcwi> ++#include <../lx2160acex7/include/SD1_8.rcwi> ++#include <../lx2160acex7/include/SD2_5.rcwi> ++#include <../lx2160acex7/include/SD3_2.rcwi> ++#include <../lx2160acex7/include/common_pbi.rcwi> ++#include <../lx2160acex7/clearfog-cx/sd1_8_eq.rcwi> +-- +2.43.0 + diff --git a/recipes-bsp/rcw/rcw_git.bbappend b/recipes-bsp/rcw/rcw_git.bbappend index fbf3373..86b8d6e 100644 --- a/recipes-bsp/rcw/rcw_git.bbappend +++ b/recipes-bsp/rcw/rcw_git.bbappend @@ -3,6 +3,14 @@ FILESEXTRAPATHS:prepend := "${THISDIR}/files:" # Add SolidRun patches SRC_URI += "file://0001-add-configuration-solidrun-lx2160a-cex-7-on-clearfog.patch \ + file://0002-lx2160acex7-move-MEM_PLL_CFG-into-ddr-speed-specific.patch \ + file://0003-lx2160acex7-add-separate-configurations-for-flexspi-.patch \ + file://0004-lx2160acex7-rename-sdhc1-config-to-generic-sdhc-for-.patch \ + file://0005-add-loadc-jumpc-and-jump-to-pbi-instructions.patch \ + file://0006-lx2160acex7-add-configuration-for-both-sdhc-xspi.patch \ + file://0007-bootlocptr-reduce-size-of-pbi-section.patch \ + file://0008-lx2160acex7-change-2.2GHz-configuration-platform-clo.patch \ + file://0009-lx2160acex7-add-configuration-for-fraction-ddr-speed.patch \ " BOARD_TARGETS:lx2160acex7 = "lx2160acex7 lx2160acex7_rev2" diff --git a/recipes-bsp/u-boot/2022.04-solidrun/0004-fsl-lsch3-update-calculation-of-ddr-clock-rate-to-in.patch b/recipes-bsp/u-boot/2022.04-solidrun/0004-fsl-lsch3-update-calculation-of-ddr-clock-rate-to-in.patch new file mode 100644 index 0000000..a961bd7 --- /dev/null +++ b/recipes-bsp/u-boot/2022.04-solidrun/0004-fsl-lsch3-update-calculation-of-ddr-clock-rate-to-in.patch @@ -0,0 +1,63 @@ +From 7320dd540f97a56f7f7cfcbd0dc2e9fae393a8a1 Mon Sep 17 00:00:00 2001 +From: Josua Mayer +Date: Tue, 8 Oct 2024 13:29:36 +0200 +Subject: [PATCH] fsl-lsch3: update calculation of ddr clock rate to include + divider + +DDR clock is passes through a divider and a multiplier - and is then +again doubled once by the phy and once by the controller. +The doubling was previously hidden by divider default value of 4. + +Take into account the divider value per MEM_PLL_CFG when calculating ddr +bus frequency, and multiply the result by 4. + +Signed-off-by: Josua Mayer +--- + arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c | 8 ++++++++ + arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 4 ++++ + 2 files changed, 12 insertions(+) + +diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c +index 1c04a5b5b7e..29a786bf26c 100644 +--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c ++++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c +@@ -97,11 +97,19 @@ void get_sys_info(struct sys_info *sys_info) + sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >> + FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT) & + FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK; ++ sys_info->freq_ddrbus /= ((gur_in32(&gur->rcwsr[0]) >> ++ FSL_CHASSIS3_RCWSR0_MEM_PLL_CFG_SHIFT) & ++ FSL_CHASSIS3_RCWSR0_MEM_PLL_CFG_MASK) + 1; ++ /* ddr clock is doubled at phy, then doubled again controller */ ++ sys_info->freq_ddrbus *= 4; + #ifdef CONFIG_SYS_FSL_HAS_DP_DDR + if (soc_has_dp_ddr()) { + sys_info->freq_ddrbus2 *= (gur_in32(&gur->rcwsr[0]) >> + FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT) & + FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK; ++ sys_info->freq_ddrbus2 /= ((gur_in32(&gur->rcwsr[0]) >> ++ FSL_CHASSIS3_RCWSR0_MEM2_PLL_CFG_SHIFT) & ++ FSL_CHASSIS3_RCWSR0_MEM2_PLL_CFG_MASK) + 1; + } else { + sys_info->freq_ddrbus2 = 0; + } +diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +index 863618a5f3d..ec9505fb6f1 100644 +--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h ++++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +@@ -374,8 +374,12 @@ struct ccsr_gur { + + #define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT 2 + #define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK 0x1f ++#define FSL_CHASSIS3_RCWSR0_MEM_PLL_CFG_SHIFT 8 ++#define FSL_CHASSIS3_RCWSR0_MEM_PLL_CFG_MASK 0x3 + #define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT 10 + #define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK 0x3f ++#define FSL_CHASSIS3_RCWSR0_MEM2_PLL_CFG_SHIFT 16 ++#define FSL_CHASSIS3_RCWSR0_MEM2_PLL_CFG_MASK 0x3 + #define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT 18 + #define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK 0x3f + +-- +2.43.0 + diff --git a/recipes-bsp/u-boot/u-boot-qoriq_2022.04.bbappend b/recipes-bsp/u-boot/u-boot-qoriq_2022.04.bbappend index 7ee1327..1a06bb8 100644 --- a/recipes-bsp/u-boot/u-boot-qoriq_2022.04.bbappend +++ b/recipes-bsp/u-boot/u-boot-qoriq_2022.04.bbappend @@ -5,4 +5,5 @@ FILESEXTRAPATHS:prepend := "${THISDIR}/2022.04-solidrun:" SRC_URI += "file://0001-add-solidrun-lx2160-cex7-board-support.patch \ file://0002-pci-ls_pcie_g4-Wait-100ms-for-Link-Up-in-ls_pcie_g4_.patch \ file://0003-pci-ls_pcie-Wait-100ms-for-Link-Up-in-ls_pcie_probe.patch \ + file://0004-fsl-lsch3-update-calculation-of-ddr-clock-rate-to-in.patch \ " diff --git a/wic/lx2160a-bootimg-sd.wks.in b/wic/lx2160a-bootimg-mmc.wks.in similarity index 77% rename from wic/lx2160a-bootimg-sd.wks.in rename to wic/lx2160a-bootimg-mmc.wks.in index fd7c178..176cf2c 100644 --- a/wic/lx2160a-bootimg-sd.wks.in +++ b/wic/lx2160a-bootimg-mmc.wks.in @@ -1,7 +1,7 @@ -# short-description: Create SD card image with a boot partition +# short-description: Create SD-Card/eMMC image with a boot partition # long-description: -# Create an image that can be written onto a SD card using dd for use -# with LX2160A SoC family. +# Create an image that can be written onto an SD card or eMMC using dd +# for use with LX2160A SoC family. # It uses atf, u-boot, mc-utils, management-complex # # The disk layout used is: @@ -12,13 +12,13 @@ # | | | | | | # 0 4kiB 1MiB 8MiB 10MiB 64MiB # -part bl2 --source rawcopy --sourceparams="file=atf/bl2_sd.pbl" --ondisk mmcblk --no-table --offset 8s +part bl2 --source rawcopy --sourceparams="file=atf/bl2_auto.pbl" --ondisk mmcblk --no-table --offset 8s part bl3 --source rawcopy --sourceparams="file=atf/fip_uboot.bin" --ondisk mmcblk --no-table --offset 2048s part ddr --source rawcopy --sourceparams="file=ddr-phy/fip_ddr.bin" --ondisk mmcblk --no-table --offset 16384s part mc-fw --source rawcopy --sourceparams="file=mc_app/mc.itb" --ondisk mmcblk --no-table --offset 20480s part mc-dpl --source rawcopy --sourceparams="file=mc-utils/clearfog-cx-s1_8-s2_0-dpl.dtb" --ondisk mmcblk --no-table --offset 26624s part mc-dpc --source rawcopy --sourceparams="file=mc-utils/clearfog-cx-s1_8-s2_0-dpc.dtb" --ondisk mmcblk --no-table --offset 28672s -part /boot --source bootimg-partition --sourceparams="loader=u-boot" --ondisk mmcblk --fstype=vfat --label boot --active --offset 131072s --size 64 +part /boot --source bootimg-partition --sourceparams="loader=u-boot" --ondisk mmcblk --fstype=vfat --label boot --active --use-uuid --offset 131072s --size 64 part / --source rootfs --ondisk mmcblk --fstype=ext4 --label rootfs --use-uuid --align 4096 bootloader --ptable msdos diff --git a/wic/lx2160a-bootimg-xspi.wks.in b/wic/lx2160a-bootimg-xspi.wks.in new file mode 100644 index 0000000..b27c5ad --- /dev/null +++ b/wic/lx2160a-bootimg-xspi.wks.in @@ -0,0 +1,22 @@ +# short-description: Create SD-Card/eMMC image with a boot partition +# long-description: +# Create an image that can be written onto an SD card or eMMC using dd +# for use with LX2160A SoC family. +# It uses atf, u-boot, mc-utils, management-complex +# +# The disk layout used is: +# - ------------- -------- ----- -------------------- +# | RCW+PBI+BL2 | u-boot | ddr | management-complex | +# --------------- -------- ----- -------------------- +# ^ ^ ^ ^ ^ +# | | | | | +# 0 1MiB 8MiB 10MiB 64MiB +# +part bl2 --source rawcopy --sourceparams="file=atf/bl2_auto.pbl" --ondisk mmcblk --no-table --offset 0s +part bl3 --source rawcopy --sourceparams="file=atf/fip_uboot.bin" --ondisk mmcblk --no-table --offset 2048s +part ddr --source rawcopy --sourceparams="file=ddr-phy/fip_ddr.bin" --ondisk mmcblk --no-table --offset 16384s +part mc-fw --source rawcopy --sourceparams="file=mc_app/mc.itb" --ondisk mmcblk --no-table --offset 20480s +part mc-dpl --source rawcopy --sourceparams="file=mc-utils/clearfog-cx-s1_8-s2_0-dpl.dtb" --ondisk mmcblk --no-table --offset 26624s +part mc-dpc --source rawcopy --sourceparams="file=mc-utils/clearfog-cx-s1_8-s2_0-dpc.dtb" --ondisk mmcblk --no-table --offset 28672s + +bootloader --ptable none --source empty diff --git a/wic/lx2160a-rootimg.wks.in b/wic/lx2160a-rootimg.wks.in new file mode 100644 index 0000000..4b5f171 --- /dev/null +++ b/wic/lx2160a-rootimg.wks.in @@ -0,0 +1,17 @@ +# short-description: Create generic disk image with a boot partition +# long-description: +# Create a generic image that can be written onto any block storage using dd +# for use with LX2160A SoC family, providing only kernel + rootfs. +# +# The disk layout used is: +# ------ -------- +# | boot | rootfs | +# ------ -------- +# ^ +# | +# 4MiB +# +part /boot --source bootimg-partition --sourceparams="loader=u-boot" --ondisk sda --fstype=vfat --label boot --use-uuid --active --offset 8192s --size 64 +part / --source rootfs --ondisk sda --fstype=ext4 --label rootfs --use-uuid --align 4096 + +bootloader --ptable msdos