From a52a71e62185597d836c49a99a6f137a072601de Mon Sep 17 00:00:00 2001 From: nomakewan Date: Tue, 24 Oct 2023 12:27:50 -0700 Subject: [PATCH 1/2] Formatting fix Fixes formatting on latest commits to pass checks. --- megaavr/bootloaders/optiboot_dx/README.md | 2 +- megaavr/bootloaders/optiboot_dx/optiboot_dx.c | 28 +++++++++---------- 2 files changed, 15 insertions(+), 15 deletions(-) diff --git a/megaavr/bootloaders/optiboot_dx/README.md b/megaavr/bootloaders/optiboot_dx/README.md index d9d5bedf..2d7955bd 100644 --- a/megaavr/bootloaders/optiboot_dx/README.md +++ b/megaavr/bootloaders/optiboot_dx/README.md @@ -182,7 +182,7 @@ Since the 64k parts have no program memory locations above the first 64k, RAMPZ It is plausible that with more aggressive optimization, it might be possible to make room for EEPROM writes on 64k and smaller flash. It would take a miracle to do that on 128k parts. -### Change 10/17/23: +### Change 10/17/23 As of 10/17/2023, users building custom versions of optiboot_dx can specify baud rates lower than 62750 now even for 128k parts. This is done by, if (and only if, for readability sake) we are using the ALT serial port (costs 3 words) AND we have 128k of flash (costs 6 words) AND the baud rate is below 62750. It works by replacing the UART initialization code with a little piece of asm, and explicitly prepares a pointer for it. This saves 2 words of flash, and was the easiest way to get these configurations to build. The price is a blob of asm to do a trivial task just to save 4 bytes. ### Wastes of space diff --git a/megaavr/bootloaders/optiboot_dx/optiboot_dx.c b/megaavr/bootloaders/optiboot_dx/optiboot_dx.c index eafc8095..c12f6812 100644 --- a/megaavr/bootloaders/optiboot_dx/optiboot_dx.c +++ b/megaavr/bootloaders/optiboot_dx/optiboot_dx.c @@ -308,7 +308,7 @@ typedef union { #endif #define ASM_COPY // gives us about 18 bytes -#if defined(ASM_COPY) && defined(ASM_UART) +#if defined(ASM_COPY) && defined(ASM_UART) #define ASM_COPY_RX(__buff__, __len__) \ __asm__ __volatile__( \ "doRxCh:" "\n\t" /* */ \ @@ -450,7 +450,7 @@ static inline void read_flash(uint16_t len); #endif - + #if defined (ASM_UART) register USART_t* _usart asm ("r28"); // keep available throughout whole program #endif @@ -463,17 +463,17 @@ register addr16_t address asm("r14"); // set by avrdude, reg has to be mov'd an /* main program starts here */ int main (void) { uint8_t ch; - + // This is the first code to run. // // Optiboot C code makes the following assumptions: // No interrupts will execute // SP points to RAMEND __asm__ __volatile__ ("clr __zero_reg__"); // known-zero required by avr-libc - + // init global register variable buff.word = RAMSTART; - + // Here is the reset cause logic: // We always clear the reset cause immediately before jumping to the app, stashing it in GPR.GPR0. // This makes sure we can honor the reset entry conditions even if the user code doesn't touch @@ -573,7 +573,7 @@ int main (void) { #if (defined(MYUART_PMUX_VAL) && MYUART_PMUX_VAL != 0) MYPMUX_REG = MYUART_PMUX_VAL; // alternate pinout to use #endif - + #if defined (ASM_UART) #if (BAUD_SETTING_4 < 256) _usart->BAUDL = BAUD_SETTING_4; @@ -687,7 +687,7 @@ int main (void) { // Adaboot no-wait mod watchdogConfig(WDT_PERIOD_8CLK_gc); verifySpace(); - + /* Write up to 1 page of flash (or EEPROM, except that isn't supported due to space) */ } else if ((ch & 0xEF) == STK_PROG_PAGE) { // 0xEF = ~0x10 = 0x74-0x64 = STK_READ_PAGE - STK_PROG_PAGE uint16_t length; @@ -783,7 +783,7 @@ void putch (char ch) { // Clobbers r24 and r25 (return in r24) uint8_t getch (void) { - uint8_t ch; + uint8_t ch; #if defined(ASM_UART) while (1) { uint8_t status; @@ -795,7 +795,7 @@ uint8_t getch (void) { "ldd r25, Y+1" "\n\t" "sbrs r25, %[bp]" "\n\t" "wdr" "\n\t" - :: [bp] "I" (USART_FERR_bp) + :: [bp] "I" (USART_FERR_bp) : "r25"); #else while (!(MYUART.STATUS & USART_RXCIF_bm)) @@ -809,7 +809,7 @@ uint8_t getch (void) { #ifdef LED_DATA_FLASH LED_PORT.IN |= LED; #endif - + return ch; } @@ -821,7 +821,7 @@ void getNch (uint8_t count) { #else do getch(); while (--count); #endif - + verifySpace(); } @@ -928,7 +928,7 @@ void watchdogConfig (uint8_t x) { #if (defined(BIGBOOT) && BIGBOOT) || defined(TRY_USING_EEPROM) address.word += MAPPED_EEPROM_START; nvm_cmd(NVMCTRL_CMD_EEERWR_gc); - + #if defined(ASM_COPY_MEM) ASM_COPY_MEM(address.bptr, buff.bptr, len); #else @@ -969,7 +969,7 @@ void watchdogConfig (uint8_t x) { "dec r25" "\n\t" "brne head" "\n\t" "clr r1" "\n\t" - :: "z" ((uint16_t)address.word), + :: "z" ((uint16_t)address.word), [ptr] "x" ((uint16_t)buff.bptr), [len] "r" (len) : "r0", "r25"); // and declare r25 clobbered @@ -1107,4 +1107,4 @@ void app() //__asm__ __volatile__ ("jmp 0"); // similar to running off end of memory _PROTECTED_WRITE(RSTCTRL.SWRR, 1); // cause new reset - doesn't this make more sense?! } -*/ \ No newline at end of file +*/ From 9dee16b3011e5c293052fb6e6aab0b0e4216c9c3 Mon Sep 17 00:00:00 2001 From: nomakewan Date: Sat, 28 Oct 2023 19:08:43 -0700 Subject: [PATCH 2/2] Fix new errors Fixes newly-introduced typographical errors. --- megaavr/extras/AboutDxSeries.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/megaavr/extras/AboutDxSeries.md b/megaavr/extras/AboutDxSeries.md index 727ee525..14426f4d 100644 --- a/megaavr/extras/AboutDxSeries.md +++ b/megaavr/extras/AboutDxSeries.md @@ -64,7 +64,7 @@ Notes: * The UPDI pin can be used as an input or output (PF7) instead of UPDI, requiring HV programming to reprogram. After an HV override of that pin. * The OPAMPs have fixed pin mapping. All pins are always available on parts that have builtin OPAMPs. * (SPI, USART, TWI) Only pin mappings which are not missing the "primary" pins (TX and RX for USART, SCK, MOSI and MISO for SPI) are included for those peripherals. For TWI, options that are strictly inferior are not included in that count (this would include the case where only the dual mode pins are available, and those pins are the full function pins on another multiplexing option which does not provide dual mode pins. This happens to TWI0 on DD14, or where the a multiplexing option has the same full function pins as another mux option but no dual mode pins). In these cases, that mux option cannot do anything that cannot be done by another option which offers more functionality, and is not counted here. -* `*` VQFN version of the AVR64DD20 is NOT listed as an available package on the preliminary datasheet, and does not appear to be planned. I do not belive the die quite fits in the tiny VQFN package. +* `*` VQFN version of the AVR64DD20 is NOT listed as an available package on the preliminary datasheet, and does not appear to be planned. I do not believe the die quite fits in the tiny VQFN package. * `**` Only 2 independent TCD timer channels exist, but are distributed in groups of 4. Within each group, 2 pins are bound to a specific channel, while the other to can choose - though DxCore does not expose the ability to for pin C to output pwm B nor pin D to output pwm A. On DA and DB-series parts, current errata leaves only the first group of pins functional. The DD-series has 2 pins which appear in two groups (PA4 and PA5). The AVR DA-series is impacted by errata that prevent the PORTG mapping from working. * `!!` Flash endurance was initially spec'ed at 10k for all Dx-series parts. Shortly before the release of the DD-series, they issued an erratum ("it's broken, but we'll fix it some day, maybe") for the DA/DB parts, which was subsequently changed to a "datasheet clarification" ("it's broken, and we ain't gonna fix it") - presumably their investigation concluded that there was no ready solution (likely this is related to the word-write capability that these parts have). The DD-series was released with the datasheet specifying 1k rewrite cycles. If the limit in realisic conditions of use is 1k, that is low enough that it would constrain use of the devices in cases which relied frequent self-programming. What isn't clear though is whether the lower limit is only observed in adverse conditions (I am of the understanding that tempeature has an impact) or if even mild and typical conditions will see such low endurance. It obviously brings consideration of the flash endurance to the table in a lot of scenarios where it could normally be neglected. * There are large differences between the errata impacting the available hardware DA and DB parts (with DBs having less), and with the 128k flash versions having more than the smaller flash versions - they were released first. The AVR128DB also received a package of fixes almost immediately, likely due to a severe bug impacting the ADC when making single-ended measurements, and two problems with the OPAMPs in the initial silicon (A4 revision). Very few of those made it into the wild - even the parts I had that arrived before the preliminary datasheet had even been posted are A5. The DD-series has very little errata. @@ -85,7 +85,7 @@ Notes: | Total pins on package | 14 | 20 | 28 | 32 | 28 | 32 | 48 | 14 | 20 | 28 | 32 | | Avail. as TQFP | No | No | No | 7x7mm .8p | No | 7x7mm .8p | 7x7mm .5p | No | No | No |7x7mm .8p | | Avail. as VQFN | No | 3x3mm .4p | 4x4mm .4p | 5x5mm .5p | 4x4mm .4p | 5x5mm .5p | 6x6mm .4p | No | ?? | 4x4mmm .4|5x5mm .5p | -| Avail. as SSOP (5.3mm wide) | Yes | Yes | Yes | No | Yes | No | No | ?? | ?? | ?? | ?? | +| Avail. as SSOP (5.3mm wide) | Yes | Yes | Yes | No | Yes | No | No | ?? | ?? | ?? | ?? | | Avail. as SOP (N = Narrow) | Yes, N | No! | No | No | Yes, Wide | No | No | ?? | ?? | ?? | ?? | | Avail. as DIP (Narrow DIP28) | No | No | Yes | No | Yes | No | No | No | No | ?? | No | | I/O Pins (not reset/UPDI) | 10 | 16 | 22 | 26 | 22 | 26 | 40 | 7 | 13 | 21 | 23 |