diff --git a/bsp/digilent/NexysA7SmpLinux/include/soc.h b/bsp/digilent/NexysA7SmpLinux/include/soc.h
index 3ea9bf22f..651757449 100644
--- a/bsp/digilent/NexysA7SmpLinux/include/soc.h
+++ b/bsp/digilent/NexysA7SmpLinux/include/soc.h
@@ -32,10 +32,10 @@
 #define SYSTEM_PLIC_SYSTEM_MAC_INTERRUPT 3
 #define SYSTEM_PLIC_SYSTEM_DMA_VGA_CHANNEL_INTERRUPT 12
 #define SYSTEM_PLIC_SYSTEM_DMA_AUDIO_OUT_CHANNEL_INTERRUPT 13
-#define SYSTEM_PLIC_SYSTEM_GPIO_A_INTERRUPTS_0 4
-#define SYSTEM_PLIC_SYSTEM_GPIO_A_INTERRUPTS_1 5
-#define SYSTEM_PLIC_SYSTEM_GPIO_A_INTERRUPTS_2 6
-#define SYSTEM_PLIC_SYSTEM_GPIO_A_INTERRUPTS_3 7
+#define SYSTEM_PLIC_SYSTEM_GPIO_A_INTERRUPTS_24 4
+#define SYSTEM_PLIC_SYSTEM_GPIO_A_INTERRUPTS_25 5
+#define SYSTEM_PLIC_SYSTEM_GPIO_A_INTERRUPTS_26 6
+#define SYSTEM_PLIC_SYSTEM_GPIO_A_INTERRUPTS_27 7
 #define SYSTEM_CORES_0_D_BUS 0x0
 #define SYSTEM_FABRIC_D_BUS_COHERENT_BMB 0x0
 #define SYSTEM_FABRIC_EXCLUSIVE_MONITOR_INPUT 0x0
diff --git a/hardware/scala/saxon/board/digilent/NexysA7SmpLinux.scala b/hardware/scala/saxon/board/digilent/NexysA7SmpLinux.scala
index 09deb10bf..79ed2275d 100644
--- a/hardware/scala/saxon/board/digilent/NexysA7SmpLinux.scala
+++ b/hardware/scala/saxon/board/digilent/NexysA7SmpLinux.scala
@@ -25,6 +25,7 @@ import spinal.lib.memory.sdram.xdr.phy.XilinxS7Phy
 import spinal.lib.misc.analog.{BmbBsbToDeltaSigmaGenerator, BsbToDeltaSigmaParameter}
 import spinal.lib.system.dma.sg.{DmaMemoryLayout, DmaSgGenerator}
 import vexriscv.demo.smp.VexRiscvSmpClusterGen
+import vexriscv.plugin.AesPlugin
 
 
 class NexysA7SmpLinuxAbtract(cpuCount : Int) extends VexRiscvClusterGenerator(cpuCount){
@@ -97,7 +98,7 @@ class NexysA7SmpLinuxAbtract(cpuCount : Int) extends VexRiscvClusterGenerator(cp
   )
 }
 
-class NexysA7SmpLinux extends Generator{
+class NexysA7SmpLinux(cpuCount : Int) extends Generator{
   val debugCd = ClockDomainResetGenerator()
   debugCd.holdDuration.load(4095)
   debugCd.enablePowerOnReset()
@@ -119,7 +120,7 @@ class NexysA7SmpLinux extends Generator{
     omitReset = true
   )
 
-  val system = new NexysA7SmpLinuxAbtract(2){
+  val system = new NexysA7SmpLinuxAbtract(cpuCount){
     val vgaPhy = vga.withRegisterPhy(withColorEn = false)
   }
   system.onClockDomain(systemCd.outputClockDomain)
@@ -223,8 +224,7 @@ class NexysA7SmpLinux extends Generator{
   }
 
   val audioOut = add task new Area{
-    val sd = out Bool()
-    sd := Bool(true)
+    val sd = out(True)
   }
 
   val startupe2 = system.spiA.flash.produce(
@@ -245,6 +245,7 @@ object NexysA7SmpLinuxAbstract{
         iBusWidth = 64,
         dBusWidth = 64
       ))
+      cpu.config.plugins += AesPlugin()
     }
 
     ramA.size.load(8 KiB)
@@ -268,8 +269,8 @@ object NexysA7SmpLinuxAbstract{
     )
 
     gpioA.parameter load Gpio.Parameter(
-      width = 16,
-      interrupt = List(0, 1, 2, 3)
+      width = 32,
+      interrupt = List(24, 25, 26, 27)
     )
     gpioA.connectInterrupts(plic, 4)
 
@@ -347,10 +348,10 @@ object NexysA7SmpLinux {
   def main(args: Array[String]): Unit = {
     val report = SpinalRtlConfig
       .copy(
-        defaultConfigForClockDomains = ClockDomainConfig(resetKind = spinal.core.SYNC),
+        defaultConfigForClockDomains = ClockDomainConfig(resetKind = SYNC),
         inlineRom = true
       ).addStandardMemBlackboxing(blackboxByteEnables)
-       .generateVerilog(InOutWrapper(default(new NexysA7SmpLinux()).toComponent()))
+       .generateVerilog(InOutWrapper(default(new NexysA7SmpLinux(2)).toComponent()))
     BspGenerator("digilent/NexysA7SmpLinux", report.toplevel.generator, report.toplevel.generator.system.cores(0).dBus)
   }
 }
@@ -372,7 +373,7 @@ object NexysA7SmpLinuxSystemSim {
 //    simConfig.withConfig(SpinalConfig(anonymSignalPrefix = "zz_"))
     simConfig.addSimulatorFlag("-Wno-MULTIDRIVEN")
 
-    simConfig.compile(new NexysA7SmpLinuxAbtract(2){
+    simConfig.compile(new NexysA7SmpLinuxAbtract(cpuCount = 2){
       val debugCd = ClockDomainResetGenerator()
       debugCd.enablePowerOnReset()
       debugCd.holdDuration.load(63)
diff --git a/hardware/synthesis/digilent/NexysA7SmpLinux/NexysA7.xdc b/hardware/synthesis/digilent/NexysA7SmpLinux/NexysA7.xdc
index a33363f7e..bbec1e710 100644
--- a/hardware/synthesis/digilent/NexysA7SmpLinux/NexysA7.xdc
+++ b/hardware/synthesis/digilent/NexysA7SmpLinux/NexysA7.xdc
@@ -11,22 +11,22 @@ create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports { c
 
 ##Switches
 
-#set_property -dict { PACKAGE_PIN J15   IOSTANDARD LVCMOS33 } [get_ports { SW[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0]
-#set_property -dict { PACKAGE_PIN L16   IOSTANDARD LVCMOS33 } [get_ports { SW[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1]
-#set_property -dict { PACKAGE_PIN M13   IOSTANDARD LVCMOS33 } [get_ports { SW[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2]
-#set_property -dict { PACKAGE_PIN R15   IOSTANDARD LVCMOS33 } [get_ports { SW[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3]
-#set_property -dict { PACKAGE_PIN R17   IOSTANDARD LVCMOS33 } [get_ports { SW[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4]
-#set_property -dict { PACKAGE_PIN T18   IOSTANDARD LVCMOS33 } [get_ports { SW[5] }]; #IO_L7N_T1_D10_14 Sch=sw[5]
-#set_property -dict { PACKAGE_PIN U18   IOSTANDARD LVCMOS33 } [get_ports { SW[6] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6]
-#set_property -dict { PACKAGE_PIN R13   IOSTANDARD LVCMOS33 } [get_ports { SW[7] }]; #IO_L5N_T0_D07_14 Sch=sw[7]
-#set_property -dict { PACKAGE_PIN T8    IOSTANDARD LVCMOS18 } [get_ports { SW[8] }]; #IO_L24N_T3_34 Sch=sw[8]
-#set_property -dict { PACKAGE_PIN U8    IOSTANDARD LVCMOS18 } [get_ports { SW[9] }]; #IO_25_34 Sch=sw[9]
-#set_property -dict { PACKAGE_PIN R16   IOSTANDARD LVCMOS33 } [get_ports { SW[10] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10]
-#set_property -dict { PACKAGE_PIN T13   IOSTANDARD LVCMOS33 } [get_ports { SW[11] }]; #IO_L23P_T3_A03_D19_14 Sch=sw[11]
-#set_property -dict { PACKAGE_PIN H6    IOSTANDARD LVCMOS33 } [get_ports { SW[12] }]; #IO_L24P_T3_35 Sch=sw[12]
-#set_property -dict { PACKAGE_PIN U12   IOSTANDARD LVCMOS33 } [get_ports { SW[13] }]; #IO_L20P_T3_A08_D24_14 Sch=sw[13]
-#set_property -dict { PACKAGE_PIN U11   IOSTANDARD LVCMOS33 } [get_ports { SW[14] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14]
-#set_property -dict { PACKAGE_PIN V10   IOSTANDARD LVCMOS33 } [get_ports { SW[15] }]; #IO_L21P_T3_DQS_14 Sch=sw[15]
+set_property -dict { PACKAGE_PIN J15   IOSTANDARD LVCMOS33 } [get_ports { system_gpioA_gpio[16] }]; #IO_L24N_T3_RS0_15 Sch=sw[0]
+set_property -dict { PACKAGE_PIN L16   IOSTANDARD LVCMOS33 } [get_ports { system_gpioA_gpio[17] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1]
+set_property -dict { PACKAGE_PIN M13   IOSTANDARD LVCMOS33 } [get_ports { system_gpioA_gpio[18] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2]
+set_property -dict { PACKAGE_PIN R15   IOSTANDARD LVCMOS33 } [get_ports { system_gpioA_gpio[19] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3]
+set_property -dict { PACKAGE_PIN R17   IOSTANDARD LVCMOS33 } [get_ports { system_gpioA_gpio[20] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4]
+set_property -dict { PACKAGE_PIN T18   IOSTANDARD LVCMOS33 } [get_ports { system_gpioA_gpio[21] }]; #IO_L7N_T1_D10_14 Sch=sw[5]
+set_property -dict { PACKAGE_PIN U18   IOSTANDARD LVCMOS33 } [get_ports { system_gpioA_gpio[22] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6]
+set_property -dict { PACKAGE_PIN R13   IOSTANDARD LVCMOS33 } [get_ports { system_gpioA_gpio[23] }]; #IO_L5N_T0_D07_14 Sch=sw[7]
+set_property -dict { PACKAGE_PIN T8    IOSTANDARD LVCMOS18 } [get_ports { system_gpioA_gpio[24] }]; #IO_L24N_T3_34 Sch=sw[8]
+set_property -dict { PACKAGE_PIN U8    IOSTANDARD LVCMOS18 } [get_ports { system_gpioA_gpio[25] }]; #IO_25_34 Sch=sw[9]
+set_property -dict { PACKAGE_PIN R16   IOSTANDARD LVCMOS33 } [get_ports { system_gpioA_gpio[26] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10]
+set_property -dict { PACKAGE_PIN T13   IOSTANDARD LVCMOS33 } [get_ports { system_gpioA_gpio[27] }]; #IO_L23P_T3_A03_D19_14 Sch=sw[11]
+set_property -dict { PACKAGE_PIN H6    IOSTANDARD LVCMOS33 } [get_ports { system_gpioA_gpio[28] }]; #IO_L24P_T3_35 Sch=sw[12]
+set_property -dict { PACKAGE_PIN U12   IOSTANDARD LVCMOS33 } [get_ports { system_gpioA_gpio[29] }]; #IO_L20P_T3_A08_D24_14 Sch=sw[13]
+set_property -dict { PACKAGE_PIN U11   IOSTANDARD LVCMOS33 } [get_ports { system_gpioA_gpio[30] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14]
+set_property -dict { PACKAGE_PIN V10   IOSTANDARD LVCMOS33 } [get_ports { system_gpioA_gpio[31] }]; #IO_L21P_T3_DQS_14 Sch=sw[15]
 
 
 ## LEDs
diff --git a/hardware/synthesis/digilent/NexysA7SmpLinux/README.md b/hardware/synthesis/digilent/NexysA7SmpLinux/README.md
index 241bb9f6e..0a4f1f881 100644
--- a/hardware/synthesis/digilent/NexysA7SmpLinux/README.md
+++ b/hardware/synthesis/digilent/NexysA7SmpLinux/README.md
@@ -671,6 +671,20 @@ ping 10.0.0.1
 };
 ```
 
+### Audio
+
+```sh
+tftp -g -r sample3.mp3 10.0.0.1
+mpg123 -m sample3.mp3 
+```
+
+### Video
+
+```sh
+tftp -g -r sample.mp4 10.0.0.1
+ffmpeg -i sample.mp4 -pix_fmt rgb565le -f fbdev /dev/fb0
+```
+
 ## Simulation
 
 ### Ethernet