From 4d3cd06419b6c1623c344ca9b76df78d9a17d647 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Tue, 9 Jul 2024 13:24:35 +0200 Subject: [PATCH] #20 add support for more than 32 bits physical address via for instance : --region base=80000000,size=380000000,main=1,exe=1 --region base=10000000,size=10000000,main=0,exe=0 --physical-width=34 --- src/main/scala/vexiiriscv/Generate.scala | 6 +- src/main/scala/vexiiriscv/Param.scala | 64 ++++++++++++------- .../scala/vexiiriscv/tester/TestBench.scala | 21 ++++-- 3 files changed, 61 insertions(+), 30 deletions(-) diff --git a/src/main/scala/vexiiriscv/Generate.scala b/src/main/scala/vexiiriscv/Generate.scala index 41f506fe..b209162a 100644 --- a/src/main/scala/vexiiriscv/Generate.scala +++ b/src/main/scala/vexiiriscv/Generate.scala @@ -19,15 +19,19 @@ import scala.collection.mutable.ArrayBuffer object Generate extends App { val param = new ParamSimple() val sc = SpinalConfig() + val regions = ArrayBuffer[PmaRegion]() assert(new scopt.OptionParser[Unit]("VexiiRiscv") { help("help").text("prints this usage text") param.addOptions(this) + ParamSimple.addptionRegion(this, regions) }.parse(args, Unit).nonEmpty) + if(regions.isEmpty) regions ++= ParamSimple.defaultPma + val report = sc.generateVerilog { val plugins = param.plugins() - ParamSimple.setPma(plugins) + ParamSimple.setPma(plugins, regions) VexiiRiscv(plugins) } } diff --git a/src/main/scala/vexiiriscv/Param.scala b/src/main/scala/vexiiriscv/Param.scala index 45bf8bea..631257cc 100644 --- a/src/main/scala/vexiiriscv/Param.scala +++ b/src/main/scala/vexiiriscv/Param.scala @@ -22,33 +22,48 @@ import vexiiriscv.test.WhiteboxerPlugin import scala.collection.mutable.ArrayBuffer object ParamSimple{ - def setPma(plugins : Seq[Hostable]) = { - val regions = ArrayBuffer[PmaRegion]( - new PmaRegionImpl( - mapping = SizeMapping(0x80000000l, 0x80000000l), - isMain = true, - isExecutable = true, - transfers = M2sTransfers( - get = SizeRange.all, - putFull = SizeRange.all - ) - ), - new PmaRegionImpl( - mapping = SizeMapping(0x10000000l, 0x10000000l), - isMain = false, - isExecutable = true, - transfers = M2sTransfers( - get = SizeRange.all, - putFull = SizeRange.all - ) + + def addptionRegion(parser: scopt.OptionParser[Unit], regions : ArrayBuffer[PmaRegion]): Unit = { + import parser._ + opt[Map[String, String]]("region") unbounded() action { (v, c) => + regions += PmaRegionImpl( + mapping = SizeMapping(BigInt(v("base"), 16), BigInt(v("size"), 16)), + transfers = M2sTransfers.all, + isMain = v("main") == "1", + isExecutable = v("exe") == "1" + ) + } text ("Specify a memory region, for instance : --region base=80000000,size=80000000,main=1,exe=1 --region base=10000000,size=10000000,main=0,exe=0") + } + + val defaultPma = List[PmaRegion]( + new PmaRegionImpl( + mapping = SizeMapping(0x80000000l, 0x80000000l), + isMain = true, + isExecutable = true, + transfers = M2sTransfers( + get = SizeRange.all, + putFull = SizeRange.all + ) + ), + new PmaRegionImpl( + mapping = SizeMapping(0x10000000l, 0x10000000l), + isMain = false, + isExecutable = true, + transfers = M2sTransfers( + get = SizeRange.all, + putFull = SizeRange.all ) ) + ) + + def setPma(plugins : Seq[Hostable], regions : Seq[PmaRegion] = defaultPma) = { + val array = ArrayBuffer(regions :_*) plugins.foreach { - case p: FetchCachelessPlugin => p.regions.load(regions) - case p: LsuCachelessPlugin => p.regions.load(regions) - case p: FetchL1Plugin => p.regions.load(regions) - case p: LsuPlugin => p.ioRegions.load(regions) - case p: LsuL1Plugin => p.regions.load(regions) + case p: FetchCachelessPlugin => p.regions.load(array) + case p: LsuCachelessPlugin => p.regions.load(array) + case p: FetchL1Plugin => p.regions.load(array) + case p: LsuPlugin => p.ioRegions.load(array) + case p: LsuL1Plugin => p.regions.load(array) case _ => } plugins @@ -179,6 +194,7 @@ class ParamSimple(){ privParam.withSupervisor = true privParam.withUser = true xlen = 64 + physicalWidth = 38 privParam.withDebug = true diff --git a/src/main/scala/vexiiriscv/tester/TestBench.scala b/src/main/scala/vexiiriscv/tester/TestBench.scala index a3e263ff..3afc7a93 100644 --- a/src/main/scala/vexiiriscv/tester/TestBench.scala +++ b/src/main/scala/vexiiriscv/tester/TestBench.scala @@ -235,11 +235,23 @@ class TestOptions{ probe.backends ++= r } - probe.backends.foreach { b => - b.addRegion(0, 0, 0x20000000l, 0xE0000000l) // mem - b.addRegion(0, 1, 0x10000000l, 0x10000000l) // io + val regions = dut.host.services.collectFirst { + case p: LsuCachelessPlugin => p.regions.get + case p: LsuL1Plugin => p.regions.get + }.get + + for(region <- regions){ + probe.backends.foreach { b => + val mapping = region.mapping match { + case sm : SizeMapping => sm + } + if(mapping.base != 0x1000) { + b.addRegion(0, region.isMain.mux(0, 1), mapping.base.toLong, mapping.size.toLong) + } + } } + val mem = SparseMemory(seed = 0) // Load the binaries for ((offset, file) <- bins) { @@ -565,7 +577,7 @@ object TestBench extends App{ } val regions = ArrayBuffer( new PmaRegion{ - override def mapping: AddressMapping = SizeMapping(0x80000000l, 0x80000000l) + override def mapping: AddressMapping = SizeMapping(0x80000000l, (1l << param.physicalWidth) - 0x80000000l) override def transfers: MemoryTransfers = M2sTransfers( get = SizeRange.all, putFull = SizeRange.all @@ -591,7 +603,6 @@ object TestBench extends App{ override def isMain: Boolean = true override def isExecutable: Boolean = true } - ) ret.foreach{ case p: FetchCachelessPlugin => p.regions.load(regions)