From 9ee8e355d640c794b06345d261ee15afa789864d Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Mon, 8 Jan 2024 16:57:50 +0100 Subject: [PATCH] cleaning --- .../scala/vexiiriscv/decode/DecoderPlugin.scala | 2 +- src/main/scala/vexiiriscv/memory/MmuPLugin.scala | 6 +++--- .../scala/vexiiriscv/misc/PrivilegedPlugin.scala | 14 ++++++++------ src/main/scala/vexiiriscv/misc/TrapPlugin.scala | 2 +- .../scala/vexiiriscv/test/WhiteboxerPlugin.scala | 2 +- src/main/scala/vexiiriscv/tester/TestBench.scala | 2 +- 6 files changed, 15 insertions(+), 13 deletions(-) diff --git a/src/main/scala/vexiiriscv/decode/DecoderPlugin.scala b/src/main/scala/vexiiriscv/decode/DecoderPlugin.scala index 487c949f..1cba44dd 100644 --- a/src/main/scala/vexiiriscv/decode/DecoderPlugin.scala +++ b/src/main/scala/vexiiriscv/decode/DecoderPlugin.scala @@ -117,7 +117,7 @@ class DecoderPlugin(var decodeAt : Int) extends FiberPlugin with DecoderService } val interrupt = new Area { - val async = B(host[PrivilegedPlugin].miaou.csrs.map(_.int.pending)) + val async = B(host[PrivilegedPlugin].logic.harts.map(_.int.pending)) //We need to buffer interrupts request to ensure we don't generate sporadic flushes while the ctrl is stuck val buffered = RegNextWhen(async, !decodeCtrl.link.up.valid || decodeCtrl.link.up.ready || decodeCtrl.link.up.isCanceling) init(0) } diff --git a/src/main/scala/vexiiriscv/memory/MmuPLugin.scala b/src/main/scala/vexiiriscv/memory/MmuPLugin.scala index dc764efe..c3df3ac9 100644 --- a/src/main/scala/vexiiriscv/memory/MmuPLugin.scala +++ b/src/main/scala/vexiiriscv/memory/MmuPLugin.scala @@ -5,7 +5,7 @@ //import spinal.lib._ //import spinal.lib.fsm._ //import spinal.lib.misc.plugin.FiberPlugin -//import spinal.lib.pipeline.{Payload, Stage} +//import spinal.lib.misc.pipeline._ //import vexiiriscv._ //import Global._ //import spinal.lib.misc.pipeline.{NodeBaseApi, Payload} @@ -104,7 +104,7 @@ // storageSpecs.addRet(StorageSpec(p)) // } // -// override def newTranslationPort(stages: Seq[Stage], +// override def newTranslationPort(stages: Seq[NodeBaseApi], // preAddress: Payload[UInt], // allowRefill : Payload[Bool], // usage : AddressTranslationPortUsage, @@ -180,7 +180,7 @@ // val status = new Area{ // val mxr = RegInit(False) // val sum = RegInit(False) -// val mprv = RegInit(False) clearWhen(priv.io.harts(0).xretAwayFromMachine) +// val mprv = RegInit(False) clearWhen(priv.hart(0).xretAwayFromMachine) // } // // for(offset <- List(CSR.MSTATUS, CSR.SSTATUS)) csr.readWrite(offset, 19 -> status.mxr, 18 -> status.sum) diff --git a/src/main/scala/vexiiriscv/misc/PrivilegedPlugin.scala b/src/main/scala/vexiiriscv/misc/PrivilegedPlugin.scala index 770c19e6..568662ce 100644 --- a/src/main/scala/vexiiriscv/misc/PrivilegedPlugin.scala +++ b/src/main/scala/vexiiriscv/misc/PrivilegedPlugin.scala @@ -50,13 +50,13 @@ class PrivilegedPlugin(val p : PrivilegedParam, hartIds : Seq[Int]) extends Fibe def implementUser = p.withUser def implementUserTrap = p.withUserTrap - def getPrivilege(hartId : UInt) : UInt = miaou.csrs.map(_.privilege).read(hartId) + def getPrivilege(hartId : UInt) : UInt = logic.harts.map(_.privilege).read(hartId) case class Delegator(var enable: Bool, privilege: Int) case class InterruptSpec(var cond: Bool, id: Int, privilege: Int, delegators: List[Delegator]) case class ExceptionSpec(id: Int, delegators: List[Delegator]) - override def getCommitMask(hartId: Int): Bits = miaou.csrs(hartId).commitMask - override def hasInflight(hartId: Int): Bool = miaou.csrs(hartId).hasInflight + override def getCommitMask(hartId: Int): Bits = logic.harts(hartId).commitMask + override def hasInflight(hartId: Int): Bool = logic.harts(hartId).hasInflight val misaIds = mutable.LinkedHashSet[Int]() def addMisa(id: Char): Unit = addMisa(id - 'A') @@ -64,7 +64,9 @@ class PrivilegedPlugin(val p : PrivilegedParam, hartIds : Seq[Int]) extends Fibe misaIds += id } - val miaou = during setup new Area { + def hart(id : Int) = logic.harts(id) + + val logic = during setup new Area { val cap = host[CsrAccessPlugin] val pp = host[PipelineBuilderPlugin] val pcs = host[PcService] @@ -88,7 +90,7 @@ class PrivilegedPlugin(val p : PrivilegedParam, hartIds : Seq[Int]) extends Fibe assert(HART_COUNT.get == 1) val rdtime = in UInt (64 bits) - val csrs = for (hartId <- 0 until HART_COUNT) yield new Area { + val harts = for (hartId <- 0 until HART_COUNT) yield new Area { val xretAwayFromMachine = False val commitMask = Bits(host.list[ExecuteLanePlugin].size bits) val hasInflight = Bool() @@ -271,7 +273,7 @@ class PrivilegedPlugin(val p : PrivilegedParam, hartIds : Seq[Int]) extends Fibe val defaultTrap = new Area { val csrPrivilege = cap.onDecodeAddress(8, 2 bits) val csrReadOnly = cap.onDecodeAddress(10, 2 bits) === U"11" - when(csrReadOnly && cap.onDecodeWrite || csrPrivilege > csrs.reader(cap.onDecodeHartId)(_.privilege)) { + when(csrReadOnly && cap.onDecodeWrite || csrPrivilege > harts.reader(cap.onDecodeHartId)(_.privilege)) { cap.onDecodeTrap() } } diff --git a/src/main/scala/vexiiriscv/misc/TrapPlugin.scala b/src/main/scala/vexiiriscv/misc/TrapPlugin.scala index ede5b6c2..ec1aca88 100644 --- a/src/main/scala/vexiiriscv/misc/TrapPlugin.scala +++ b/src/main/scala/vexiiriscv/misc/TrapPlugin.scala @@ -89,7 +89,7 @@ class TrapPlugin(trapAt : Int) extends FiberPlugin with TrapService { trapLock.await() val harts = for(hartId <- 0 until HART_COUNT) yield new Area{ - val csr = priv.miaou.csrs(hartId) + val csr = priv.logic.harts(hartId) val crsPorts = withRam generate new Area{ val read = crs.ramReadPort(CsrRamService.priority.TRAP) diff --git a/src/main/scala/vexiiriscv/test/WhiteboxerPlugin.scala b/src/main/scala/vexiiriscv/test/WhiteboxerPlugin.scala index e709dd72..2ae399c5 100644 --- a/src/main/scala/vexiiriscv/test/WhiteboxerPlugin.scala +++ b/src/main/scala/vexiiriscv/test/WhiteboxerPlugin.scala @@ -240,7 +240,7 @@ class WhiteboxerPlugin extends FiberPlugin{ class InterruptsProxy { val priv = host[PrivilegedPlugin] val checkers = ArrayBuffer[InterruptChecker]() - for ((hart, hartId) <- priv.miaou.csrs.zipWithIndex) { + for ((hart, hartId) <- priv.logic.harts.zipWithIndex) { checkers += new InterruptChecker(hartId, hart.int.m.timer, 7) checkers += new InterruptChecker(hartId, hart.int.m.software, 3) checkers += new InterruptChecker(hartId, hart.int.m.external, 11) diff --git a/src/main/scala/vexiiriscv/tester/TestBench.scala b/src/main/scala/vexiiriscv/tester/TestBench.scala index 4ecb9dc6..6a974c30 100644 --- a/src/main/scala/vexiiriscv/tester/TestBench.scala +++ b/src/main/scala/vexiiriscv/tester/TestBench.scala @@ -169,7 +169,7 @@ class TestOptions{ } } - val priv = dut.host[PrivilegedPlugin].miaou.csrs(0) + val priv = dut.host[PrivilegedPlugin].logic.harts(0) val peripheral = new PeripheralEmulator(0x10000000, priv.int.m.external, (priv.int.s != null) generate priv.int.s.external, mti = priv.int.m.timer, cd = cd){ override def getClintTime(): Long = probe.cycle }