From efc15ccc8dabdf219fd73f660e41d9e59863f7a0 Mon Sep 17 00:00:00 2001
From: Dolu1990 <charles.papon.90@gmail.com>
Date: Tue, 9 Jan 2024 17:38:24 +0100
Subject: [PATCH] Add page fault to lsuCacheless

---
 .../vexiiriscv/execute/LsuCachelessPlugin.scala  | 16 +++++++++++++++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/src/main/scala/vexiiriscv/execute/LsuCachelessPlugin.scala b/src/main/scala/vexiiriscv/execute/LsuCachelessPlugin.scala
index 077f7ab1..665f300a 100644
--- a/src/main/scala/vexiiriscv/execute/LsuCachelessPlugin.scala
+++ b/src/main/scala/vexiiriscv/execute/LsuCachelessPlugin.scala
@@ -181,8 +181,22 @@ class LsuCachelessPlugin(var layer : LaneLayer,
         trapPort.code := TrapReason.JUMP
         trapPort.tval(0, INSTRUCTION_SLICE_COUNT_WIDTH + 1 bits) := 0
       }
+      
+      when(tpk.PAGE_FAULT || LOAD.mux(!tpk.ALLOW_READ, !tpk.ALLOW_WRITE)) {
+        skip := True
+        trapPort.exception := True
+        trapPort.code := CSR.MCAUSE_ENUM.LOAD_PAGE_FAULT
+        trapPort.code(1) setWhen(!LOAD)
+      }
+
+      when(tpk.ACCESS_FAULT) {
+        skip := True
+        trapPort.exception := True
+        trapPort.code := CSR.MCAUSE_ENUM.LOAD_ACCESS_FAULT
+        trapPort.code(1) setWhen (!LOAD)
+      }
 
-      when(tpk.REDO){
+      when(tpk.REDO) {
         skip := True
         trapPort.exception := False
         trapPort.code := TrapReason.WAIT_MMU