From adce26f165c3bc6fa8dd59200fadb017d177af89 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Wed, 9 Jun 2021 18:30:58 +0200 Subject: [PATCH 01/39] Prepare for next version v0.8.2. --- doc/conf.py | 2 +- setup.py | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/doc/conf.py b/doc/conf.py index 6020ce0ea..9ebd25b8c 100644 --- a/doc/conf.py +++ b/doc/conf.py @@ -37,7 +37,7 @@ def _LatestTagName(): # The full version, including alpha/beta/rc tags version = "0.8" # The short X.Y version. -release = "0.8.1" # The full version, including alpha/beta/rc tags. +release = "0.8.2" # The full version, including alpha/beta/rc tags. try: if _IsUnderGitControl: latestTagName = _LatestTagName()[1:] # remove prefix "v" diff --git a/setup.py b/setup.py index fde77839c..0ad30917a 100644 --- a/setup.py +++ b/setup.py @@ -53,7 +53,7 @@ # Assemble all package information setuptools_setup( name=projectName, - version="0.8.1", + version="0.8.2", author="Patrick Lehmann", author_email="Paebbels@gmail.com", From 544cf9764ba2d35602af3d81cb64b73db461ab01 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Thu, 10 Jun 2021 14:00:29 +0200 Subject: [PATCH 02/39] New combined workflow. --- .github/workflows/Documentation.yml | 27 --- .github/workflows/Pipeline.yml | 262 ++++++++++++++++++++++++++++ .github/workflows/Release.yml | 43 ----- .github/workflows/Test.yml | 95 ---------- pyVHDLModel/VHDLModel.py | 2 +- 5 files changed, 263 insertions(+), 166 deletions(-) delete mode 100644 .github/workflows/Documentation.yml create mode 100644 .github/workflows/Pipeline.yml delete mode 100644 .github/workflows/Release.yml delete mode 100644 .github/workflows/Test.yml diff --git a/.github/workflows/Documentation.yml b/.github/workflows/Documentation.yml deleted file mode 100644 index 8f28dde6a..000000000 --- a/.github/workflows/Documentation.yml +++ /dev/null @@ -1,27 +0,0 @@ -name: Documentation - -on: [ push ] - -jobs: - BuildTheDocs: - name: Run BuildTheDocs and publish to GH-Pages - runs-on: ubuntu-latest - steps: - - - uses: actions/checkout@v2 - - - name: Build pyVHDLModel/doc - run: | - docker build -t vhdl/doc - <<-EOF - FROM btdi/sphinx:featured - RUN apk add -U --no-cache graphviz - EOF - - - uses: buildthedocs/btd@v0 - with: - token: ${{ github.token }} - - - uses: actions/upload-artifact@master - with: - name: doc - path: doc/_build/html diff --git a/.github/workflows/Pipeline.yml b/.github/workflows/Pipeline.yml new file mode 100644 index 000000000..e9c06046d --- /dev/null +++ b/.github/workflows/Pipeline.yml @@ -0,0 +1,262 @@ +name: Unit Testing, Coverage Collection, Package, Release, Documentation and Publish + +on: [ push ] + +jobs: + UnitTesting: + name: Unit Tests + runs-on: ubuntu-latest + strategy: + fail-fast: false + matrix: + python-version: [ 3.6, 3.7, 3.8, 3.9 ] + + env: + PYTHON: ${{ matrix.python-version }} + outputs: + python: ${{ env.PYTHON }} + + steps: + - name: Checkout repository + uses: actions/checkout@v2 + + - name: Setup Python ${{ matrix.python-version }} + uses: actions/setup-python@v2 + with: + python-version: ${{ matrix.python-version }} + + - name: Install dependencies + run: | + python -m pip install --upgrade pip + pip install -r tests/requirements.txt + + - name: Run unit tests + run: | + python -m pytest -rA tests/unit + + Coverage: + name: Collect Coverage Data + runs-on: ubuntu-latest + + env: + PYTHON: 3.9 + outputs: + python: ${{ env.PYTHON }} + + steps: + - name: Checkout repository + uses: actions/checkout@v2 + + - name: Setup Python ${{ env.PYTHON }} + uses: actions/setup-python@v2 + with: + python-version: ${{ env.PYTHON }} + + - name: Install dependencies + run: | + python -m pip install --upgrade pip + pip install -r tests/requirements.txt + + - name: Collect coverage + continue-on-error: true + run: | + python -m pytest -rA --cov=.. --cov-config=tests/.coveragerc tests/unit + + - name: Convert to cobertura format + run: | + coverage xml + + - name: Publish coverage at CodeCov + continue-on-error: true + uses: codecov/codecov-action@v1 + with: + file: ./coverage.xml + flags: unittests + env_vars: PYTHON + + - name: Publish coverage at Codacy + continue-on-error: true + uses: codacy/codacy-coverage-reporter-action@master + with: + project-token: ${{ secrets.CODACY_PROJECT_TOKEN }} + coverage-reports: ./coverage.xml + + Release: + name: Release Page on GitHub + runs-on: ubuntu-latest + + if: startsWith(github.ref, 'refs/tags') + needs: + - UnitTesting + - Coverage + + env: + PYTHON: ${{ needs.Coverage.outputs.python }} + outputs: + python: ${{ env.PYTHON }} + tag: ${{ steps.getVariables.outputs.gitTag }} + version: ${{ steps.getVariables.outputs.version }} + datetime: ${{ steps.getVariables.outputs.datetime }} + upload_url: ${{ steps.createReleasePage.outputs.upload_url }} + + steps: + - name: Extract Git tag from GITHUB_REF + id: getVariables + run: | + GIT_TAG=${GITHUB_REF#refs/*/} + RELEASE_VERSION=${GIT_TAG#v} + RELEASE_DATETIME="$(date --utc '+%d.%m.%Y - %H:%M:%S')" + # write to step outputs + echo ::set-output name=gitTag::${GIT_TAG} + echo ::set-output name=version::${RELEASE_VERSION} + echo ::set-output name=datetime::${RELEASE_DATETIME} + + - name: Create Release Page + id: createReleasePage + uses: actions/create-release@v1 + env: + GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} + with: + tag_name: ${{ steps.getVariables.outputs.gitTag }} +# release_name: ${{ steps.getVariables.outputs.gitTag }} + body: | + **Automated Release created on: ${{ steps.getVariables.outputs.datetime }}** + + # New Features + * tbd + + # Changes + * tbd + + # Bug Fixes + * tbd + draft: false + prerelease: false + + Package: + name: Package in Wheel Format + runs-on: ubuntu-latest + + if: startsWith(github.ref, 'refs/tags') + needs: + - Coverage + + env: + PYTHON: ${{ needs.Coverage.outputs.python }} + ARTIFACT: pyVHDLModel-wheel + outputs: + python: ${{ env.PYTHON }} + artifact: ${{ env.ARTIFACT }} + + steps: + - name: Checkout repository + uses: actions/checkout@v2 + + - name: Setup Python ${{ env.PYTHON }} + uses: actions/setup-python@v2 + with: + python-version: ${{ env.PYTHON }} + + - name: Install dependencies for packaging and release + run: | + python -m pip install --upgrade pip + pip install wheel + + - name: Build Python package (source distribution) + run: | + python setup.py sdist + + - name: Build Python package (binary distribution - wheel) + run: | + python setup.py bdist_wheel + + - name: Upload 'pyVHDLModel' artifact + uses: actions/upload-artifact@v2 + with: + name: ${{ env.ARTIFACT }} + path: dist/ + if-no-files-found: error + retention-days: 1 + + PublishOnPyPI: + name: Publish to PyPI + runs-on: ubuntu-latest + + if: startsWith(github.ref, 'refs/tags') + needs: + - Package + + env: + PYTHON: ${{ needs.Package.outputs.python }} + ARTIFACT: ${{ needs.Package.outputs.artifact }} + outputs: + python: ${{ env.PYTHON }} + artifact: ${{ env.ARTIFACT }} + + steps: + - name: Download artifacts '${{ env.ARTIFACT }}' from 'Package' job + uses: actions/download-artifact@v2 + with: + name: ${{ env.ARTIFACT }} + path: dist/ + + - name: Setup Python ${{ env.PYTHON }} + uses: actions/setup-python@v2 + with: + python-version: ${{ env.PYTHON }} + + - name: Install dependencies for packaging and release + run: | + python -m pip install --upgrade pip + pip install wheel twine + + - name: Release Python package to PyPI + env: + TWINE_USERNAME: __token__ + TWINE_PASSWORD: ${{ secrets.PYPI_TOKEN }} + run: | + twine upload dist/* + + BuildTheDocs: + name: Run BuildTheDocs and publish to GH-Pages + runs-on: ubuntu-latest + steps: + + - name: Checkout repository + uses: actions/checkout@v2 + + - name: Build documentation in 'pyVHDLModel/doc' + run: | + docker build -t vhdl/doc - <<-EOF + FROM btdi/sphinx:featured + RUN apk add -U --no-cache graphviz + EOF + + - name: Unknown + uses: buildthedocs/btd@v0 + with: + token: ${{ github.token }} + + - name: Upload artifacts to GitHub Pages + uses: actions/upload-artifact@master + with: + name: doc + path: doc/_build/html + + ArtifactCleanUp: + name: Artifact Cleanup + runs-on: ubuntu-latest + + needs: + - Package + - PublishOnPyPI + + env: + ARTIFACT: ${{ needs.Package.outputs.artifact }} + + steps: + - name: Delete all Artifacts + uses: geekyeggo/delete-artifact@v1 + with: + name: | + ${{ env.ARTIFACT }} diff --git a/.github/workflows/Release.yml b/.github/workflows/Release.yml deleted file mode 100644 index b007cf1fd..000000000 --- a/.github/workflows/Release.yml +++ /dev/null @@ -1,43 +0,0 @@ -name: Release - -on: - repository_dispatch: - types: [ doRelease ] - -jobs: - Release: - name: Package and Publish to PyPI - runs-on: ubuntu-latest - env: - PYTHON: ${{ github.event.client_payload.PYTHON }} - steps: - - name: Checkout repository - uses: actions/checkout@v2 - with: - ref: ${{ github.event.client_payload.ref }} - - - name: Setup Python ${{ env.PYTHON }} - uses: actions/setup-python@v2 - with: - python-version: ${{ env.PYTHON }} - - - name: Install dependencies for packaging and release - run: | - python -m pip install --upgrade pip - pip install wheel twine - - - name: Build Python package (source distribution) - run: | - python setup.py sdist - - - name: Build Python package (binary distribution - wheel) - run: | - python setup.py bdist_wheel - - - name: Release Python package to PyPI -# if: startsWith(github.ref, 'refs/tags') - env: - TWINE_USERNAME: __token__ - TWINE_PASSWORD: ${{ secrets.PYPI_TOKEN }} - run: | - twine upload dist/* diff --git a/.github/workflows/Test.yml b/.github/workflows/Test.yml deleted file mode 100644 index 8a8c4b9e2..000000000 --- a/.github/workflows/Test.yml +++ /dev/null @@ -1,95 +0,0 @@ -name: Test and Coverage - -on: [ push ] - -jobs: - Test: - name: Unit Tests - runs-on: ubuntu-latest - strategy: - fail-fast: false - max-parallel: 3 - matrix: - python-version: [ 3.6, 3.7, 3.8, 3.9 ] - - env: - PYTHON: ${{ matrix.python-version }} - steps: - - name: Checkout repository - uses: actions/checkout@v2 - - - name: Setup Python ${{ matrix.python-version }} - uses: actions/setup-python@v2 - with: - python-version: ${{ matrix.python-version }} - - - name: Install dependencies - run: | - python -m pip install --upgrade pip - pip install -r tests/requirements.txt - - - name: Run unit tests -# run: python -m unittest discover tests/unit *.py - run: | - python -m pytest -rA --cov=.. --cov-config=tests/.coveragerc tests/unit - - Coverage: - name: Collect Coverage Data - runs-on: ubuntu-latest - env: - PYTHON: 3.9 - steps: - - name: Checkout repository - uses: actions/checkout@v2 - - - name: Setup Python ${{ env.PYTHON }} - uses: actions/setup-python@v2 - with: - python-version: ${{ env.PYTHON }} - - - name: Install dependencies - run: | - python -m pip install --upgrade pip - pip install -r tests/requirements.txt - - - name: Collect coverage - if: ${{ always() }} -# run: coverage run -m unittest discover tests/unit *.py - run: | - python -m pytest -rA --cov=.. --cov-config=tests/.coveragerc tests/unit - - - name: Convert to cobertura format - if: ${{ always() }} - run: | - coverage xml - - - name: Publish coverage at CodeCov - if: ${{ always() }} - uses: codecov/codecov-action@v1 - with: - file: ./coverage.xml - flags: unittests - env_vars: PYTHON - - - name: Publish coverage at Codacy - if: ${{ always() }} - uses: codacy/codacy-coverage-reporter-action@master - with: - project-token: ${{ secrets.CODACY_PROJECT_TOKEN }} - coverage-reports: ./coverage.xml - - TriggerNext: - name: Trigger next Workflows - needs: [Test, Coverage] - runs-on: ubuntu-latest - env: - PYTHON: 3.9 - steps: - - name: Trigger Release Workflow - if: startsWith(github.ref, 'refs/tags') - uses: peter-evans/repository-dispatch@v1 - with: - token: ${{ secrets.TRIGGER_TOKEN_2 }} -# repository: vhdl/pyVHDLModel - event-type: doRelease - client-payload: '{"ref": "${{ github.ref }}", "sha": "${{ github.sha }}", "PYTHON": "${{ env.PYTHON }}"}' diff --git a/pyVHDLModel/VHDLModel.py b/pyVHDLModel/VHDLModel.py index 72ded2408..d37d797f1 100644 --- a/pyVHDLModel/VHDLModel.py +++ b/pyVHDLModel/VHDLModel.py @@ -424,7 +424,7 @@ def Name(self): @export -class RecordType(BaseType): +class RecordType(CompositeType): _members: List[RecordTypeMember] def __init__(self, name: str): From 9d7aedd2ae80ea3990458d7009ab423c8d886f3b Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Thu, 10 Jun 2021 23:41:46 +0200 Subject: [PATCH 03/39] Added dependabot configuration file. --- .github/dependabot.yml | 15 +++++++++++++++ .github/workflows/Pipeline.yml | 12 ++++++------ 2 files changed, 21 insertions(+), 6 deletions(-) create mode 100644 .github/dependabot.yml diff --git a/.github/dependabot.yml b/.github/dependabot.yml new file mode 100644 index 000000000..7c45a0d48 --- /dev/null +++ b/.github/dependabot.yml @@ -0,0 +1,15 @@ +version: 2 +updates: +- package-ecosystem: pip + directory: "/" + target-branch: dev + commit-message: + prefix: "[Dependency Update]" + labels: + - Dependencies + assignees: + - Paebbels + reviewers: + - Paebbels + schedule: + interval: daily diff --git a/.github/workflows/Pipeline.yml b/.github/workflows/Pipeline.yml index e9c06046d..07c276e6f 100644 --- a/.github/workflows/Pipeline.yml +++ b/.github/workflows/Pipeline.yml @@ -4,15 +4,15 @@ on: [ push ] jobs: UnitTesting: - name: Unit Tests + name: Unit Tests using Python ${{ matrix.python }} runs-on: ubuntu-latest strategy: fail-fast: false matrix: - python-version: [ 3.6, 3.7, 3.8, 3.9 ] + python: [ 3.6, 3.7, 3.8, 3.9 ] env: - PYTHON: ${{ matrix.python-version }} + PYTHON: ${{ matrix.python }} outputs: python: ${{ env.PYTHON }} @@ -20,10 +20,10 @@ jobs: - name: Checkout repository uses: actions/checkout@v2 - - name: Setup Python ${{ matrix.python-version }} + - name: Setup Python ${{ matrix.python }} uses: actions/setup-python@v2 with: - python-version: ${{ matrix.python-version }} + python-version: ${{ matrix.python }} - name: Install dependencies run: | @@ -35,7 +35,7 @@ jobs: python -m pytest -rA tests/unit Coverage: - name: Collect Coverage Data + name: Collect Coverage Data using Python ${{ env.PYTHON }} runs-on: ubuntu-latest env: From 8cf603ebef244f000827ee3a9342fa02cf77f1f4 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Thu, 10 Jun 2021 23:42:01 +0200 Subject: [PATCH 04/39] Documented enumerations. --- doc/LanguageModel/Enumerations.rst | 65 ++++++++++++++++++++++++++++-- 1 file changed, 61 insertions(+), 4 deletions(-) diff --git a/doc/LanguageModel/Enumerations.rst b/doc/LanguageModel/Enumerations.rst index cf600196c..29f7a7052 100644 --- a/doc/LanguageModel/Enumerations.rst +++ b/doc/LanguageModel/Enumerations.rst @@ -7,19 +7,57 @@ The language model contains some enumerations to express a *kind* of a models en .. rubric:: Table of Content +* :ref:`vhdlmodel-direction` * :ref:`vhdlmodel-mode` * :ref:`vhdlmodel-objclass` +.. _vhdlmodel-direction: + +Direction +========= + +Ranges and slices have an ascending (`to`) or descending (`downto`) direction. + +**Condensed definition of class** :class:`~pyVHDLModel.VHDLModel.Direction`: + +.. code-block:: Python + + @export + class Direction(Enum): + To = 0 + DownTo = 1 + + + .. _vhdlmodel-mode: Mode ==== -.. todo:: +A *mode* describes the direction of data exchange e.g. for entity ports or subprogram parameters. - Write documentation. +VHDL supports: + +* `in` +* `out` +* `inout` +* `buffer` +* `linkage` + +**Condensed definition of class** :class:`~pyVHDLModel.VHDLModel.Mode`: + +.. code-block:: Python + + @export + class Mode(Enum): + Default = 0 + In = 1 + Out = 2 + InOut = 3 + Buffer = 4 + Linkage = 5 @@ -28,6 +66,25 @@ Mode Object Class ============ -.. todo:: +VHDL has 4 object classes. + +These are + +* `Constant` +* `Variable` +* `Signal` +* `File` + +**Condensed definition of class** :class:`~pyVHDLModel.VHDLModel.Class`: + +.. code-block:: Python - Write documentation. + @export + class Class(Enum): + Default = 0 + Constant = 1 + Variable = 2 + Signal = 3 + File = 4 + Type = 5 + Subprogram = 6 From d93e458aedb6d1060d3188086788d2794837d728 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Thu, 10 Jun 2021 23:47:19 +0200 Subject: [PATCH 05/39] Fixed syntax error in yaml. --- .github/workflows/Pipeline.yml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/.github/workflows/Pipeline.yml b/.github/workflows/Pipeline.yml index 07c276e6f..ea4a8c5ca 100644 --- a/.github/workflows/Pipeline.yml +++ b/.github/workflows/Pipeline.yml @@ -6,6 +6,7 @@ jobs: UnitTesting: name: Unit Tests using Python ${{ matrix.python }} runs-on: ubuntu-latest + strategy: fail-fast: false matrix: @@ -35,7 +36,7 @@ jobs: python -m pytest -rA tests/unit Coverage: - name: Collect Coverage Data using Python ${{ env.PYTHON }} + name: Collect Coverage Data using Python 3.9 runs-on: ubuntu-latest env: From 2cccb02c4031702a5b6d62d91911733470bb59a0 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Fri, 11 Jun 2021 10:06:39 +0200 Subject: [PATCH 06/39] Added more cross references. --- doc/LanguageModel/ConcurrentStatements.rst | 32 ++++++++++---- doc/LanguageModel/ObjectDeclarations.rst | 20 ++++++--- doc/LanguageModel/SequentialStatements.rst | 36 +++++++++++---- doc/LanguageModel/TypeDefinitions.rst | 51 +++++++++++++++++----- 4 files changed, 106 insertions(+), 33 deletions(-) diff --git a/doc/LanguageModel/ConcurrentStatements.rst b/doc/LanguageModel/ConcurrentStatements.rst index e5db4df3e..4c4187dde 100644 --- a/doc/LanguageModel/ConcurrentStatements.rst +++ b/doc/LanguageModel/ConcurrentStatements.rst @@ -3,14 +3,16 @@ Concurrent Statements ##################### -* Assert -* Signal assignment -* Instantiation -* If generate -* Case generate -* For generate -* Procedure call -* Process +* :ref:`vhdlmodel-con-assertstatement` +* :ref:`vhdlmodel-con-signalassignment` +* :ref:`vhdlmodel-instantiation` +* :ref:`vhdlmodel-ifgenerate` +* :ref:`vhdlmodel-casegenerate` +* :ref:`vhdlmodel-forgenerate` +* :ref:`vhdlmodel-con-procedurecall` +* :ref:`vhdlmodel-process` + +.. _vhdlmodel-con-assertstatement: Assert ====== @@ -19,6 +21,8 @@ Assert Write documentation. +.. _vhdlmodel-con-signalassignment: + Signal Assignment ================= @@ -26,6 +30,8 @@ Signal Assignment Write documentation. +.. _vhdlmodel-instantiation: + Instantiation ============= @@ -33,6 +39,8 @@ Instantiation Write documentation. +.. _vhdlmodel-ifgenerate: + If Generate =========== @@ -40,6 +48,8 @@ If Generate Write documentation. +.. _vhdlmodel-casegenerate: + Case Generate ============= @@ -47,6 +57,8 @@ Case Generate Write documentation. +.. _vhdlmodel-forgenerate: + For Generate ============ @@ -54,6 +66,8 @@ For Generate Write documentation. +.. _vhdlmodel-con-procedurecall: + Procedure Call ============== @@ -61,6 +75,8 @@ Procedure Call Write documentation. +.. _vhdlmodel-process: + Process ======= diff --git a/doc/LanguageModel/ObjectDeclarations.rst b/doc/LanguageModel/ObjectDeclarations.rst index 375b26be2..41483cd18 100644 --- a/doc/LanguageModel/ObjectDeclarations.rst +++ b/doc/LanguageModel/ObjectDeclarations.rst @@ -3,11 +3,13 @@ Object Declartions ################### -* Constant -* Variable -* Shared variable -* Signal -* File +* :ref:`vhdlmodel-constant` +* :ref:`vhdlmodel-variable` +* :ref:`vhdlmodel-sharedvariable` +* :ref:`vhdlmodel-signal` +* :ref:`vhdlmodel-file` + +.. _vhdlmodel-constant: Constant ======== @@ -16,6 +18,8 @@ Constant Write documentation. +.. _vhdlmodel-variable: + Variable ======== @@ -23,6 +27,8 @@ Variable Write documentation. +.. _vhdlmodel-sharedvariable: + Shared Variable =============== @@ -30,6 +36,8 @@ Shared Variable Write documentation. +.. _vhdlmodel-signal: + Signal ====== @@ -37,6 +45,8 @@ Signal Write documentation. +.. _vhdlmodel-file: + File ==== diff --git a/doc/LanguageModel/SequentialStatements.rst b/doc/LanguageModel/SequentialStatements.rst index 299123d68..af9bd7e99 100644 --- a/doc/LanguageModel/SequentialStatements.rst +++ b/doc/LanguageModel/SequentialStatements.rst @@ -3,15 +3,17 @@ Sequential Statements ##################### -* Signal assignment -* Variable assignment -* If statement -* Case statement+ -* For loop -* While loop -* Report statement -* Assert statement -* Procedure call +* :ref:`vhdlmodel-seq-signalassignment` +* :ref:`vhdlmodel-variableassignment` +* :ref:`vhdlmodel-ifstatement` +* :ref:`vhdlmodel-casestatement` +* :ref:`vhdlmodel-forloop` +* :ref:`vhdlmodel-whileloop` +* :ref:`vhdlmodel-seq-reportstatement` +* :ref:`vhdlmodel-seq-assertstatement` +* :ref:`vhdlmodel-seq-procedurecall` + +.. _vhdlmodel-seq-signalassignment: Signal Assignment ================= @@ -20,6 +22,8 @@ Signal Assignment Write documentation. +.. _vhdlmodel-variableassignment: + Variable Assignment =================== @@ -27,6 +31,8 @@ Variable Assignment Write documentation. +.. _vhdlmodel-ifstatement: + If Statement ============ @@ -34,6 +40,8 @@ If Statement Write documentation. +.. _vhdlmodel-casestatement: + Case Statement ============== @@ -41,6 +49,8 @@ Case Statement Write documentation. +.. _vhdlmodel-forloop: + For Loop ======== @@ -48,6 +58,8 @@ For Loop Write documentation. +.. _vhdlmodel-whileloop: + While Loop ========== @@ -55,6 +67,8 @@ While Loop Write documentation. +.. _vhdlmodel-seq-reportstatement: + Report Statement ================ @@ -62,6 +76,8 @@ Report Statement Write documentation. +.. _vhdlmodel-seq-assertstatement: + Assert Statement ================ @@ -69,6 +85,8 @@ Assert Statement Write documentation. +.. _vhdlmodel-seq-procedurecall: + Procedure Call ============== diff --git a/doc/LanguageModel/TypeDefinitions.rst b/doc/LanguageModel/TypeDefinitions.rst index cc82d359a..63ca55991 100644 --- a/doc/LanguageModel/TypeDefinitions.rst +++ b/doc/LanguageModel/TypeDefinitions.rst @@ -3,30 +3,40 @@ Type Declarations ################# +VHDL has types (also called a base type) and subtypes. The following shows VHDL's type hierarchy: + +.. rubric:: Type Hierarchy + * Types - * Scalar types + * :ref:`vhdlmodel-scalartypes` - * Enumeration - * Integer - * Real - * Physical + * :ref:`vhdlmodel-enumeratedtypes` + * :ref:`vhdlmodel-integertypes` + * :ref:`vhdlmodel-realtypes` + * :ref:`vhdlmodel-physicaltypes` - * Composite types + * :ref:`vhdlmodel-compositetypes` - * Array - * Record + * :ref:`vhdlmodel-arraytypes` + * :ref:`vhdlmodel-recordtypes` - * Access - * File - * Protected + * :ref:`vhdlmodel-accesstypes` + * :ref:`vhdlmodel-filetypes` + * :ref:`vhdlmodel-protectedtypes` * Subtype + + +.. _vhdlmodel-scalartypes: + Scalar Types ============ +.. _vhdlmodel-enumeratedtypes: + Enumeration ----------- @@ -34,6 +44,8 @@ Enumeration Write documentation. +.. _vhdlmodel-integertypes: + Integer ------- @@ -41,6 +53,9 @@ Integer Write documentation. + +.. _vhdlmodel-realtypes: + Real ---- @@ -48,6 +63,8 @@ Real Write documentation. +.. _vhdlmodel-physicaltypes: + Physical -------- @@ -55,9 +72,13 @@ Physical Write documentation. +.. _vhdlmodel-compositetypes: + Composite Types =============== +.. _vhdlmodel-arraytypes: + Array ----- @@ -65,6 +86,8 @@ Array Write documentation. +.. _vhdlmodel-recordtypes: + Record ------ @@ -72,6 +95,8 @@ Record Write documentation. +.. _vhdlmodel-accesstypes: + Access ====== @@ -79,6 +104,8 @@ Access Write documentation. +.. _vhdlmodel-filetypes: + File ==== @@ -86,6 +113,8 @@ File Write documentation. +.. _vhdlmodel-protectedtypes: + Protected ========= From d247553c9634f12f9b8f2d6897c045171f63dd73 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Fri, 11 Jun 2021 11:51:42 +0200 Subject: [PATCH 07/39] More documentation and cross references. --- doc/LanguageModel/Enumerations.rst | 24 ++-- doc/LanguageModel/InterfaceItems.rst | 13 +++ doc/LanguageModel/ObjectDeclarations.rst | 138 +++++++++++++++++++++-- 3 files changed, 147 insertions(+), 28 deletions(-) diff --git a/doc/LanguageModel/Enumerations.rst b/doc/LanguageModel/Enumerations.rst index 29f7a7052..bbc6dd1f0 100644 --- a/doc/LanguageModel/Enumerations.rst +++ b/doc/LanguageModel/Enumerations.rst @@ -3,7 +3,8 @@ Enumerations ############ -The language model contains some enumerations to express a *kind* of a models entity. +The language model contains some enumerations to express a *kind* of a models +entity. These are not enumerated types defined by VHDL itself, like `boolean`. .. rubric:: Table of Content @@ -37,14 +38,8 @@ Mode ==== A *mode* describes the direction of data exchange e.g. for entity ports or subprogram parameters. - -VHDL supports: - -* `in` -* `out` -* `inout` -* `buffer` -* `linkage` +In addition to the modes defined by VHDL (`In`, `Out`, `InOut`, `Buffer` and `Linkage`), `Default` +is a placeholder for omitted modes. The mode is then determined from the context. **Condensed definition of class** :class:`~pyVHDLModel.VHDLModel.Mode`: @@ -66,14 +61,9 @@ VHDL supports: Object Class ============ -VHDL has 4 object classes. - -These are - -* `Constant` -* `Variable` -* `Signal` -* `File` +In addition to the 4 object classes defined by VHDL (`Constant`, `Variable`, +`Signal` and `File`), `Default` is used when no object class is defined. In +such a case, the object class is determined from the context. **Condensed definition of class** :class:`~pyVHDLModel.VHDLModel.Class`: diff --git a/doc/LanguageModel/InterfaceItems.rst b/doc/LanguageModel/InterfaceItems.rst index 507625b31..7c1968838 100644 --- a/doc/LanguageModel/InterfaceItems.rst +++ b/doc/LanguageModel/InterfaceItems.rst @@ -23,10 +23,13 @@ Interface items are used in generic, port and parameter declarations. * :class:`~pyVHDLModel.VHDLModel.ParameterSignalInterfaceItem` * :class:`~pyVHDLModel.VHDLModel.ParameterFileInterfaceItem` +.. _vhdlmodel-generics: Generic Interface Item ====================== +.. _vhdlmodel-genericconstant: + GenericConstantInterfaceItem ---------------------------- @@ -42,6 +45,7 @@ GenericConstantInterfaceItem class GenericConstantInterfaceItem(GenericInterfaceItem): +.. _vhdlmodel-generictype: GenericTypeInterfaceItem ------------------------ @@ -58,6 +62,7 @@ GenericTypeInterfaceItem class GenericTypeInterfaceItem(GenericInterfaceItem): +.. _vhdlmodel-genericsubprogram: GenericSubprogramInterfaceItem ------------------------------ @@ -74,6 +79,7 @@ GenericSubprogramInterfaceItem class GenericSubprogramInterfaceItem(GenericInterfaceItem): +.. _vhdlmodel-genericpackage: GenericPackageInterfaceItem --------------------------- @@ -90,10 +96,12 @@ GenericPackageInterfaceItem class GenericPackageInterfaceItem(GenericInterfaceItem): +.. _vhdlmodel-ports: Port Interface Item =================== +.. _vhdlmodel-portsignal: PortSignalInterfaceItem ----------------------- @@ -109,10 +117,12 @@ PortSignalInterfaceItem @Export class PortSignalInterfaceItem(PortInterfaceItem): +.. _vhdlmodel-parameters: Parameter Interface Item ========================= +.. _vhdlmodel-parameterconstant: ParameterConstantInterfaceItem ------------------------------ @@ -129,6 +139,7 @@ ParameterConstantInterfaceItem class ParameterConstantInterfaceItem(ParameterInterfaceItem): +.. _vhdlmodel-parametervariable: ParameterVariableInterfaceItem ------------------------------ @@ -145,6 +156,7 @@ ParameterVariableInterfaceItem class ParameterVariableInterfaceItem(ParameterInterfaceItem): +.. _vhdlmodel-parametersignal: ParameterSignalInterfaceItem ---------------------------- @@ -161,6 +173,7 @@ ParameterSignalInterfaceItem class ParameterSignalInterfaceItem(ParameterInterfaceItem): +.. _vhdlmodel-parameterfile: ParameterFileInterfaceItem -------------------------- diff --git a/doc/LanguageModel/ObjectDeclarations.rst b/doc/LanguageModel/ObjectDeclarations.rst index 41483cd18..a916727a8 100644 --- a/doc/LanguageModel/ObjectDeclarations.rst +++ b/doc/LanguageModel/ObjectDeclarations.rst @@ -1,32 +1,104 @@ .. _vhdlmodel-obj: -Object Declartions +Object Declarations ################### -* :ref:`vhdlmodel-constant` -* :ref:`vhdlmodel-variable` +* :ref:`vhdlmodel-constants` + * :ref:`vhdlmodel-constant` + * :ref:`vhdlmodel-deferredconstant` + * :ref:`vhdlmodel-obj-genericconstant` + * :ref:`vhdlmodel-obj-parameterconstant` +* :ref:`vhdlmodel-variables` + * :ref:`vhdlmodel-variable` + * :ref:`vhdlmodel-obj-parametervariable` * :ref:`vhdlmodel-sharedvariable` -* :ref:`vhdlmodel-signal` -* :ref:`vhdlmodel-file` +* :ref:`vhdlmodel-signals` + * :ref:`vhdlmodel-signal` + * :ref:`vhdlmodel-obj-portsignal` + * :ref:`vhdlmodel-obj-parametersignal` +* :ref:`vhdlmodel-files` + * :ref:`vhdlmodel-file` + * :ref:`vhdlmodel-obj-parameterfile` + +.. _vhdlmodel-constants: + +Constants +========= + +VHDL defines regular constants as an object. In addition, deferred constants are +supported in package declarations. Often generics to e.g. packages or entities +are constants. Also most *in* parameters to subprograms are constants. + +.. inheritance-diagram:: pyVHDLModel.VHDLModel.Constant pyVHDLModel.VHDLModel.DeferredConstant pyVHDLModel.VHDLModel.GenericConstantInterfaceItem pyVHDLModel.VHDLModel.ParameterConstantInterfaceItem + :parts: 1 .. _vhdlmodel-constant: Constant -======== +-------- + +.. _vhdlmodel-deferredconstant: + +DeferredConstant +---------------- .. todo:: Write documentation. +.. _vhdlmodel-obj-genericconstant: + +GenericConstantInterfaceItem +---------------------------- + +A generic without object class or a generic constant is a *regular* constant. + +.. seealso:: + + See :ref:`vhdlmodel-genericconstant` for details. + +.. _vhdlmodel-obj-paramaterconstant: + +ParameterConstantInterfaceItem +------------------------------ + +A subprogram parameter without object class of mode *in* or a parameter constant is a *regular* constant. + +.. seealso:: + + See :ref:`vhdlmodel-parameterconstant` for details. + + + +.. _vhdlmodel-variables: + +Variables +========= + +.. inheritance-diagram:: pyVHDLModel.VHDLModel.Variable pyVHDLModel.VHDLModel.ParameterVariableInterfaceItem + :parts: 1 + .. _vhdlmodel-variable: Variable -======== +-------- .. todo:: Write documentation. +.. _vhdlmodel-obj-parametervariable: + +ParameterVariableInterfaceItem +------------------------------ + +A subprogram parameter without object class of mode *out* or a parameter variable is a *regular* variable. + +.. seealso:: + + See :ref:`vhdlmodel-parametervariable` for details. + + .. _vhdlmodel-sharedvariable: Shared Variable @@ -36,20 +108,64 @@ Shared Variable Write documentation. +.. _vhdlmodel-signals: + +Signals +======= + +.. inheritance-diagram:: pyVHDLModel.VHDLModel.Signal pyVHDLModel.VHDLModel.PortSignalInterfaceItem pyVHDLModel.VHDLModel.ParameterSignalInterfaceItem + :parts: 1 + .. _vhdlmodel-signal: Signal -====== +------ .. todo:: Write documentation. -.. _vhdlmodel-file: +.. _vhdlmodel-obj-portsignal: + +PortSignalInterfaceItem +----------------------- + +A port signal is a *regular* signal. + +.. seealso:: + + See :ref:`vhdlmodel-portsignal` for details. + +.. _vhdlmodel-obj-parametersignal: -File -==== +ParameterSignalInterfaceItem +---------------------------- + +A parameter signal is a *regular* signal. + +.. seealso:: + + See :ref:`vhdlmodel-parametersignal` for details. + +.. _vhdlmodel-files: + +Files +===== + +.. inheritance-diagram:: pyVHDLModel.VHDLModel.File pyVHDLModel.VHDLModel.ParameterFileInterfaceItem + :parts: 1 .. todo:: Write documentation. + +.. _vhdlmodel-obj-parameterfile: + +ParameterFileInterfaceItem +-------------------------- + +A parameter file is a *regular* file. + +.. seealso:: + + See :ref:`vhdlmodel-parameterfile` for details. From 8e5696faee8cd8fc60035549ced120f51eff06e2 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Fri, 11 Jun 2021 12:02:54 +0200 Subject: [PATCH 08/39] Added news/change log for June 2021. --- doc/LanguageModel/ObjectDeclarations.rst | 14 +++++++++++++- doc/index.rst | 18 ++++++++++++++++-- 2 files changed, 29 insertions(+), 3 deletions(-) diff --git a/doc/LanguageModel/ObjectDeclarations.rst b/doc/LanguageModel/ObjectDeclarations.rst index a916727a8..f1ac8f50c 100644 --- a/doc/LanguageModel/ObjectDeclarations.rst +++ b/doc/LanguageModel/ObjectDeclarations.rst @@ -4,19 +4,26 @@ Object Declarations ################### * :ref:`vhdlmodel-constants` + * :ref:`vhdlmodel-constant` * :ref:`vhdlmodel-deferredconstant` * :ref:`vhdlmodel-obj-genericconstant` * :ref:`vhdlmodel-obj-parameterconstant` + * :ref:`vhdlmodel-variables` + * :ref:`vhdlmodel-variable` * :ref:`vhdlmodel-obj-parametervariable` + * :ref:`vhdlmodel-sharedvariable` * :ref:`vhdlmodel-signals` + * :ref:`vhdlmodel-signal` * :ref:`vhdlmodel-obj-portsignal` * :ref:`vhdlmodel-obj-parametersignal` + * :ref:`vhdlmodel-files` + * :ref:`vhdlmodel-file` * :ref:`vhdlmodel-obj-parameterfile` @@ -57,7 +64,7 @@ A generic without object class or a generic constant is a *regular* constant. See :ref:`vhdlmodel-genericconstant` for details. -.. _vhdlmodel-obj-paramaterconstant: +.. _vhdlmodel-obj-parameterconstant: ParameterConstantInterfaceItem ------------------------------ @@ -155,6 +162,11 @@ Files .. inheritance-diagram:: pyVHDLModel.VHDLModel.File pyVHDLModel.VHDLModel.ParameterFileInterfaceItem :parts: 1 +.. _vhdlmodel-file: + +File +---- + .. todo:: Write documentation. diff --git a/doc/index.rst b/doc/index.rst index 64791b9be..fdf903c2f 100644 --- a/doc/index.rst +++ b/doc/index.rst @@ -57,6 +57,19 @@ Use Cases News **** +.. only:: html + + Jun. 2021 - Model and documentation enhancements + ================================================ + +.. only:: latex + + .. rubric:: Model and documentation enhancements + +* Made generic, port, and parameter items a subclass of the matching object classes. +* Enhanced class documentation and cross references. +* ... + .. only:: html Jan. 2021 - Documentation enhancements @@ -68,7 +81,8 @@ News * Enhanced class documentation. * Changed test runner to ``pytest``. -* Dependency check and license clearance. +* Dependency check and license clearance. |br| + See :ref:`dependency` for details. .. only:: html @@ -80,7 +94,7 @@ News .. rubric:: Split from pyVHDLParser -`pyVHDLModel` was split from `pyVHDLParser` (v0.6.0) as an independent Python package. +* `pyVHDLModel` was split from `pyVHDLParser `__ (v0.6.0) as an independent Python package. From ceade95e32750bfc7517f37e117b26881628e523 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Fri, 11 Jun 2021 12:28:07 +0200 Subject: [PATCH 09/39] Changed object dependencies. Added condensed code for constants. --- doc/LanguageModel/ObjectDeclarations.rst | 60 +++- pyVHDLModel/VHDLModel.py | 409 +++++++++++------------ 2 files changed, 250 insertions(+), 219 deletions(-) diff --git a/doc/LanguageModel/ObjectDeclarations.rst b/doc/LanguageModel/ObjectDeclarations.rst index f1ac8f50c..bbf1583a1 100644 --- a/doc/LanguageModel/ObjectDeclarations.rst +++ b/doc/LanguageModel/ObjectDeclarations.rst @@ -3,6 +3,8 @@ Object Declarations ################### +.. rubric:: Table of Content + * :ref:`vhdlmodel-constants` * :ref:`vhdlmodel-constant` @@ -27,6 +29,8 @@ Object Declarations * :ref:`vhdlmodel-file` * :ref:`vhdlmodel-obj-parameterfile` + + .. _vhdlmodel-constants: Constants @@ -39,19 +43,71 @@ are constants. Also most *in* parameters to subprograms are constants. .. inheritance-diagram:: pyVHDLModel.VHDLModel.Constant pyVHDLModel.VHDLModel.DeferredConstant pyVHDLModel.VHDLModel.GenericConstantInterfaceItem pyVHDLModel.VHDLModel.ParameterConstantInterfaceItem :parts: 1 + + .. _vhdlmodel-constant: Constant -------- +A constant represents immutable data. This data (value) must be assigned via a +default expression. If a constant's value is delayed in calculation, it's called +a deferred constant. See :ref:`vhdlmodel-deferredconstant` in next section. + + +**Condensed definition of class** :class:`~pyVHDLModel.VHDLModel.Constant`: + +.. code-block:: Python + + @export + class Constant(BaseConstant): + # inherited from ModelEntity + @property + def Parent(self) -> 'ModelEntity': + + # inherited from NamedEntity + @property + def Name(self) -> str: + + # inherited from Object + @property + def SubType(self) -> SubType: + + @property + def DefaultExpression(self) -> Expression: + + + .. _vhdlmodel-deferredconstant: DeferredConstant ---------------- -.. todo:: +If a constant's value is delayed in calculation, it's a deferred constant. Such +a deferred constant has a reference to the *regular* constant of the same name. + +**Condensed definition of class** :class:`~pyVHDLModel.VHDLModel.DeferredConstant`: + +.. code-block:: Python + + @export + class DeferredConstant(BaseConstant): + # inherited from ModelEntity + @property + def Parent(self) -> 'ModelEntity': + + # inherited from NamedEntity + @property + def Name(self) -> str: + + # inherited from Object + @property + def SubType(self) -> SubType: + + @property + def ConstantReference(self) -> Constant: + - Write documentation. .. _vhdlmodel-obj-genericconstant: diff --git a/pyVHDLModel/VHDLModel.py b/pyVHDLModel/VHDLModel.py index d37d797f1..139fed369 100644 --- a/pyVHDLModel/VHDLModel.py +++ b/pyVHDLModel/VHDLModel.py @@ -63,9 +63,6 @@ class ModelEntity: """ _parent: 'ModelEntity' #: Reference to a parent entity in the model. - def __init__(self): - self._parent = None - @property def Parent(self) -> 'ModelEntity': """Returns a reference to the parent entity.""" @@ -525,121 +522,241 @@ class Range: def __init__(self): pass - @export -class InterfaceItem(ModelEntity): - _name: str - _mode: Mode +class Object(ModelEntity, NamedEntity): + _subType: SubType - def __init__(self, name: str, mode: Mode): + def __init__(self, name: str): super().__init__() - - self._name = name - self._mode = mode - - @property - def Name(self) -> str: - return self._name + NamedEntity.__init__(self, name) @property - def Mode(self) -> Mode: - return self._mode + def SubType(self) -> SubType: + return self._subType @export -class GenericInterfaceItem(InterfaceItem): +class BaseConstant(Object): pass @export -class PortInterfaceItem(InterfaceItem): - pass +class Constant(BaseConstant): + _defaultExpression: Expression + def __init__(self, name: str): + super().__init__(name) -@export -class ParameterInterfaceItem(InterfaceItem): - pass + @property + def DefaultExpression(self) -> Expression: + return self._defaultExpression @export -class GenericConstantInterfaceItem(GenericInterfaceItem): - _subtype: SubType # FIXME: add documentation - _defaultExpression: Expression # FIXME: add documentation +class DeferredConstant(BaseConstant): + _constantReference: Constant + + def __init__(self, name: str): + super().__init__(name) @property - def SubType(self) -> SubType: - return self._subType + def ConstantReference(self) -> Constant: + return self._constantReference + + +@export +class Variable(Object): + _defaultExpression: Expression + + def __init__(self, name: str): + super().__init__(name) @property def DefaultExpression(self) -> Expression: return self._defaultExpression -@export -class GenericTypeInterfaceItem(GenericInterfaceItem): - pass @export -class GenericSubprogramInterfaceItem(GenericInterfaceItem): - pass +class Signal(Object): + _defaultExpression: Expression + + def __init__(self, name: str): + super().__init__(name) + + @property + def DefaultExpression(self) -> Expression: + return self._defaultExpression @export -class GenericPackageInterfaceItem(GenericInterfaceItem): - pass +class File(Object): +# _defaultExpression: Expression + def __init__(self, name: str): + super().__init__(name) @export -class PortSignalInterfaceItem(PortInterfaceItem): - _subType: SubType - _defaultExpression: Expression +class SubProgramm(ModelEntity, NamedEntity): + _genericItems: List['GenericInterfaceItem'] + _parameterItems: List['ParameterInterfaceItem'] + _declaredItems: List + _bodyItems: List['SequentialStatement'] + _isPure: bool - def __init__(self, name: str, mode: Mode): - super().__init__(name, mode) + def __init__(self, name: str): + super().__init__() + NamedEntity.__init__(self, name) + + self._genericItems = [] + self._parameterItems = [] + self._declaredItems = [] + self._bodyItems = [] @property - def SubType(self) -> SubType: - return self._subType + def GenericItems(self) -> List['GenericInterfaceItem']: + return self._genericItems @property - def DefaultExpression(self) -> Expression: - return self._defaultExpression + def ParameterItems(self) -> List['ParameterInterfaceItem']: + return self._parameterItems + + @property + def DeclaredItems(self) -> List: + return self._declaredItems + + @property + def BodyItems(self) -> List['SequentialStatement']: + return self._bodyItems + + @property + def IsPure(self) -> bool: + return self._isPure @export -class ParameterConstantInterfaceItem(ParameterInterfaceItem): - pass +class Procedure(SubProgramm): + _isPure: bool = False @export -class ParameterVariableInterfaceItem(ParameterInterfaceItem): - _subType: SubType - _mode: Mode - _defaultExpression: Expression +class Function(SubProgramm): + _returnType: SubType - def __init__(self, name: str): + def __init__(self, name: str, isPure: bool = True): super().__init__(name) + self._isPure = isPure @property - def SubType(self) -> SubType: - return self._subType + def ReturnType(self) -> SubType: + return self._returnType + + +@export +class Method: + _protectedType: ProtectedType + + def __init__(self, protectedType: ProtectedType): + self._protectedType = protectedType + + @property + def ProtectedType(self) -> ProtectedType: + return self._protectedType + + +@export +class ProcedureMethod(Procedure, Method): + def __init__(self, name: str, protectedType: ProtectedType): + super().__init__(name) + Method.__init__(self, protectedType) + + +@export +class FunctionMethod(Function, Method): + def __init__(self, name: str, protectedType: ProtectedType): + super().__init__(name) + Method.__init__(self, protectedType) + + +@export +class InterfaceItem: + _mode: Mode + + def __init__(self, mode: Mode): + self._mode = mode @property def Mode(self) -> Mode: return self._mode - @property - def DefaultExpression(self) -> Expression: - return self._defaultExpression + +@export +class GenericInterfaceItem(InterfaceItem): + pass + + +@export +class PortInterfaceItem(InterfaceItem): + pass + + +@export +class ParameterInterfaceItem(InterfaceItem): + pass + + +@export +class GenericConstantInterfaceItem(Constant, GenericInterfaceItem): + def __init__(self, name: str, mode: Mode): + super().__init__(name) + GenericInterfaceItem.__init__(self, mode) @export -class ParameterSignalInterfaceItem(ParameterInterfaceItem): +class GenericTypeInterfaceItem(GenericInterfaceItem): pass +@export +class GenericSubprogramInterfaceItem(GenericInterfaceItem): + pass @export -class ParameterFileInterfaceItem(ParameterInterfaceItem): +class GenericPackageInterfaceItem(GenericInterfaceItem): pass + +@export +class PortSignalInterfaceItem(Signal, PortInterfaceItem): + def __init__(self, name: str, mode: Mode): + super().__init__(name) + PortInterfaceItem.__init__(self, mode) + + +@export +class ParameterConstantInterfaceItem(Constant, ParameterInterfaceItem): + def __init__(self, name: str, mode: Mode): + super().__init__(name) + ParameterInterfaceItem.__init__(self, mode) + + +@export +class ParameterVariableInterfaceItem(Variable, ParameterInterfaceItem): + def __init__(self, name: str, mode: Mode): + super().__init__(name) + ParameterInterfaceItem.__init__(self, mode) + + +@export +class ParameterSignalInterfaceItem(Signal, ParameterInterfaceItem): + def __init__(self, name: str, mode: Mode): + super().__init__(name) + ParameterInterfaceItem.__init__(self, mode) + + +@export +class ParameterFileInterfaceItem(File, ParameterInterfaceItem): + def __init__(self, name: str, mode: Mode): + super().__init__(name) + ParameterInterfaceItem.__init__(self, mode) + # class GenericItem(ModelEntity): # def __init__(self): # super().__init__() @@ -849,6 +966,23 @@ def __init__(self, name: str): class Instantiation: pass +@export +class SubprogramInstantiation(ModelEntity, Instantiation): + def __init__(self): + super().__init__() + Instantiation.__init__(self) + self._subprogramReference = None + + +@export +class ProcedureInstantiation(SubprogramInstantiation): + pass + + +@export +class FunctionInstantiation(SubprogramInstantiation): + pass + @export class Package(PrimaryUnit): @@ -933,165 +1067,6 @@ def GenericAssociations(self) -> List[GenericAssociationItem]: return self._genericAssociations -@export -class Object(ModelEntity, NamedEntity): - _subType: SubType - - def __init__(self, name: str): - super().__init__() - NamedEntity.__init__(self, name) - - @property - def SubType(self) -> SubType: - return self._subType - - -@export -class BaseConstant(Object): - pass - - -@export -class Constant(BaseConstant): - _defaultExpression: Expression - - def __init__(self, name: str): - super().__init__(name) - - @property - def DefaultExpression(self) -> Expression: - return self._defaultExpression - - -@export -class DeferredConstant(BaseConstant): - _constantReference: Constant - - def __init__(self, name: str): - super().__init__(name) - - @property - def ConstantReference(self) -> Constant: - return self._constantReference - - -@export -class Variable(Object): - _defaultExpression: Expression - - def __init__(self, name: str): - super().__init__(name) - - @property - def DefaultExpression(self) -> Expression: - return self._defaultExpression - - -@export -class Signal(Object): - _defaultExpression: Expression - - def __init__(self, name: str): - super().__init__(name) - - @property - def DefaultExpression(self) -> Expression: - return self._defaultExpression - - -@export -class SubProgramm(ModelEntity, NamedEntity): - _genericItems: List[GenericInterfaceItem] - _parameterItems: List[ParameterInterfaceItem] - _declaredItems: List - _bodyItems: List['SequentialStatement'] - - def __init__(self, name: str): - super().__init__() - NamedEntity.__init__(self, name) - - self._genericItems = [] - self._parameterItems = [] - self._declaredItems = [] - self._bodyItems = [] - - @property - def GenericItems(self) -> List[GenericInterfaceItem]: - return self._genericItems - - @property - def ParameterItems(self) -> List[ParameterInterfaceItem]: - return self._parameterItems - - @property - def DeclaredItems(self) -> List: - return self._declaredItems - - @property - def BodyItems(self) -> List['SequentialStatement']: - return self._bodyItems - - -@export -class Procedure(SubProgramm): - pass - - -@export -class Function(SubProgramm): - _returnType: SubType - _isPure: bool = True - - def __init__(self, name: str): - super().__init__(name) - - @property - def ReturnType(self) -> SubType: - return self._returnType - - @property - def IsPure(self) -> bool: - return self._isPure - - -@export -class SubprogramInstantiation(ModelEntity, Instantiation): - def __init__(self): - super().__init__() - Instantiation.__init__(self) - self._subprogramReference = None - - -@export -class ProcedureInstantiation(SubprogramInstantiation): - pass - - -@export -class FunctionInstantiation(SubprogramInstantiation): - pass - - -@export -class Method: - def __init__(self): - self._protectedType = None - - -@export -class ProcedureMethod(Procedure, Method): - def __init__(self, name: str): - super().__init__(name) - Method.__init__(self) - - -@export -class FunctionMethod(Function, Method): - def __init__(self, name: str): - super().__init__(name) - Method.__init__(self) - - @export class Statement(ModelEntity, LabeledEntity): def __init__(self, label: str = None): From ac8fc85de1209b0fe512f0abac2cd5c886f10c11 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Fri, 11 Jun 2021 14:00:28 +0200 Subject: [PATCH 10/39] Added base-class and mixin descriptions. --- pyVHDLModel/VHDLModel.py | 182 ++++++++++++++++++++++++++------------- 1 file changed, 121 insertions(+), 61 deletions(-) diff --git a/pyVHDLModel/VHDLModel.py b/pyVHDLModel/VHDLModel.py index 139fed369..9639b8723 100644 --- a/pyVHDLModel/VHDLModel.py +++ b/pyVHDLModel/VHDLModel.py @@ -249,8 +249,11 @@ class Direction(Enum): @export class Mode(Enum): """ - A ``Mode`` is an enumeration and represents a direction (``in``, ``out``, ...) - for how objects are passed. + A ``Mode`` is an enumeration. It represents the direction of data exchange + (``in``, ``out``, ...) for objects in generic, port or parameter lists. + + In case no *mode* is define, ``Default`` is used, so the *mode* is inferred + from context. """ Default = 0 In = 1 @@ -263,8 +266,11 @@ class Mode(Enum): @export class Class(Enum): """ - A ``Class`` is an enumeration and represents an object's class (``constant``, + A ``Class`` is an enumeration. It represents an object's class (``constant``, ``signal``, ...). + + In case no *object class* is define, ``Default`` is used, so the *object class* + is inferred from context. """ Default = 0 Constant = 1 @@ -327,12 +333,16 @@ class ScalarType(BaseType): @export class NumericType: - pass + """ + A ``NumericType`` is a mixin class for all numeric types. + """ @export class DiscreteType: - pass + """ + A ``DiscreteType`` is a mixin class for all discrete types. + """ @export @@ -445,7 +455,7 @@ class Literal: @export -class IntegerLiteral: +class IntegerLiteral(Literal): _value: int def __init__(self, value: int): @@ -457,7 +467,7 @@ def Value(self): @export -class FloatingPointLiteral: +class FloatingPointLiteral(Literal): _value: float def __init__(self, value: float): @@ -536,63 +546,51 @@ def SubType(self) -> SubType: @export -class BaseConstant(Object): - pass - - -@export -class Constant(BaseConstant): +class WithDefaultExpression: + """ + A ``WithDefaultExpression`` is a mixin class for all objects declarations + accepting default expressions. + """ _defaultExpression: Expression - def __init__(self, name: str): - super().__init__(name) - @property def DefaultExpression(self) -> Expression: return self._defaultExpression @export -class DeferredConstant(BaseConstant): - _constantReference: Constant +class BaseConstant(Object): + pass - def __init__(self, name: str): - super().__init__(name) - @property - def ConstantReference(self) -> Constant: - return self._constantReference +@export +class Constant(BaseConstant, WithDefaultExpression): + pass @export -class Variable(Object): - _defaultExpression: Expression - - def __init__(self, name: str): - super().__init__(name) +class DeferredConstant(BaseConstant): + _constantReference: Constant @property - def DefaultExpression(self) -> Expression: - return self._defaultExpression + def ConstantReference(self) -> Constant: + return self._constantReference @export -class Signal(Object): - _defaultExpression: Expression +class Variable(Object, WithDefaultExpression): + pass - def __init__(self, name: str): - super().__init__(name) - @property - def DefaultExpression(self) -> Expression: - return self._defaultExpression +@export +class Signal(Object, WithDefaultExpression): + pass @export class File(Object): + pass # _defaultExpression: Expression - def __init__(self, name: str): - super().__init__(name) @export class SubProgramm(ModelEntity, NamedEntity): @@ -652,6 +650,9 @@ def ReturnType(self) -> SubType: @export class Method: + """ + A ``Method`` is a mixin class for all subprograms in a protected type. + """ _protectedType: ProtectedType def __init__(self, protectedType: ProtectedType): @@ -678,6 +679,10 @@ def __init__(self, name: str, protectedType: ProtectedType): @export class InterfaceItem: + """ + An ``InterfaceItem`` is a base-class for all mixin-classes for all interface + items. + """ _mode: Mode def __init__(self, mode: Mode): @@ -690,17 +695,23 @@ def Mode(self) -> Mode: @export class GenericInterfaceItem(InterfaceItem): - pass + """ + A ``GenericInterfaceItem`` is a mixin class for all generic interface items. + """ @export class PortInterfaceItem(InterfaceItem): - pass + """ + A ``PortInterfaceItem`` is a mixin class for all port interface items. + """ @export class ParameterInterfaceItem(InterfaceItem): - pass + """ + A ``ParameterInterfaceItem`` is a mixin class for all parameter interface items. + """ @export @@ -718,6 +729,14 @@ class GenericTypeInterfaceItem(GenericInterfaceItem): class GenericSubprogramInterfaceItem(GenericInterfaceItem): pass +@export +class GenericProcedureInterfaceItem(Procedure, GenericInterfaceItem): + pass + +@export +class GenericFunctionInterfaceItem(Function, GenericInterfaceItem): + pass + @export class GenericPackageInterfaceItem(GenericInterfaceItem): pass @@ -943,17 +962,18 @@ def Actual(self) -> Expression: @export -class GenericAssociationItem(InterfaceItem): +class GenericAssociationItem(AssociationItem): pass @export -class PortAssociationItem(InterfaceItem): +class PortAssociationItem(AssociationItem): pass @export -class ParameterAssociationItem(InterfaceItem): +class ParameterAssociationItem(AssociationItem): pass + @export class Configuration(ModelEntity, NamedEntity): def __init__(self, name: str): @@ -961,7 +981,6 @@ def __init__(self, name: str): NamedEntity.__init__(self, name) - @export class Instantiation: pass @@ -975,12 +994,12 @@ def __init__(self): @export -class ProcedureInstantiation(SubprogramInstantiation): +class ProcedureInstantiation(Procedure, SubprogramInstantiation): pass @export -class FunctionInstantiation(SubprogramInstantiation): +class FunctionInstantiation(Function, SubprogramInstantiation): pass @@ -1076,12 +1095,16 @@ def __init__(self, label: str = None): @export class ConcurrentStatement(Statement): - pass + """ + A ``ConcurrentStatement`` is a base-class for all concurrent statements. + """ @export class SequentialStatement(Statement): - pass + """ + A ``SequentialStatement`` is a base-class for all sequential statements. + """ @export @@ -1145,11 +1168,11 @@ def PortItems(self) -> List[PortInterfaceItem]: @export class BaseConditional: + """ + A ``BaseConditional`` is a base-class for all conditional statements. + """ _condition: Expression - def __init__(self): - super().__init__() - @property def Condition(self) -> Expression: return self._condition @@ -1157,10 +1180,15 @@ def Condition(self) -> Expression: @export class BaseBranch: - pass + """ + A ``BaseBranch`` is a base-class for all statements with branches. + """ @export class BaseConditionalBranch(BaseBranch, BaseConditional): + """ + A ``BaseBranch`` is a base-class for all conditional statements with branches. + """ def __init__(self): super().__init__() BaseConditional.__init__(self) @@ -1168,19 +1196,30 @@ def __init__(self): @export class BaseIfBranch(BaseConditionalBranch): - pass + """ + A ``BaseIfBranch`` is a base-class for all conditional statements with + if-branches. + """ @export class BaseElsifBranch(BaseConditionalBranch): - pass + """ + A ``BaseElsifBranch`` is a base-class for all conditional statements with + elsif-branches. + """ @export class BaseElseBranch(BaseBranch): - pass + """ + A ``BaseElseBranch`` is a base-class for all conditional statements with + else-branches. + """ @export class GenerateBranch(ModelEntity): - pass + """ + A ``GenerateBranch`` is a base-class for all branches in a generate statements. + """ @export class IfGenerateBranch(GenerateBranch, BaseIfBranch): @@ -1257,6 +1296,9 @@ def Range(self) -> Range: @export class Assignment: + """ + An ``Assignment`` is a base-class for all assignment statements. + """ _target: Object _expression: Expression @@ -1274,12 +1316,16 @@ def Expression(self) -> Expression: @export class SignalAssignment(Assignment): - pass + """ + An ``SignalAssignment`` is a base-class for all signal assignment statements. + """ @export class VariableAssignment(Assignment): - pass + """ + An ``VariableAssignment`` is a base-class for all variable assignment statements. + """ @export @@ -1307,6 +1353,9 @@ def __init__(self): @export class ReportStatement: + """ + A ``ReportStatement`` is a base-class for all report and assert statements. + """ _message: Expression _severity: Expression @@ -1324,6 +1373,9 @@ def Severity(self) -> Expression: @export class AssertStatement(ReportStatement): + """ + A ``AssertStatement`` is a base-class for all assert statements. + """ _condition: Expression def __init__(self): @@ -1382,6 +1434,9 @@ def __init__(self): @export class CompoundStatement(SequentialStatement): + """ + A ``CompoundStatement`` is a base-class for all compound statements. + """ _bodyItems: List[SequentialStatement] def __init__(self): @@ -1420,7 +1475,9 @@ def ElseBranch(self) -> ElseBranch: @export class LoopStatement(CompoundStatement): - pass + """ + A ``LoopStatement`` is a base-class for all loop statements. + """ @export @@ -1449,6 +1506,9 @@ def __init__(self): @export class LoopControlStatement(ModelEntity, BaseConditional): + """ + A ``LoopControlStatement`` is a base-class for all loop controlling statements. + """ _loopReference: LoopStatement def __init__(self): From 77ac747ae479d053b86d3632ae837dcdf44f72ec Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Fri, 11 Jun 2021 14:00:50 +0200 Subject: [PATCH 11/39] Improved object and subprogram documentation. --- doc/LanguageModel/ObjectDeclarations.rst | 57 ++++++++++++- doc/LanguageModel/SubprogramDefinitions.rst | 92 ++++++++++++++++++++- 2 files changed, 141 insertions(+), 8 deletions(-) diff --git a/doc/LanguageModel/ObjectDeclarations.rst b/doc/LanguageModel/ObjectDeclarations.rst index bbf1583a1..9ec9c52f8 100644 --- a/doc/LanguageModel/ObjectDeclarations.rst +++ b/doc/LanguageModel/ObjectDeclarations.rst @@ -104,6 +104,7 @@ a deferred constant has a reference to the *regular* constant of the same name. @property def SubType(self) -> SubType: + # inherited from WithDefaultExpression @property def ConstantReference(self) -> Constant: @@ -146,9 +147,33 @@ Variables Variable -------- -.. todo:: +A variable represents mutable data in sequential regions. Assignments to +variables have no delay. The initial value can be assigned via a default +expression. + +**Condensed definition of class** :class:`~pyVHDLModel.VHDLModel.Variable`: + +.. code-block:: Python + + @export + class Variable(Object): + # inherited from ModelEntity + @property + def Parent(self) -> 'ModelEntity': + + # inherited from NamedEntity + @property + def Name(self) -> str: + + # inherited from Object + @property + def SubType(self) -> SubType: + + # inherited from WithDefaultExpression + @property + def DefaultExpression(self) -> Expression: + - Write documentation. .. _vhdlmodel-obj-parametervariable: @@ -184,9 +209,33 @@ Signals Signal ------ -.. todo:: +A signal represents mutable data in concurrent regions. Assignments to signals +are delayed until next wait statement is executed. The initial value can be +assigned via a default expression. + +**Condensed definition of class** :class:`~pyVHDLModel.VHDLModel.Signal`: + +.. code-block:: Python + + @export + class Signal(Object): + # inherited from ModelEntity + @property + def Parent(self) -> 'ModelEntity': + + # inherited from NamedEntity + @property + def Name(self) -> str: + + # inherited from Object + @property + def SubType(self) -> SubType: + + # inherited from WithDefaultExpression + @property + def DefaultExpression(self) -> Expression: + - Write documentation. .. _vhdlmodel-obj-portsignal: diff --git a/doc/LanguageModel/SubprogramDefinitions.rst b/doc/LanguageModel/SubprogramDefinitions.rst index a47f70927..4828b9f17 100644 --- a/doc/LanguageModel/SubprogramDefinitions.rst +++ b/doc/LanguageModel/SubprogramDefinitions.rst @@ -5,27 +5,111 @@ Subprogram Declarations .. rubric:: Table of Content -* :ref:`vhdlmodel-procedure` -* :ref:`vhdlmodel-function` +* :ref:`vhdlmodel-procedures` + + * :ref:`vhdlmodel-procedure` + * :ref:`vhdlmodel-procedureinstantiation` + * :ref:`vhdlmodel-proceduremethod` + * :ref:`vhdlmodel-sub-genericprocedure` + +* :ref:`vhdlmodel-functions` + + * :ref:`vhdlmodel-function` + * :ref:`vhdlmodel-functioninstantiation` + * :ref:`vhdlmodel-functionmethod` + * :ref:`vhdlmodel-sub-genericfunction` + + + +.. _vhdlmodel-procedures: + +Procedures +========== + +.. inheritance-diagram:: pyVHDLModel.VHDLModel.Procedure pyVHDLModel.VHDLModel.ProcedureMethod pyVHDLModel.VHDLModel.GenericProcedureInterfaceItem + :parts: 1 .. _vhdlmodel-procedure: Procedure -========= +--------- .. todo:: Write documentation. +.. _vhdlmodel-procedureinstantiation: + +ProcedureInstantiation +---------------------- + + +.. _vhdlmodel-proceduremethod: + +ProcedureMethod +--------------- + + + +.. _vhdlmodel-sub-genericprocedure: + +GenericProcedureInterfaceItem +----------------------------- + +A generic procedure is a *regular* procedure. + +.. seealso:: + + See :ref:`vhdlmodel-genericprocedure` for details. + + + +.. _vhdlmodel-functions: + +Functions +========= + +.. inheritance-diagram:: pyVHDLModel.VHDLModel.Function pyVHDLModel.VHDLModel.FunctionMethod pyVHDLModel.VHDLModel.GenericFunctionInterfaceItem + :parts: 1 + .. _vhdlmodel-function: Function -======== +-------- .. todo:: Write documentation. + + + + +.. _vhdlmodel-functioninstantiation: + +FunctionInstantiation +--------------------- + + + + +.. _vhdlmodel-functionmethod: + +FunctionMethod +-------------- + + + +.. _vhdlmodel-sub-genericfunction: + +GenericFunctionInterfaceItem +---------------------------- + +A generic function is a *regular* function. + +.. seealso:: + + See :ref:`vhdlmodel-genericfunction` for details. From 8daa6cc8917f3a1e7a454ab9b7ee64f1dae68ad7 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Fri, 11 Jun 2021 14:19:35 +0200 Subject: [PATCH 12/39] Improved subprogram documentation. --- doc/LanguageModel/InterfaceItems.rst | 29 +++- doc/LanguageModel/SubprogramDefinitions.rst | 168 +++++++++++++++++++- 2 files changed, 188 insertions(+), 9 deletions(-) diff --git a/doc/LanguageModel/InterfaceItems.rst b/doc/LanguageModel/InterfaceItems.rst index 7c1968838..c4bc85ff4 100644 --- a/doc/LanguageModel/InterfaceItems.rst +++ b/doc/LanguageModel/InterfaceItems.rst @@ -62,21 +62,40 @@ GenericTypeInterfaceItem class GenericTypeInterfaceItem(GenericInterfaceItem): -.. _vhdlmodel-genericsubprogram: +.. _vhdlmodel-genericprocedure: -GenericSubprogramInterfaceItem ------------------------------- +GenericProcedureInterfaceItem +----------------------------- + +.. todo:: + + Write documentation. + +**Condensed definition of class** :class:`~pyVHDLModel.VHDLModel.GenericProcedureInterfaceItem`: + +.. code-block:: Python + + @Export + class GenericProcedureInterfaceItem(GenericSubprogramInterfaceItem): + + + +.. _vhdlmodel-genericfunction: + +GenericFunctionInterfaceItem +---------------------------- .. todo:: Write documentation. -**Condensed definition of class** :class:`~pyVHDLModel.VHDLModel.GenericSubprogramInterfaceItem`: +**Condensed definition of class** :class:`~pyVHDLModel.VHDLModel.GenericFunctionInterfaceItem`: .. code-block:: Python @Export - class GenericSubprogramInterfaceItem(GenericInterfaceItem): + class GenericFunctionInterfaceItem(GenericSubprogramInterfaceItem): + .. _vhdlmodel-genericpackage: diff --git a/doc/LanguageModel/SubprogramDefinitions.rst b/doc/LanguageModel/SubprogramDefinitions.rst index 4828b9f17..17819c1ad 100644 --- a/doc/LanguageModel/SubprogramDefinitions.rst +++ b/doc/LanguageModel/SubprogramDefinitions.rst @@ -36,21 +36,100 @@ Procedures Procedure --------- -.. todo:: +**Condensed definition of class** :class:`~pyVHDLModel.VHDLModel.Procedure`: + +.. code-block:: Python + + @export + class Procedure(SubProgramm): + # inherited from ModelEntity + @property + def Parent(self) -> 'ModelEntity': + + # inherited from NamedEntity + @property + def Name(self) -> str: + + # inherited from Subprogram + def __init__(self, name: str): + + @property + def GenericItems(self) -> List['GenericInterfaceItem']: + + @property + def ParameterItems(self) -> List['ParameterInterfaceItem']: + + @property + def DeclaredItems(self) -> List: + + @property + def BodyItems(self) -> List['SequentialStatement']: + + @property + def IsPure(self) -> bool: + + # from Procedure + _isPure: bool = False + - Write documentation. .. _vhdlmodel-procedureinstantiation: ProcedureInstantiation ---------------------- +.. todo:: + + Write documentation. + + .. _vhdlmodel-proceduremethod: ProcedureMethod --------------- +**Condensed definition of class** :class:`~pyVHDLModel.VHDLModel.ProcedureMethod`: + +.. code-block:: Python + + @export + class ProcedureMethod(SubProgramm): + # inherited from ModelEntity + @property + def Parent(self) -> 'ModelEntity': + + # inherited from NamedEntity + @property + def Name(self) -> str: + + # inherited from Subprogram + def __init__(self, name: str): + + @property + def GenericItems(self) -> List['GenericInterfaceItem']: + + @property + def ParameterItems(self) -> List['ParameterInterfaceItem']: + + @property + def DeclaredItems(self) -> List: + + @property + def BodyItems(self) -> List['SequentialStatement']: + + @property + def IsPure(self) -> bool: + + # inherited from Procedure + _isPure: bool = False + + # inherited from Method + @property + def ProtectedType(self) -> ProtectedType: + + # from ProcedureMethod + def __init__(self, name: str, protectedType: ProtectedType): .. _vhdlmodel-sub-genericprocedure: @@ -81,10 +160,43 @@ Functions Function -------- -.. todo:: +**Condensed definition of class** :class:`~pyVHDLModel.VHDLModel.Function`: - Write documentation. +.. code-block:: Python + + @export + class Function(SubProgramm): + # inherited from ModelEntity + @property + def Parent(self) -> 'ModelEntity': + + # inherited from NamedEntity + @property + def Name(self) -> str: + + # inherited from Subprogram + @property + def GenericItems(self) -> List['GenericInterfaceItem']: + + @property + def ParameterItems(self) -> List['ParameterInterfaceItem']: + + @property + def DeclaredItems(self) -> List: + @property + def BodyItems(self) -> List['SequentialStatement']: + + @property + def IsPure(self) -> bool: + + # from Function + _returnType: SubType + + def __init__(self, name: str, isPure: bool = True): + + @property + def ReturnType(self) -> SubType: @@ -93,6 +205,9 @@ Function FunctionInstantiation --------------------- +.. todo:: + + Write documentation. @@ -101,6 +216,51 @@ FunctionInstantiation FunctionMethod -------------- +**Condensed definition of class** :class:`~pyVHDLModel.VHDLModel.FunctionMethod`: + +.. code-block:: Python + + @export + class Function(SubProgramm): + # inherited from ModelEntity + @property + def Parent(self) -> 'ModelEntity': + + # inherited from NamedEntity + @property + def Name(self) -> str: + + # inherited from Subprogram + @property + def GenericItems(self) -> List['GenericInterfaceItem']: + + @property + def ParameterItems(self) -> List['ParameterInterfaceItem']: + + @property + def DeclaredItems(self) -> List: + + @property + def BodyItems(self) -> List['SequentialStatement']: + + @property + def IsPure(self) -> bool: + + # inherited from Function + _returnType: SubType + + def __init__(self, name: str, isPure: bool = True): + + @property + def ReturnType(self) -> SubType: + + # inherited from Method + @property + def ProtectedType(self) -> ProtectedType: + + # from FunctionMethod + def __init__(self, name: str, protectedType: ProtectedType): + .. _vhdlmodel-sub-genericfunction: From b85e47a22f689f7a8fca42ec29c84263b76a62ff Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Fri, 11 Jun 2021 15:38:00 +0200 Subject: [PATCH 13/39] Improved template --- doc/LanguageModel/SubprogramDefinitions.rst | 11 +---------- doc/_templates/autoapi/module.rst | 1 + doc/_templates/autoapi/script.rst | 1 + 3 files changed, 3 insertions(+), 10 deletions(-) diff --git a/doc/LanguageModel/SubprogramDefinitions.rst b/doc/LanguageModel/SubprogramDefinitions.rst index 17819c1ad..af6a7ab05 100644 --- a/doc/LanguageModel/SubprogramDefinitions.rst +++ b/doc/LanguageModel/SubprogramDefinitions.rst @@ -68,9 +68,6 @@ Procedure @property def IsPure(self) -> bool: - # from Procedure - _isPure: bool = False - .. _vhdlmodel-procedureinstantiation: @@ -121,9 +118,6 @@ ProcedureMethod @property def IsPure(self) -> bool: - # inherited from Procedure - _isPure: bool = False - # inherited from Method @property def ProtectedType(self) -> ProtectedType: @@ -132,6 +126,7 @@ ProcedureMethod def __init__(self, name: str, protectedType: ProtectedType): + .. _vhdlmodel-sub-genericprocedure: GenericProcedureInterfaceItem @@ -191,8 +186,6 @@ Function def IsPure(self) -> bool: # from Function - _returnType: SubType - def __init__(self, name: str, isPure: bool = True): @property @@ -247,8 +240,6 @@ FunctionMethod def IsPure(self) -> bool: # inherited from Function - _returnType: SubType - def __init__(self, name: str, isPure: bool = True): @property diff --git a/doc/_templates/autoapi/module.rst b/doc/_templates/autoapi/module.rst index e359b32af..8ded38ea6 100644 --- a/doc/_templates/autoapi/module.rst +++ b/doc/_templates/autoapi/module.rst @@ -120,6 +120,7 @@ {##} .. rubric:: Inheritance .. inheritance-diagram:: {{ item }} + :parts: 1 {##} .. rubric:: Members {##} diff --git a/doc/_templates/autoapi/script.rst b/doc/_templates/autoapi/script.rst index b10d7c0d0..ab52306a4 100644 --- a/doc/_templates/autoapi/script.rst +++ b/doc/_templates/autoapi/script.rst @@ -124,6 +124,7 @@ {##} .. rubric:: Inheritance .. inheritance-diagram:: {{ item }} + :parts: 1 {##} .. rubric:: Members {##} From 4d6f5554303b3d2f69faeb9845b5e52bcdafad3d Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Fri, 11 Jun 2021 17:13:06 +0200 Subject: [PATCH 14/39] Improved DesignUnit documentation and reworked some class hierarchy. --- doc/LanguageModel/DesignUnits.rst | 75 ++++++++++----- pyVHDLModel/VHDLModel.py | 146 ++++++++++++++++-------------- 2 files changed, 132 insertions(+), 89 deletions(-) diff --git a/doc/LanguageModel/DesignUnits.rst b/doc/LanguageModel/DesignUnits.rst index 9c88c708a..56eff9b40 100644 --- a/doc/LanguageModel/DesignUnits.rst +++ b/doc/LanguageModel/DesignUnits.rst @@ -21,6 +21,11 @@ between *primary* and *secondary* design units. * :ref:`vhdlmodel-packagebody` +.. rubric:: Class Hierarchy + +.. inheritance-diagram:: pyVHDLModel.VHDLModel.Architecture pyVHDLModel.VHDLModel.Context pyVHDLModel.VHDLModel.Configuration pyVHDLModel.VHDLModel.Entity pyVHDLModel.VHDLModel.Package pyVHDLModel.VHDLModel.PackageBody + :parts: 1 + .. _vhdlmodel-primary: Primary Units @@ -53,8 +58,11 @@ Configuration Entity ------ -An ``Entity`` represents a VHDL entity declaration. It has a list of generic and -port items. It can contain a list of declared and body items. +An ``Entity`` represents a VHDL entity declaration. Libraries and package +references declared ahead an entity are consumed by that entity and made +available as lists. An entities also provides lists of generic and port items. +The list of declared items (e.g. objects) also contains defined items (e.g. +types). An entity's list of statements is called body items. **Condensed definition of class** :class:`~pyVHDLModel.VHDLModel.Entity`: @@ -62,13 +70,15 @@ port items. It can contain a list of declared and body items. @export class Entity(PrimaryUnit): - _libraryReferences: List[LibraryReference] - _packageReferences: List[PackageReference] - _genericItems: List[GenericInterfaceItem] - _portItems: List[PortInterfaceItem] - _declaredItems: List # FIXME: define liste element type e.g. via Union - _bodyItems: List['ConcurrentStatement'] + # inherited from ModelEntity + @property + def Parent(self) -> 'ModelEntity': + # inherited from NamedEntity + @property + def Name(self) -> str: + + # from Entity def __init__(self, name: str): @property @@ -77,6 +87,9 @@ port items. It can contain a list of declared and body items. @property def PackageReferences(self) -> List[PackageReference]: + @property + def ContextReferences(self) -> List[ContextReference]: + @property def GenericItems(self) -> List[GenericInterfaceItem]: @@ -106,11 +119,15 @@ Package @export class Package(PrimaryUnit): - _libraryReferences: List[Library] - _packageReferences: List[PackageReference] - _genericItems: List[GenericInterfaceItem] - _declaredItems: List + # inherited from ModelEntity + @property + def Parent(self) -> 'ModelEntity': + # inherited from NamedEntity + @property + def Name(self) -> str: + + # from Package def __init__(self, name: str): @property @@ -119,6 +136,9 @@ Package @property def PackageReferences(self) -> List[PackageReference]: + @property + def ContextReferences(self) -> List[ContextReference]: + @property def GenericItems(self) -> List[GenericInterfaceItem]: @@ -147,12 +167,15 @@ Architeture @export class Architecture(SecondaryUnit): - _entity: Entity - _libraryReferences: List[Library] - _packageReferences: List[PackageReference] - _declaredItems: List # FIXME: define liste element type e.g. via Union - _bodyItems: List['ConcurrentStatement'] + # inherited from ModelEntity + @property + def Parent(self) -> 'ModelEntity': + + # inherited from NamedEntity + @property + def Name(self) -> str: + # from Architecture def __init__(self, name: str): @property @@ -164,6 +187,9 @@ Architeture @property def PackageReferences(self) -> List[PackageReference]: + @property + def ContextReferences(self) -> List[ContextReference]: + @property def DeclaredItems(self) -> List: @@ -187,11 +213,15 @@ Package Body @export class PackageBody(SecondaryUnit): - _package: Package - _libraryReferences: List[Library] - _packageReferences: List[PackageReference] - _declaredItems: List + # inherited from ModelEntity + @property + def Parent(self) -> 'ModelEntity': + + # inherited from NamedEntity + @property + def Name(self) -> str: + # from Package Body def __init__(self, name: str): @property @@ -203,5 +233,8 @@ Package Body @property def PackageReferences(self) -> List[PackageReference]: + @property + def ContextReferences(self) -> List[ContextReference]: + @property def DeclaredItems(self) -> List: diff --git a/pyVHDLModel/VHDLModel.py b/pyVHDLModel/VHDLModel.py index 9639b8723..5595fc780 100644 --- a/pyVHDLModel/VHDLModel.py +++ b/pyVHDLModel/VHDLModel.py @@ -830,17 +830,71 @@ def Item(self) -> str: @export -class PrimaryUnit(ModelEntity, NamedEntity): - def __init__(self, name: str): +class ContextReference(ModelEntity): + _library: Library + _context: 'Context' + + def __init__(self): super().__init__() - NamedEntity.__init__(self, name) + + @property + def Library(self) -> Library: + return self._library + + @property + def Context(self) -> 'Context': + return self._context @export -class SecondaryUnit(ModelEntity, NamedEntity): +class DesignUnit(ModelEntity, NamedEntity): + """ + A ``DesignUnit`` is a base-class for all design units. + """ + def __init__(self, name: str): super().__init__() - NamedEntity.__init__(self, name) + NamedEntity.__init__(self, name)\ + +@export +class DesignUnitWithReferences: + """ + A ``DesignUnitWithReferences`` is a base-class for all design units with contexts. + """ + _libraryReferences: List[LibraryReference] + _packageReferences: List[PackageReference] + _contextReferences: List[ContextReference] + + def __init__(self): + self._libraryReferences = [] + self._packageReferences = [] + self._contextReferences = [] + + @property + def LibraryReferences(self) -> List[Library]: + return self._libraryReferences + + @property + def PackageReferences(self) -> List[PackageReference]: + return self._packageReferences + + @property + def ContextReferences(self) -> List[ContextReference]: + return self._contextReferences + + +@export +class PrimaryUnit(DesignUnit): + """ + A ``PrimaryUnit`` is a base-class for all primary units. + """ + + +@export +class SecondaryUnit(DesignUnit): + """ + A ``SecondaryUnit`` is a base-class for all secondary units. + """ @export @@ -864,32 +918,21 @@ def PackageReferences(self) -> List[PackageReference]: @export -class Entity(PrimaryUnit): - _libraryReferences: List[LibraryReference] - _packageReferences: List[PackageReference] +class Entity(PrimaryUnit, DesignUnitWithReferences): _genericItems: List[GenericInterfaceItem] _portItems: List[PortInterfaceItem] - _declaredItems: List # FIXME: define liste element type e.g. via Union + _declaredItems: List # FIXME: define list element type e.g. via Union _bodyItems: List['ConcurrentStatement'] def __init__(self, name: str): super().__init__(name) + DesignUnitWithReferences.__init__(self) - self._libraryReferences = [] - self._packageReferences = [] self._genericItems = [] self._portItems = [] self._declaredItems = [] self._bodyItems = [] - @property - def LibraryReferences(self) -> List[LibraryReference]: - return self._libraryReferences - - @property - def PackageReferences(self) -> List[PackageReference]: - return self._packageReferences - @property def GenericItems(self) -> List[GenericInterfaceItem]: return self._genericItems @@ -899,7 +942,7 @@ def PortItems(self) -> List[PortInterfaceItem]: return self._portItems @property - def DeclaredItems(self) -> List: # FIXME: define liste element type e.g. via Union + def DeclaredItems(self) -> List: # FIXME: define list element type e.g. via Union return self._declaredItems @property @@ -908,18 +951,15 @@ def BodyItems(self) -> List['ConcurrentStatement']: @export -class Architecture(SecondaryUnit): +class Architecture(SecondaryUnit, DesignUnitWithReferences): _entity: Entity - _libraryReferences: List[Library] - _packageReferences: List[PackageReference] - _declaredItems: List # FIXME: define liste element type e.g. via Union + _declaredItems: List # FIXME: define list element type e.g. via Union _bodyItems: List['ConcurrentStatement'] def __init__(self, name: str): super().__init__(name) + DesignUnitWithReferences.__init__(self) - self._libraryReferences = [] - self._packageReferences = [] self._declaredItems = [] self._bodyItems = [] @@ -928,15 +968,7 @@ def Entity(self) -> Entity: return self._entity @property - def LibraryReferences(self) -> List[Library]: - return self._libraryReferences - - @property - def PackageReferences(self) -> List[PackageReference]: - return self._packageReferences - - @property - def DeclaredItems(self) -> List: # FIXME: define liste element type e.g. via Union + def DeclaredItems(self) -> List: # FIXME: define list element type e.g. via Union return self._declaredItems @property @@ -944,6 +976,13 @@ def BodyItems(self) -> List['ConcurrentStatement']: return self._bodyItems +@export +class Configuration(PrimaryUnit, DesignUnitWithReferences): + def __init__(self, name: str): + super().__init__(name) + DesignUnitWithReferences.__init__(self) + + @export class AssociationItem(ModelEntity): _formal: str # FIXME: defined type @@ -974,13 +1013,6 @@ class ParameterAssociationItem(AssociationItem): pass -@export -class Configuration(ModelEntity, NamedEntity): - def __init__(self, name: str): - super().__init__() - NamedEntity.__init__(self, name) - - @export class Instantiation: pass @@ -1004,28 +1036,17 @@ class FunctionInstantiation(Function, SubprogramInstantiation): @export -class Package(PrimaryUnit): - _libraryReferences: List[Library] - _packageReferences: List[PackageReference] +class Package(PrimaryUnit, DesignUnitWithReferences): _genericItems: List[GenericInterfaceItem] _declaredItems: List def __init__(self, name: str): super().__init__(name) + DesignUnitWithReferences.__init__(self) - self._libraryReferences = [] - self._packageReferences = [] self._genericItems = [] self._declaredItems = [] - @property - def LibraryReferences(self) -> List[Library]: - return self._libraryReferences - - @property - def PackageReferences(self) -> List[PackageReference]: - return self._packageReferences - @property def GenericItems(self) -> List[GenericInterfaceItem]: return self._genericItems @@ -1036,31 +1057,20 @@ def DeclaredItems(self) -> List: @export -class PackageBody(SecondaryUnit): +class PackageBody(SecondaryUnit, DesignUnitWithReferences): _package: Package - _libraryReferences: List[Library] - _packageReferences: List[PackageReference] _declaredItems: List def __init__(self, name: str): super().__init__(name) + DesignUnitWithReferences.__init__(self) - self._libraryReferences = [] - self._packageReferences = [] self._declaredItems = [] @property def Package(self) -> Package: return self._package - @property - def LibraryReferences(self) -> List[Library]: - return self._libraryReferences - - @property - def PackageReferences(self) -> List[PackageReference]: - return self._packageReferences - @property def DeclaredItems(self) -> List: return self._declaredItems From d53989a641718ea4d382b9c5ce52229eb934824a Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Fri, 11 Jun 2021 17:21:00 +0200 Subject: [PATCH 15/39] Adjusted to DesignUnitWithReferences. --- doc/LanguageModel/DesignUnits.rst | 48 +++++++++++++++++-------------- 1 file changed, 26 insertions(+), 22 deletions(-) diff --git a/doc/LanguageModel/DesignUnits.rst b/doc/LanguageModel/DesignUnits.rst index 56eff9b40..d87ce47f8 100644 --- a/doc/LanguageModel/DesignUnits.rst +++ b/doc/LanguageModel/DesignUnits.rst @@ -69,7 +69,7 @@ types). An entity's list of statements is called body items. .. code-block:: Python @export - class Entity(PrimaryUnit): + class Entity(PrimaryUnit, DesignUnitWithReferences): # inherited from ModelEntity @property def Parent(self) -> 'ModelEntity': @@ -78,9 +78,7 @@ types). An entity's list of statements is called body items. @property def Name(self) -> str: - # from Entity - def __init__(self, name: str): - + # inherited from DesignUnitWithReferences @property def LibraryReferences(self) -> List[LibraryReference]: @@ -90,6 +88,9 @@ types). An entity's list of statements is called body items. @property def ContextReferences(self) -> List[ContextReference]: + # from Entity + def __init__(self, name: str): + @property def GenericItems(self) -> List[GenericInterfaceItem]: @@ -127,11 +128,9 @@ Package @property def Name(self) -> str: - # from Package - def __init__(self, name: str): - + # inherited from DesignUnitWithReferences @property - def LibraryReferences(self) -> List[Library]: + def LibraryReferences(self) -> List[LibraryReference]: @property def PackageReferences(self) -> List[PackageReference]: @@ -139,6 +138,9 @@ Package @property def ContextReferences(self) -> List[ContextReference]: + # from Package + def __init__(self, name: str): + @property def GenericItems(self) -> List[GenericInterfaceItem]: @@ -175,14 +177,9 @@ Architeture @property def Name(self) -> str: - # from Architecture - def __init__(self, name: str): - + # inherited from DesignUnitWithReferences @property - def Entity(self) -> Entity: - - @property - def LibraryReferences(self) -> List[Library]: + def LibraryReferences(self) -> List[LibraryReference]: @property def PackageReferences(self) -> List[PackageReference]: @@ -190,6 +187,12 @@ Architeture @property def ContextReferences(self) -> List[ContextReference]: + # from Architecture + def __init__(self, name: str): + + @property + def Entity(self) -> Entity: + @property def DeclaredItems(self) -> List: @@ -221,14 +224,9 @@ Package Body @property def Name(self) -> str: - # from Package Body - def __init__(self, name: str): - + # inherited from DesignUnitWithReferences @property - def Package(self) -> Package: - - @property - def LibraryReferences(self) -> List[Library]: + def LibraryReferences(self) -> List[LibraryReference]: @property def PackageReferences(self) -> List[PackageReference]: @@ -236,5 +234,11 @@ Package Body @property def ContextReferences(self) -> List[ContextReference]: + # from Package Body + def __init__(self, name: str): + + @property + def Package(self) -> Package: + @property def DeclaredItems(self) -> List: From 8cfeb9dbf42a993d6f7a6075b8e7afd5e8ab1d89 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Fri, 11 Jun 2021 17:24:48 +0200 Subject: [PATCH 16/39] Renamed 'DesignUnitWithReferences' to 'DesignUnitWithContext'. --- doc/LanguageModel/DesignUnits.rst | 16 ++++++++-------- pyVHDLModel/VHDLModel.py | 22 +++++++++++----------- 2 files changed, 19 insertions(+), 19 deletions(-) diff --git a/doc/LanguageModel/DesignUnits.rst b/doc/LanguageModel/DesignUnits.rst index d87ce47f8..975fa8962 100644 --- a/doc/LanguageModel/DesignUnits.rst +++ b/doc/LanguageModel/DesignUnits.rst @@ -69,7 +69,7 @@ types). An entity's list of statements is called body items. .. code-block:: Python @export - class Entity(PrimaryUnit, DesignUnitWithReferences): + class Entity(PrimaryUnit, DesignUnitWithContext): # inherited from ModelEntity @property def Parent(self) -> 'ModelEntity': @@ -78,7 +78,7 @@ types). An entity's list of statements is called body items. @property def Name(self) -> str: - # inherited from DesignUnitWithReferences + # inherited from DesignUnitWithContext @property def LibraryReferences(self) -> List[LibraryReference]: @@ -119,7 +119,7 @@ Package .. code-block:: Python @export - class Package(PrimaryUnit): + class Package(PrimaryUnit, DesignUnitWithContext): # inherited from ModelEntity @property def Parent(self) -> 'ModelEntity': @@ -128,7 +128,7 @@ Package @property def Name(self) -> str: - # inherited from DesignUnitWithReferences + # inherited from DesignUnitWithContext @property def LibraryReferences(self) -> List[LibraryReference]: @@ -168,7 +168,7 @@ Architeture .. code-block:: Python @export - class Architecture(SecondaryUnit): + class Architecture(SecondaryUnit, DesignUnitWithContext): # inherited from ModelEntity @property def Parent(self) -> 'ModelEntity': @@ -177,7 +177,7 @@ Architeture @property def Name(self) -> str: - # inherited from DesignUnitWithReferences + # inherited from DesignUnitWithContext @property def LibraryReferences(self) -> List[LibraryReference]: @@ -215,7 +215,7 @@ Package Body .. code-block:: Python @export - class PackageBody(SecondaryUnit): + class PackageBody(SecondaryUnit, DesignUnitWithContext): # inherited from ModelEntity @property def Parent(self) -> 'ModelEntity': @@ -224,7 +224,7 @@ Package Body @property def Name(self) -> str: - # inherited from DesignUnitWithReferences + # inherited from DesignUnitWithContext @property def LibraryReferences(self) -> List[LibraryReference]: diff --git a/pyVHDLModel/VHDLModel.py b/pyVHDLModel/VHDLModel.py index 5595fc780..acf1eec24 100644 --- a/pyVHDLModel/VHDLModel.py +++ b/pyVHDLModel/VHDLModel.py @@ -857,7 +857,7 @@ def __init__(self, name: str): NamedEntity.__init__(self, name)\ @export -class DesignUnitWithReferences: +class DesignUnitWithContext: """ A ``DesignUnitWithReferences`` is a base-class for all design units with contexts. """ @@ -918,7 +918,7 @@ def PackageReferences(self) -> List[PackageReference]: @export -class Entity(PrimaryUnit, DesignUnitWithReferences): +class Entity(PrimaryUnit, DesignUnitWithContext): _genericItems: List[GenericInterfaceItem] _portItems: List[PortInterfaceItem] _declaredItems: List # FIXME: define list element type e.g. via Union @@ -926,7 +926,7 @@ class Entity(PrimaryUnit, DesignUnitWithReferences): def __init__(self, name: str): super().__init__(name) - DesignUnitWithReferences.__init__(self) + DesignUnitWithContext.__init__(self) self._genericItems = [] self._portItems = [] @@ -951,14 +951,14 @@ def BodyItems(self) -> List['ConcurrentStatement']: @export -class Architecture(SecondaryUnit, DesignUnitWithReferences): +class Architecture(SecondaryUnit, DesignUnitWithContext): _entity: Entity _declaredItems: List # FIXME: define list element type e.g. via Union _bodyItems: List['ConcurrentStatement'] def __init__(self, name: str): super().__init__(name) - DesignUnitWithReferences.__init__(self) + DesignUnitWithContext.__init__(self) self._declaredItems = [] self._bodyItems = [] @@ -977,10 +977,10 @@ def BodyItems(self) -> List['ConcurrentStatement']: @export -class Configuration(PrimaryUnit, DesignUnitWithReferences): +class Configuration(PrimaryUnit, DesignUnitWithContext): def __init__(self, name: str): super().__init__(name) - DesignUnitWithReferences.__init__(self) + DesignUnitWithContext.__init__(self) @export @@ -1036,13 +1036,13 @@ class FunctionInstantiation(Function, SubprogramInstantiation): @export -class Package(PrimaryUnit, DesignUnitWithReferences): +class Package(PrimaryUnit, DesignUnitWithContext): _genericItems: List[GenericInterfaceItem] _declaredItems: List def __init__(self, name: str): super().__init__(name) - DesignUnitWithReferences.__init__(self) + DesignUnitWithContext.__init__(self) self._genericItems = [] self._declaredItems = [] @@ -1057,13 +1057,13 @@ def DeclaredItems(self) -> List: @export -class PackageBody(SecondaryUnit, DesignUnitWithReferences): +class PackageBody(SecondaryUnit, DesignUnitWithContext): _package: Package _declaredItems: List def __init__(self, name: str): super().__init__(name) - DesignUnitWithReferences.__init__(self) + DesignUnitWithContext.__init__(self) self._declaredItems = [] From f6e984bcc40230446bd562dbad68e13dc7fc03d3 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Fri, 11 Jun 2021 17:46:04 +0200 Subject: [PATCH 17/39] Partially documented interface items. --- doc/LanguageModel/InterfaceItems.rst | 158 +++++++++++++++++++++++---- 1 file changed, 134 insertions(+), 24 deletions(-) diff --git a/doc/LanguageModel/InterfaceItems.rst b/doc/LanguageModel/InterfaceItems.rst index c4bc85ff4..de7cd60d8 100644 --- a/doc/LanguageModel/InterfaceItems.rst +++ b/doc/LanguageModel/InterfaceItems.rst @@ -5,28 +5,37 @@ Interface Items Interface items are used in generic, port and parameter declarations. -* :class:`~pyVHDLModel.VHDLModel.GenericInterfaceItem` +.. rubric:: Table of Content - * :class:`~pyVHDLModel.VHDLModel.GenericConstantInterfaceItem` - * :class:`~pyVHDLModel.VHDLModel.GenericTypeInterfaceItem` - * :class:`~pyVHDLModel.VHDLModel.GenericSubprogramInterfaceItem` - * :class:`~pyVHDLModel.VHDLModel.GenericPackageInterfaceItem` +* :ref:`vhdlmodel-generics` -* :class:`~pyVHDLModel.VHDLModel.PortInterfaceItem` + * :ref:`vhdlmodel-genericconstant` + * :ref:`vhdlmodel-generictype` + * :ref:`vhdlmodel-genericprocedure` + * :ref:`vhdlmodel-genericfunction` + * :ref:`vhdlmodel-genericpackage` - * :class:`~pyVHDLModel.VHDLModel.PortSignalInterfaceItem` +* :ref:`vhdlmodel-ports` -* :class:`~pyVHDLModel.VHDLModel.ParameterInterfaceItem` + * :ref:`vhdlmodel-portsignal` + +* :ref:`vhdlmodel-parameters` + + * :ref:`vhdlmodel-parameterconstant` + * :ref:`vhdlmodel-parametervariable` + * :ref:`vhdlmodel-parametersignal` + * :ref:`vhdlmodel-parameterfile` + +.. rubric:: Class Hierarchy + +.. inheritance-diagram:: pyVHDLModel.VHDLModel.GenericConstantInterfaceItem pyVHDLModel.VHDLModel.GenericTypeInterfaceItem pyVHDLModel.VHDLModel.GenericProcedureInterfaceItem pyVHDLModel.VHDLModel.GenericFunctionInterfaceItem pyVHDLModel.VHDLModel.PortSignalInterfaceItem pyVHDLModel.VHDLModel.ParameterConstantInterfaceItem pyVHDLModel.VHDLModel.ParameterVariableInterfaceItem pyVHDLModel.VHDLModel.ParameterSignalInterfaceItem pyVHDLModel.VHDLModel.ParameterFileInterfaceItem + :parts: 1 - * :class:`~pyVHDLModel.VHDLModel.ParameterConstantInterfaceItem` - * :class:`~pyVHDLModel.VHDLModel.ParameterVariableInterfaceItem` - * :class:`~pyVHDLModel.VHDLModel.ParameterSignalInterfaceItem` - * :class:`~pyVHDLModel.VHDLModel.ParameterFileInterfaceItem` .. _vhdlmodel-generics: -Generic Interface Item -====================== +Generic Interface Items +======================= .. _vhdlmodel-genericconstant: @@ -41,8 +50,28 @@ GenericConstantInterfaceItem .. code-block:: Python - @Export - class GenericConstantInterfaceItem(GenericInterfaceItem): + @export + class GenericConstantInterfaceItem(Constant, GenericInterfaceItem): + # inherited from ModelEntity + @property + def Parent(self) -> 'ModelEntity': + + # inherited from NamedEntity + @property + def Name(self) -> str: + + # inherited from Object + @property + def SubType(self) -> SubType: + + # inherited from WithDefaultExpression + @property + def DefaultExpression(self) -> Expression: + + # inherited from InterfaceItem + @property + def Mode(self) -> Mode: + .. _vhdlmodel-generictype: @@ -133,8 +162,29 @@ PortSignalInterfaceItem .. code-block:: Python - @Export - class PortSignalInterfaceItem(PortInterfaceItem): + @export + class PortSignalInterfaceItem(Signal, PortInterfaceItem): + # inherited from ModelEntity + @property + def Parent(self) -> 'ModelEntity': + + # inherited from NamedEntity + @property + def Name(self) -> str: + + # inherited from Object + @property + def SubType(self) -> SubType: + + # inherited from WithDefaultExpression + @property + def DefaultExpression(self) -> Expression: + + # inherited from InterfaceItem + @property + def Mode(self) -> Mode: + + .. _vhdlmodel-parameters: @@ -154,8 +204,28 @@ ParameterConstantInterfaceItem .. code-block:: Python - @Export - class ParameterConstantInterfaceItem(ParameterInterfaceItem): + @export + class ParameterConstantInterfaceItem(Constant, ParameterInterfaceItem): + # inherited from ModelEntity + @property + def Parent(self) -> 'ModelEntity': + + # inherited from NamedEntity + @property + def Name(self) -> str: + + # inherited from Object + @property + def SubType(self) -> SubType: + + # inherited from WithDefaultExpression + @property + def DefaultExpression(self) -> Expression: + + # inherited from InterfaceItem + @property + def Mode(self) -> Mode: + .. _vhdlmodel-parametervariable: @@ -171,8 +241,28 @@ ParameterVariableInterfaceItem .. code-block:: Python - @Export - class ParameterVariableInterfaceItem(ParameterInterfaceItem): + @export + class ParameterVariableInterfaceItem(Variable, ParameterInterfaceItem): + # inherited from ModelEntity + @property + def Parent(self) -> 'ModelEntity': + + # inherited from NamedEntity + @property + def Name(self) -> str: + + # inherited from Object + @property + def SubType(self) -> SubType: + + # inherited from WithDefaultExpression + @property + def DefaultExpression(self) -> Expression: + + # inherited from InterfaceItem + @property + def Mode(self) -> Mode: + .. _vhdlmodel-parametersignal: @@ -188,8 +278,28 @@ ParameterSignalInterfaceItem .. code-block:: Python - @Export - class ParameterSignalInterfaceItem(ParameterInterfaceItem): + @export + class ParameterSignalInterfaceItem(Signal, ParameterInterfaceItem): + # inherited from ModelEntity + @property + def Parent(self) -> 'ModelEntity': + + # inherited from NamedEntity + @property + def Name(self) -> str: + + # inherited from Object + @property + def SubType(self) -> SubType: + + # inherited from WithDefaultExpression + @property + def DefaultExpression(self) -> Expression: + + # inherited from InterfaceItem + @property + def Mode(self) -> Mode: + .. _vhdlmodel-parameterfile: From 41c5d58b189d47bfd028fb6139177b71e43094cc Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Fri, 11 Jun 2021 18:03:57 +0200 Subject: [PATCH 18/39] Documenting types --- doc/LanguageModel/TypeDefinitions.rst | 90 ++++++++++++++++++++++++--- pyVHDLModel/VHDLModel.py | 10 ++- 2 files changed, 89 insertions(+), 11 deletions(-) diff --git a/doc/LanguageModel/TypeDefinitions.rst b/doc/LanguageModel/TypeDefinitions.rst index 63ca55991..8fd548569 100644 --- a/doc/LanguageModel/TypeDefinitions.rst +++ b/doc/LanguageModel/TypeDefinitions.rst @@ -21,13 +21,16 @@ VHDL has types (also called a base type) and subtypes. The following shows VHDL' * :ref:`vhdlmodel-arraytypes` * :ref:`vhdlmodel-recordtypes` + * :ref:`vhdlmodel-protectedtypes` * :ref:`vhdlmodel-accesstypes` * :ref:`vhdlmodel-filetypes` - * :ref:`vhdlmodel-protectedtypes` * Subtype +.. rubric:: Class Hierarchy +.. inheritance-diagram:: pyVHDLModel.VHDLModel.EnumeratedType pyVHDLModel.VHDLModel.IntegerType pyVHDLModel.VHDLModel.RealType pyVHDLModel.VHDLModel.PhysicalType pyVHDLModel.VHDLModel.ArrayType pyVHDLModel.VHDLModel.RecordType pyVHDLModel.VHDLModel.ProtectedType pyVHDLModel.VHDLModel.AccessType pyVHDLModel.VHDLModel.FileType + :parts: 1 .. _vhdlmodel-scalartypes: @@ -44,6 +47,26 @@ Enumeration Write documentation. +**Condensed definition of class** :class:`~pyVHDLModel.VHDLModel.EnumeratedType`: + +.. code-block:: Python + + @export + class EnumeratedType(ScalarType, DiscreteType): + # inherited from ModelEntity + @property + def Parent(self) -> 'ModelEntity': + + # inherited from NamedEntity + @property + def Name(self) -> str: + + # from EnumeratedType + @property + def Elements(self) -> List: + + + .. _vhdlmodel-integertypes: Integer @@ -53,6 +76,21 @@ Integer Write documentation. +**Condensed definition of class** :class:`~pyVHDLModel.VHDLModel.IntegerType`: + +.. code-block:: Python + + @export + class IntegerType(ScalarType, NumericType, DiscreteType): + # inherited from ModelEntity + @property + def Parent(self) -> 'ModelEntity': + + # inherited from NamedEntity + @property + def Name(self) -> str: + + .. _vhdlmodel-realtypes: @@ -63,6 +101,22 @@ Real Write documentation. +**Condensed definition of class** :class:`~pyVHDLModel.VHDLModel.RealType`: + +.. code-block:: Python + + @export + class RealType(ScalarType, NumericType): + # inherited from ModelEntity + @property + def Parent(self) -> 'ModelEntity': + + # inherited from NamedEntity + @property + def Name(self) -> str: + + + .. _vhdlmodel-physicaltypes: Physical @@ -72,6 +126,22 @@ Physical Write documentation. +**Condensed definition of class** :class:`~pyVHDLModel.VHDLModel.PhysicalType`: + +.. code-block:: Python + + @export + class PhysicalType(ScalarType, NumericType): + # inherited from ModelEntity + @property + def Parent(self) -> 'ModelEntity': + + # inherited from NamedEntity + @property + def Name(self) -> str: + + + .. _vhdlmodel-compositetypes: Composite Types @@ -95,28 +165,28 @@ Record Write documentation. -.. _vhdlmodel-accesstypes: +.. _vhdlmodel-protectedtypes: -Access -====== +Protected +========= .. todo:: Write documentation. -.. _vhdlmodel-filetypes: +.. _vhdlmodel-accesstypes: -File -==== +Access +====== .. todo:: Write documentation. -.. _vhdlmodel-protectedtypes: +.. _vhdlmodel-filetypes: -Protected -========= +File +==== .. todo:: diff --git a/pyVHDLModel/VHDLModel.py b/pyVHDLModel/VHDLModel.py index acf1eec24..4b43c86ed 100644 --- a/pyVHDLModel/VHDLModel.py +++ b/pyVHDLModel/VHDLModel.py @@ -396,7 +396,15 @@ class RealType(ScalarType, NumericType): def __init__(self, name: str): super().__init__(name) -# TODO: PhysicalType + +@export +class PhysicalType(ScalarType, NumericType): + _leftBound: 'Expression' + _rightBound: 'Expression' + + def __init__(self, name: str): + super().__init__(name) + @export class ArrayType(CompositeType): From 57ce42b879025ce528baccf7efedecd96d3e96d8 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Fri, 11 Jun 2021 18:16:09 +0200 Subject: [PATCH 19/39] Added RangedScalarType --- doc/LanguageModel/TypeDefinitions.rst | 34 +++++++++++++++-- pyVHDLModel/VHDLModel.py | 54 ++++++++++++++++++++------- 2 files changed, 71 insertions(+), 17 deletions(-) diff --git a/doc/LanguageModel/TypeDefinitions.rst b/doc/LanguageModel/TypeDefinitions.rst index 8fd548569..64db85274 100644 --- a/doc/LanguageModel/TypeDefinitions.rst +++ b/doc/LanguageModel/TypeDefinitions.rst @@ -81,7 +81,7 @@ Integer .. code-block:: Python @export - class IntegerType(ScalarType, NumericType, DiscreteType): + class IntegerType(RangedScalarType, NumericType, DiscreteType): # inherited from ModelEntity @property def Parent(self) -> 'ModelEntity': @@ -90,6 +90,13 @@ Integer @property def Name(self) -> str: + # inherited from RangedScalarType + @property + def LeftBound(self) -> 'Expression': + + @property + def RightBound(self) -> 'Expression': + .. _vhdlmodel-realtypes: @@ -106,7 +113,7 @@ Real .. code-block:: Python @export - class RealType(ScalarType, NumericType): + class RealType(RangedScalarType, NumericType): # inherited from ModelEntity @property def Parent(self) -> 'ModelEntity': @@ -115,6 +122,13 @@ Real @property def Name(self) -> str: + # inherited from RangedScalarType + @property + def LeftBound(self) -> 'Expression': + + @property + def RightBound(self) -> 'Expression': + .. _vhdlmodel-physicaltypes: @@ -131,7 +145,7 @@ Physical .. code-block:: Python @export - class PhysicalType(ScalarType, NumericType): + class PhysicalType(RangedScalarType, NumericType): # inherited from ModelEntity @property def Parent(self) -> 'ModelEntity': @@ -140,6 +154,20 @@ Physical @property def Name(self) -> str: + # inherited from RangedScalarType + @property + def LeftBound(self) -> 'Expression': + + @property + def RightBound(self) -> 'Expression': + + # from PhysicalType + @property + def PrimaryUnit(self) -> str: + + @property + def SecondaryUnits(self) -> List[Tuple[int, str]]: + .. _vhdlmodel-compositetypes: diff --git a/pyVHDLModel/VHDLModel.py b/pyVHDLModel/VHDLModel.py index 4b43c86ed..a9df8a9d5 100644 --- a/pyVHDLModel/VHDLModel.py +++ b/pyVHDLModel/VHDLModel.py @@ -43,7 +43,7 @@ # load dependencies from enum import Enum from pathlib import Path -from typing import Any, List +from typing import Any, List, Tuple from pydecor.decorators import export @@ -328,7 +328,27 @@ def ResolutionFunction(self) -> 'Function': @export class ScalarType(BaseType): - pass + """ + A ``ScalarType`` is a base-class for all scalar types. + """ + + +@export +class RangedScalarType(ScalarType): + """ + A ``RangedScalarType`` is a base-class for all scalar types with a range. + """ + + _leftBound: 'Expression' + _rightBound: 'Expression' + + @property + def LeftBound(self) -> 'Expression': + return self._leftBound + + @property + def RightBound(self) -> 'Expression': + return self._rightBound @export @@ -347,7 +367,9 @@ class DiscreteType: @export class CompositeType(BaseType): - pass + """ + A ``CompositeType`` is a base-class for all composite types. + """ @export @@ -380,31 +402,35 @@ def Elements(self) -> List: @export -class IntegerType(ScalarType, NumericType, DiscreteType): - _leftBound: 'Expression' - _rightBound: 'Expression' - +class IntegerType(RangedScalarType, NumericType, DiscreteType): def __init__(self, name: str): super().__init__(name) @export -class RealType(ScalarType, NumericType): - _leftBound: 'Expression' - _rightBound: 'Expression' - +class RealType(RangedScalarType, NumericType): def __init__(self, name: str): super().__init__(name) @export -class PhysicalType(ScalarType, NumericType): - _leftBound: 'Expression' - _rightBound: 'Expression' +class PhysicalType(RangedScalarType, NumericType): + _primaryUnit: str + _secondaryUnits: List[Tuple[int, str]] def __init__(self, name: str): super().__init__(name) + self._secondaryUnits = [] + + @property + def PrimaryUnit(self) -> str: + return self._primaryUnit + + @property + def SecondaryUnits(self) -> List[Tuple[int, str]]: + return self._secondaryUnits + @export class ArrayType(CompositeType): From 7bc0a9e7e3c49799245526a3dad6de0bf5ab1d51 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Fri, 11 Jun 2021 18:25:37 +0200 Subject: [PATCH 20/39] Added composite types. --- doc/LanguageModel/TypeDefinitions.rst | 44 ++++++++++++++++++++++++++- pyVHDLModel/VHDLModel.py | 15 +++++---- 2 files changed, 52 insertions(+), 7 deletions(-) diff --git a/doc/LanguageModel/TypeDefinitions.rst b/doc/LanguageModel/TypeDefinitions.rst index 64db85274..28f0870ab 100644 --- a/doc/LanguageModel/TypeDefinitions.rst +++ b/doc/LanguageModel/TypeDefinitions.rst @@ -63,7 +63,7 @@ Enumeration # from EnumeratedType @property - def Elements(self) -> List: + def Elements(self) -> List[str]: @@ -184,6 +184,29 @@ Array Write documentation. +**Condensed definition of class** :class:`~pyVHDLModel.VHDLModel.ArrayType`: + +.. code-block:: Python + + @export + class ArrayType(CompositeType): + # inherited from ModelEntity + @property + def Parent(self) -> 'ModelEntity': + + # inherited from NamedEntity + @property + def Name(self) -> str: + + # from ArrayType + @property + def Dimensions(self) -> List['Range']: + + @property + def ElementType(self) -> SubType: + + + .. _vhdlmodel-recordtypes: Record @@ -193,6 +216,25 @@ Record Write documentation. +**Condensed definition of class** :class:`~pyVHDLModel.VHDLModel.RecordType`: + +.. code-block:: Python + + @export + class RecordType(CompositeType): + # inherited from ModelEntity + @property + def Parent(self) -> 'ModelEntity': + + # inherited from NamedEntity + @property + def Name(self) -> str: + + # from RecordType + @property + def Members(self) -> List[RecordTypeMember]: + + .. _vhdlmodel-protectedtypes: Protected diff --git a/pyVHDLModel/VHDLModel.py b/pyVHDLModel/VHDLModel.py index a9df8a9d5..b917f969a 100644 --- a/pyVHDLModel/VHDLModel.py +++ b/pyVHDLModel/VHDLModel.py @@ -389,7 +389,7 @@ class FileType(BaseType): @export class EnumeratedType(ScalarType, DiscreteType): - _elements: List + _elements: List[str] def __init__(self, name: str): super().__init__(name) @@ -397,7 +397,7 @@ def __init__(self, name: str): self._elements = [] @property - def Elements(self) -> List: + def Elements(self) -> List[str]: return self._elements @@ -443,16 +443,19 @@ def __init__(self, name: str): self._dimensions = [] @property - def Dimensions(self): + def Dimensions(self) -> List['Range']: return self._dimensions @property - def ElementType(self): + def ElementType(self) -> SubType: return self._elementType @export class RecordTypeMember(ModelEntity): + _name: str + _subType: SubType + def __init__(self, name: str): super().__init__() @@ -460,7 +463,7 @@ def __init__(self, name: str): self._subType = None @property - def Name(self): + def Name(self) -> str: return self._name @@ -474,7 +477,7 @@ def __init__(self, name: str): self._members = [] @property - def Members(self): + def Members(self) -> List[RecordTypeMember]: return self._members From 34ddbece1b2450dce751122e8648195d8f2ce412 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Fri, 11 Jun 2021 19:22:35 +0200 Subject: [PATCH 21/39] Added more expressions (unary, adding, multiplying). --- doc/LanguageModel/Expressions.rst | 109 +++++++++++++++++++ doc/LanguageModel/index.rst | 1 + pyVHDLModel/VHDLModel.py | 175 ++++++++++++++++++++++++++---- 3 files changed, 266 insertions(+), 19 deletions(-) create mode 100644 doc/LanguageModel/Expressions.rst diff --git a/doc/LanguageModel/Expressions.rst b/doc/LanguageModel/Expressions.rst new file mode 100644 index 000000000..3c8b30f7a --- /dev/null +++ b/doc/LanguageModel/Expressions.rst @@ -0,0 +1,109 @@ +.. _vhdlmodel-expr: + +Literals and Expressions +######################## + + + +.. rubric:: Table of Content + +* :ref:`vhdlmodel-literals` + + * :ref:`vhdlmodel-enumerationliteral` + * :ref:`vhdlmodel-integerliteral` + * :ref:`vhdlmodel-realliteral` + * :ref:`vhdlmodel-physicalliteral` + +* :ref:`vhdlmodel-expressions` + + * :ref:`vhdlmodel-unary` + * :ref:`vhdlmodel-binary` + * :ref:`vhdlmodel-ternary` + + +.. rubric:: Class Hierarchy + +.. inheritance-diagram:: pyVHDLModel.VHDLModel.EnumerationLiteral pyVHDLModel.VHDLModel.IntegerLiteral pyVHDLModel.VHDLModel.FloatingPointLiteral pyVHDLModel.VHDLModel.PhysicalLiteral pyVHDLModel.VHDLModel.CharacterLiteral pyVHDLModel.VHDLModel.StringLiteral pyVHDLModel.VHDLModel.BitStringLiteral + :parts: 1 + +.. _vhdlmodel-literals: + +Literals +======== + +.. _vhdlmodel-enumerationliteral: + +Enumeration Literal +------------------- + +.. todo:: + + Write documentation. + + + +.. _vhdlmodel-integerliteral: + +Integer Literal +--------------- + +.. todo:: + + Write documentation. + + + +.. _vhdlmodel-realliteral: + +Floating Point Literal +---------------------- + +.. todo:: + + Write documentation. + + + +.. _vhdlmodel-physicalliteral: + +Physical Literal +---------------- + +.. todo:: + + Write documentation. + + + +.. _vhdlmodel-expressions: + +Expressions +=========== + +.. rubric:: Class Hierarchy + +.. inheritance-diagram:: pyVHDLModel.VHDLModel.UnaryExpression pyVHDLModel.VHDLModel.BinaryExpression pyVHDLModel.VHDLModel.TernaryExpression + :parts: 1 + +.. _vhdlmodel-unary: + +Unary Expressions +----------------- + +.. rubric:: Class Hierarchy + +.. inheritance-diagram:: pyVHDLModel.VHDLModel.InverseExpression pyVHDLModel.VHDLModel.IdentityExpression pyVHDLModel.VHDLModel.NegationExpression pyVHDLModel.VHDLModel.AbsoluteExpression pyVHDLModel.VHDLModel.TypeConversion pyVHDLModel.VHDLModel.FunctionCall pyVHDLModel.VHDLModel.QualifiedExpression + :parts: 1 + + +.. _vhdlmodel-binary: + +Binary Expressions +------------------ + + + +.. _vhdlmodel-ternary: + +Ternary Expressions +------------------- diff --git a/doc/LanguageModel/index.rst b/doc/LanguageModel/index.rst index c93e99c3c..9efe8c5c4 100644 --- a/doc/LanguageModel/index.rst +++ b/doc/LanguageModel/index.rst @@ -27,3 +27,4 @@ VHDL Language Model ObjectDeclarations ConcurrentStatements SequentialStatements + Expressions diff --git a/pyVHDLModel/VHDLModel.py b/pyVHDLModel/VHDLModel.py index b917f969a..783a83169 100644 --- a/pyVHDLModel/VHDLModel.py +++ b/pyVHDLModel/VHDLModel.py @@ -482,46 +482,83 @@ def Members(self) -> List[RecordTypeMember]: @export -class Expression: - pass +class Expression(ModelEntity): + """ + A ``Expression`` is a base-class for all expressions. + """ @export -class Literal: - pass +class Literal(Expression): + """ + A ``Literal`` is a base-class for all literals. + """ +# TODO: add a reference to a basetype ? + +@export +class EnumerationLiteral(Literal): + _value: str + + def __init__(self, value: str): + self._value = value + + @property + def Value(self) -> str: + return self._value @export -class IntegerLiteral(Literal): +class NumericLiteral(Literal): + """ + A ``NumericLiteral`` is a base-class for all numeric literals. + """ + + +@export +class IntegerLiteral(NumericLiteral): _value: int def __init__(self, value: int): self._value = value @property - def Value(self): + def Value(self) -> int: return self._value @export -class FloatingPointLiteral(Literal): +class FloatingPointLiteral(NumericLiteral): _value: float def __init__(self, value: float): self._value = value @property - def Value(self): + def Value(self) -> float: return self._value -# CharacterLiteral -# StringLiteral -# BitStringLiteral -# EnumerationLiteral -# PhysicalLiteral +@export +class PhysicalLiteral(NumericLiteral): + pass + +@export +class CharacterLiteral(Literal): + pass + +@export +class StringLiteral(Literal): + pass + +@export +class BitStringLiteral(Literal): + pass + @export class UnaryExpression(Expression): + """ + A ``UnaryExpression`` is a base-class for all unary expressions. + """ _operand: Expression def __init__(self): @@ -532,15 +569,39 @@ def Operand(self): return self._operand @export -class FunctionCall(Expression): +class InverseExpression(UnaryExpression): + pass + +@export +class IdentityExpression(UnaryExpression): + pass + +@export +class NegationExpression(UnaryExpression): + pass + +@export +class AbsoluteExpression(UnaryExpression): pass @export -class QualifiedExpression(Expression): +class TypeConversion(UnaryExpression): + pass + +@export +class FunctionCall(UnaryExpression): + pass + +@export +class QualifiedExpression(UnaryExpression): pass @export class BinaryExpression(Expression): + """ + A ``BinaryExpression`` is a base-class for all binary expressions. + """ + _leftOperand: Expression _rightOperand: Expression @@ -555,10 +616,86 @@ def LeftOperand(self): def RightOperand(self): return self._rightOperand -# AddingExpression -# MultiplyingExpression -# LogicalExpression -# ShiftExpression + +@export +class AddingExpression(BinaryExpression): + """ + A ``AddingExpression`` is a base-class for all adding expressions. + """ + +@export +class AdditionExpression(AddingExpression): + pass + +@export +class SubtractionExpression(AddingExpression): + pass + +@export +class MultiplyingExpression(BinaryExpression): + """ + A ``MultiplyingExpression`` is a base-class for all multiplying expressions. + """ + +@export +class MultiplyExpression(MultiplyingExpression): + pass + +@export +class DivisionExpression(MultiplyingExpression): + pass + +@export +class RemainderExpression(MultiplyingExpression): + pass + +@export +class ModuloExpression(MultiplyingExpression): + pass + +@export +class ExponentationExpression(MultiplyingExpression): + pass + +@export +class LogicalExpression(BinaryExpression): + """ + A ``LogicalExpression`` is a base-class for all logical expressions. + """ + + +@export +class ShiftExpression(BinaryExpression): + """ + A ``ShiftExpression`` is a base-class for all shifting expressions. + """ + + +@export +class TernaryExpression(Expression): + """ + A ``TernaryExpression`` is a base-class for all ternary expressions. + """ + + _firstOperand: Expression + _secondOperand: Expression + _thirdOperand: Expression + + def __init__(self): + pass + + @property + def FirstOperand(self): + return self._firstOperand + + @property + def SecondOperand(self): + return self._secondOperand + + @property + def ThirdOperand(self): + return self._thirdOperand + @export class Range: From 058254f11d1c802514df58e67a7b1f86426bdbe7 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Fri, 11 Jun 2021 19:30:23 +0200 Subject: [PATCH 22/39] More dependency graphs. --- doc/LanguageModel/Expressions.rst | 5 ++++- pyVHDLModel/VHDLModel.py | 6 +++++- 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/doc/LanguageModel/Expressions.rst b/doc/LanguageModel/Expressions.rst index 3c8b30f7a..d64a1705a 100644 --- a/doc/LanguageModel/Expressions.rst +++ b/doc/LanguageModel/Expressions.rst @@ -82,7 +82,7 @@ Expressions .. rubric:: Class Hierarchy -.. inheritance-diagram:: pyVHDLModel.VHDLModel.UnaryExpression pyVHDLModel.VHDLModel.BinaryExpression pyVHDLModel.VHDLModel.TernaryExpression +.. inheritance-diagram:: pyVHDLModel.VHDLModel.UnaryExpression pyVHDLModel.VHDLModel.AddingExpression pyVHDLModel.VHDLModel.MultiplyingExpression pyVHDLModel.VHDLModel.LogicalExpression pyVHDLModel.VHDLModel.ShiftExpression pyVHDLModel.VHDLModel.TernaryExpression :parts: 1 .. _vhdlmodel-unary: @@ -101,7 +101,10 @@ Unary Expressions Binary Expressions ------------------ +.. rubric:: Class Hierarchy +.. inheritance-diagram:: pyVHDLModel.VHDLModel.AdditionExpression pyVHDLModel.VHDLModel.SubtractionExpression pyVHDLModel.VHDLModel.ConcatenationExpression pyVHDLModel.VHDLModel.MultiplyExpression pyVHDLModel.VHDLModel.DivisionExpression pyVHDLModel.VHDLModel.RemainderExpression pyVHDLModel.VHDLModel.ModuloExpression pyVHDLModel.VHDLModel.ExponentiationExpression + :parts: 1 .. _vhdlmodel-ternary: diff --git a/pyVHDLModel/VHDLModel.py b/pyVHDLModel/VHDLModel.py index 783a83169..6c307556b 100644 --- a/pyVHDLModel/VHDLModel.py +++ b/pyVHDLModel/VHDLModel.py @@ -631,6 +631,10 @@ class AdditionExpression(AddingExpression): class SubtractionExpression(AddingExpression): pass +@export +class ConcatenationExpression(AddingExpression): + pass + @export class MultiplyingExpression(BinaryExpression): """ @@ -654,7 +658,7 @@ class ModuloExpression(MultiplyingExpression): pass @export -class ExponentationExpression(MultiplyingExpression): +class ExponentiationExpression(MultiplyingExpression): pass @export From aab59741b9c63029d923dd1d29f3e0ae10dedccf Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Fri, 11 Jun 2021 22:09:19 +0200 Subject: [PATCH 23/39] Finalized expressions. --- doc/LanguageModel/Expressions.rst | 103 +++++++++++++++++++++++++++++- pyVHDLModel/VHDLModel.py | 85 ++++++++++++++++++++++++ 2 files changed, 187 insertions(+), 1 deletion(-) diff --git a/doc/LanguageModel/Expressions.rst b/doc/LanguageModel/Expressions.rst index d64a1705a..363dcaf07 100644 --- a/doc/LanguageModel/Expressions.rst +++ b/doc/LanguageModel/Expressions.rst @@ -85,6 +85,12 @@ Expressions .. inheritance-diagram:: pyVHDLModel.VHDLModel.UnaryExpression pyVHDLModel.VHDLModel.AddingExpression pyVHDLModel.VHDLModel.MultiplyingExpression pyVHDLModel.VHDLModel.LogicalExpression pyVHDLModel.VHDLModel.ShiftExpression pyVHDLModel.VHDLModel.TernaryExpression :parts: 1 +.. todo:: + + Write documentation. + + + .. _vhdlmodel-unary: Unary Expressions @@ -95,6 +101,11 @@ Unary Expressions .. inheritance-diagram:: pyVHDLModel.VHDLModel.InverseExpression pyVHDLModel.VHDLModel.IdentityExpression pyVHDLModel.VHDLModel.NegationExpression pyVHDLModel.VHDLModel.AbsoluteExpression pyVHDLModel.VHDLModel.TypeConversion pyVHDLModel.VHDLModel.FunctionCall pyVHDLModel.VHDLModel.QualifiedExpression :parts: 1 +.. todo:: + + Write documentation. + + .. _vhdlmodel-binary: @@ -103,10 +114,100 @@ Binary Expressions .. rubric:: Class Hierarchy -.. inheritance-diagram:: pyVHDLModel.VHDLModel.AdditionExpression pyVHDLModel.VHDLModel.SubtractionExpression pyVHDLModel.VHDLModel.ConcatenationExpression pyVHDLModel.VHDLModel.MultiplyExpression pyVHDLModel.VHDLModel.DivisionExpression pyVHDLModel.VHDLModel.RemainderExpression pyVHDLModel.VHDLModel.ModuloExpression pyVHDLModel.VHDLModel.ExponentiationExpression +.. inheritance-diagram:: pyVHDLModel.VHDLModel.AddingExpression pyVHDLModel.VHDLModel.MultiplyingExpression pyVHDLModel.VHDLModel.LogicalExpression pyVHDLModel.VHDLModel.RelationalExpression pyVHDLModel.VHDLModel.ShiftExpression :parts: 1 +.. todo:: + + Write documentation. + + + +.. _vhdlmodel-addingexpression: + +Adding Expressions +~~~~~~~~~~~~~~~~~~ + +.. rubric:: Class Hierarchy + +.. inheritance-diagram:: pyVHDLModel.VHDLModel.AdditionExpression pyVHDLModel.VHDLModel.SubtractionExpression pyVHDLModel.VHDLModel.ConcatenationExpression + :parts: 1 + +.. todo:: + + Write documentation. + + + +.. _vhdlmodel-multiplyingexpressions: + +Multiplying Expressions +~~~~~~~~~~~~~~~~~~~~~~~ + +.. rubric:: Class Hierarchy + +.. inheritance-diagram:: pyVHDLModel.VHDLModel.MultiplyExpression pyVHDLModel.VHDLModel.DivisionExpression pyVHDLModel.VHDLModel.RemainderExpression pyVHDLModel.VHDLModel.ModuloExpression pyVHDLModel.VHDLModel.ExponentiationExpression + :parts: 1 + +.. todo:: + + Write documentation. + + + +.. _vhdlmodel-logicalexpressions: + +Logical Expressions +~~~~~~~~~~~~~~~~~~~ + +.. rubric:: Class Hierarchy + +.. inheritance-diagram:: pyVHDLModel.VHDLModel.AndExpression pyVHDLModel.VHDLModel.NandExpression pyVHDLModel.VHDLModel.OrExpression pyVHDLModel.VHDLModel.NorExpression pyVHDLModel.VHDLModel.XorExpression pyVHDLModel.VHDLModel.XnorExpression + :parts: 1 + +.. todo:: + + Write documentation. + + + +.. _vhdlmodel-relationalexpressions: + +Relational Expressions +~~~~~~~~~~~~~~~~~~~~~~ + +.. rubric:: Class Hierarchy + +.. inheritance-diagram:: pyVHDLModel.VHDLModel.EqualExpression pyVHDLModel.VHDLModel.UnequalExpression pyVHDLModel.VHDLModel.GreaterThanExpression pyVHDLModel.VHDLModel.GreaterEqualExpression pyVHDLModel.VHDLModel.LessThanExpression + :parts: 1 + +.. todo:: + + Write documentation. + + + +.. _vhdlmodel-shiftingexpressions: + +Shifting Expressions +~~~~~~~~~~~~~~~~~~~~ + +.. rubric:: Class Hierarchy + +.. inheritance-diagram:: pyVHDLModel.VHDLModel.ShiftRightLogicExpression pyVHDLModel.VHDLModel.ShiftLeftLogicExpression pyVHDLModel.VHDLModel.ShiftRightArithmeticExpression pyVHDLModel.VHDLModel.ShiftLeftArithmeticExpression pyVHDLModel.VHDLModel.RotateRightExpression pyVHDLModel.VHDLModel.RotateLeftExpression + :parts: 1 + +.. todo:: + + Write documentation. + + + .. _vhdlmodel-ternary: Ternary Expressions ------------------- + +.. todo:: + + Write documentation. diff --git a/pyVHDLModel/VHDLModel.py b/pyVHDLModel/VHDLModel.py index 6c307556b..e22c09cb9 100644 --- a/pyVHDLModel/VHDLModel.py +++ b/pyVHDLModel/VHDLModel.py @@ -667,6 +667,56 @@ class LogicalExpression(BinaryExpression): A ``LogicalExpression`` is a base-class for all logical expressions. """ +@export +class AndExpression(LogicalExpression): + pass + +@export +class NandExpression(LogicalExpression): + pass + +@export +class OrExpression(LogicalExpression): + pass + +@export +class NorExpression(LogicalExpression): + pass + +@export +class XorExpression(LogicalExpression): + pass + +@export +class XnorExpression(LogicalExpression): + pass + +@export +class RelationalExpression(BinaryExpression): + """ + A ``RelationalExpression`` is a base-class for all shifting expressions. + """ + +@export +class EqualExpression(RelationalExpression): + pass + +@export +class UnequalExpression(RelationalExpression): + pass + +@export +class GreaterThanExpression(RelationalExpression): + pass + +@export +class GreaterEqualExpression(RelationalExpression): + pass + +@export +class LessThanExpression(RelationalExpression): + pass + @export class ShiftExpression(BinaryExpression): @@ -674,6 +724,41 @@ class ShiftExpression(BinaryExpression): A ``ShiftExpression`` is a base-class for all shifting expressions. """ +@export +class ShiftLogicExpression(ShiftExpression): + pass + +@export +class ShiftArithmeticExpression(ShiftExpression): + pass + +@export +class RotateExpression(ShiftExpression): + pass + +@export +class ShiftRightLogicExpression(ShiftLogicExpression): + pass + +@export +class ShiftLeftLogicExpression(ShiftLogicExpression): + pass + +@export +class ShiftRightArithmeticExpression(ShiftArithmeticExpression): + pass + +@export +class ShiftLeftArithmeticExpression(ShiftArithmeticExpression): + pass + +@export +class RotateRightExpression(RotateExpression): + pass + +@export +class RotateLeftExpression(RotateExpression): + pass @export class TernaryExpression(Expression): From a770719f750d81845a51a48895a4995da49162f4 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Fri, 11 Jun 2021 22:19:18 +0200 Subject: [PATCH 24/39] Added some more news. --- doc/index.rst | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/doc/index.rst b/doc/index.rst index fdf903c2f..d3a8eb1c3 100644 --- a/doc/index.rst +++ b/doc/index.rst @@ -67,7 +67,11 @@ News .. rubric:: Model and documentation enhancements * Made generic, port, and parameter items a subclass of the matching object classes. +* Finalized literals, expressions and types. +* Corrected class hierarchy according to LRM. * Enhanced class documentation and cross references. +* New documentation chapter for literals and expressions. +* Added inheritance diagrams as overviews to documentation sections. * ... .. only:: html From 75c79dd9cde5cf03a1031fc285292cf2d55649b3 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Sat, 12 Jun 2021 08:27:12 +0200 Subject: [PATCH 25/39] Switch inheritance_diagram and graphviz to original Sphinx extensions as bug is now fixed. --- doc/Dependency.rst | 12 ++++++------ doc/conf.py | 8 ++++---- doc/requirements.txt | 10 +++++----- 3 files changed, 15 insertions(+), 15 deletions(-) diff --git a/doc/Dependency.rst b/doc/Dependency.rst index ac5d83bc3..76b97fac6 100644 --- a/doc/Dependency.rst +++ b/doc/Dependency.rst @@ -28,11 +28,11 @@ sub-dependencies are not evaluated further. +-----------------------------------------------------------+-------------+----------------------------------------------------------------------------------------+----------------------+ | **Package** | **Version** | **License** | **Dependencies** | +===========================================================+=============+========================================================================================+======================+ -| `pytest `__ | ≥6.2.1 | `MIT `__ | *Not yet evaluated.* | +| `pytest `__ | ≥6.2.4 | `MIT `__ | *Not yet evaluated.* | +-----------------------------------------------------------+-------------+----------------------------------------------------------------------------------------+----------------------+ -| `pytest-cov `__ | ≥2.10.1 | `MIT `__ | *Not yet evaluated.* | +| `pytest-cov `__ | ≥2.12.1 | `MIT `__ | *Not yet evaluated.* | +-----------------------------------------------------------+-------------+----------------------------------------------------------------------------------------+----------------------+ -| `Coverage `__ | ≥5.3 | `Apache License, 2.0 `__ | *Not yet evaluated.* | +| `Coverage `__ | ≥5.5 | `Apache License, 2.0 `__ | *Not yet evaluated.* | +-----------------------------------------------------------+-------------+----------------------------------------------------------------------------------------+----------------------+ @@ -48,7 +48,7 @@ evaluated further. +-------------------------------------------------------------------------------------------------+--------------+----------------------------------------------------------------------------------------------------------+----------------------+ | **Package** | **Version** | **License** | **Dependencies** | +=================================================================================================+==============+==========================================================================================================+======================+ -| `Sphinx `__ | ≥3.4.1 | `BSD 3-Clause `__ | *Not yet evaluated.* | +| `Sphinx `__ | ≥4.0.2 | `BSD 3-Clause `__ | *Not yet evaluated.* | +-------------------------------------------------------------------------------------------------+--------------+----------------------------------------------------------------------------------------------------------+----------------------+ | `sphinx_btd_theme `__ | | `MIT `__ | *Not yet evaluated.* | +-------------------------------------------------------------------------------------------------+--------------+----------------------------------------------------------------------------------------------------------+----------------------+ @@ -56,11 +56,11 @@ evaluated further. +-------------------------------------------------------------------------------------------------+--------------+----------------------------------------------------------------------------------------------------------+----------------------+ | !! `sphinx_fontawesome `__ | ≥0.0.6 | `GPL 2.0 `__ | *Not yet evaluated.* | +-------------------------------------------------------------------------------------------------+--------------+----------------------------------------------------------------------------------------------------------+----------------------+ -| `sphinx_autodoc_typehints `__ | ≥1.11.1 | `MIT `__ | *Not yet evaluated.* | +| `sphinx_autodoc_typehints `__ | ≥1.12.0 | `MIT `__ | *Not yet evaluated.* | +-------------------------------------------------------------------------------------------------+--------------+----------------------------------------------------------------------------------------------------------+----------------------+ | `btd.sphinx.graphviz `__ | ≥2.3.1.post1 | `BSD 2-Clause `__ | *Not yet evaluated.* | +-------------------------------------------------------------------------------------------------+--------------+----------------------------------------------------------------------------------------------------------+----------------------+ | `btd.sphinx.inheritance_diagram `__ | ≥2.3.1.post1 | `BSD 2-Clause `__ | *Not yet evaluated.* | +-------------------------------------------------------------------------------------------------+--------------+----------------------------------------------------------------------------------------------------------+----------------------+ -| `Pygments `__ | ≥2.7.2 | `BSD 2-Clause `__ | *Not yet evaluated.* | +| `Pygments `__ | ≥2.9.0 | `BSD 2-Clause `__ | *Not yet evaluated.* | +-------------------------------------------------------------------------------------------------+--------------+----------------------------------------------------------------------------------------------------------+----------------------+ diff --git a/doc/conf.py b/doc/conf.py index 9ebd25b8c..b6cfd5032 100644 --- a/doc/conf.py +++ b/doc/conf.py @@ -171,9 +171,9 @@ def _LatestTagName(): "sphinx.ext.autodoc", 'sphinx.ext.extlinks', 'sphinx.ext.intersphinx', -# 'sphinx.ext.inheritance_diagram', + 'sphinx.ext.inheritance_diagram', 'sphinx.ext.todo', -# 'sphinx.ext.graphviz', + 'sphinx.ext.graphviz', 'sphinx.ext.mathjax', 'sphinx.ext.ifconfig', 'sphinx.ext.viewcode', @@ -188,8 +188,8 @@ def _LatestTagName(): # BuildTheDocs extensions # 'btd.sphinx.autoprogram', - 'btd.sphinx.graphviz', - 'btd.sphinx.inheritance_diagram', +# 'btd.sphinx.graphviz', +# 'btd.sphinx.inheritance_diagram', # Other extensions # 'DocumentMember', diff --git a/doc/requirements.txt b/doc/requirements.txt index 45c06a9ce..e3886e19f 100644 --- a/doc/requirements.txt +++ b/doc/requirements.txt @@ -1,6 +1,6 @@ -r ../requirements.txt # Enforce latest version on ReadTheDocs -sphinx>=3.4.1 +sphinx>=4.0.2 # Sphinx Extenstions #sphinx.ext.coverage @@ -10,13 +10,13 @@ sphinx>=3.4.1 #sphinxcontrib-spelling>=2.2.0 autoapi sphinx_fontawesome>=0.0.6 -sphinx_autodoc_typehints>=1.11.1 +sphinx_autodoc_typehints>=1.12.0 # changelog>=0.3.5 # BuildTheDocs Extensions (mostly patched Sphinx extensions) #btd.sphinx.autoprogram>=0.1.6.post1 -btd.sphinx.graphviz>=2.3.1.post1 -btd.sphinx.inheritance_diagram>=2.3.1.post1 +#btd.sphinx.graphviz>=2.3.1.post1 +#btd.sphinx.inheritance_diagram>=2.3.1.post1 # Enforce newer version on ReadTheDocs (currently using 2.3.1) -Pygments>=2.7.2 +Pygments>=2.9.0 From fc1cb58c978194b6f2c9aca26dda63e252ef3a4a Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Sat, 12 Jun 2021 10:06:18 +0200 Subject: [PATCH 26/39] Removed unsued dependencies. --- doc/Dependency.rst | 4 ---- 1 file changed, 4 deletions(-) diff --git a/doc/Dependency.rst b/doc/Dependency.rst index 76b97fac6..a037859fb 100644 --- a/doc/Dependency.rst +++ b/doc/Dependency.rst @@ -58,9 +58,5 @@ evaluated further. +-------------------------------------------------------------------------------------------------+--------------+----------------------------------------------------------------------------------------------------------+----------------------+ | `sphinx_autodoc_typehints `__ | ≥1.12.0 | `MIT `__ | *Not yet evaluated.* | +-------------------------------------------------------------------------------------------------+--------------+----------------------------------------------------------------------------------------------------------+----------------------+ -| `btd.sphinx.graphviz `__ | ≥2.3.1.post1 | `BSD 2-Clause `__ | *Not yet evaluated.* | -+-------------------------------------------------------------------------------------------------+--------------+----------------------------------------------------------------------------------------------------------+----------------------+ -| `btd.sphinx.inheritance_diagram `__ | ≥2.3.1.post1 | `BSD 2-Clause `__ | *Not yet evaluated.* | -+-------------------------------------------------------------------------------------------------+--------------+----------------------------------------------------------------------------------------------------------+----------------------+ | `Pygments `__ | ≥2.9.0 | `BSD 2-Clause `__ | *Not yet evaluated.* | +-------------------------------------------------------------------------------------------------+--------------+----------------------------------------------------------------------------------------------------------+----------------------+ From 0099f6eae6fa5f2a3fb01ad58520156ee055b657 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Sat, 12 Jun 2021 10:07:01 +0200 Subject: [PATCH 27/39] Added class hierarchy for concurrent statements. --- doc/LanguageModel/ConcurrentStatements.rst | 62 ++++++++++++++++++---- pyVHDLModel/VHDLModel.py | 46 ++++++++++++++-- 2 files changed, 93 insertions(+), 15 deletions(-) diff --git a/doc/LanguageModel/ConcurrentStatements.rst b/doc/LanguageModel/ConcurrentStatements.rst index 4c4187dde..fcb463316 100644 --- a/doc/LanguageModel/ConcurrentStatements.rst +++ b/doc/LanguageModel/ConcurrentStatements.rst @@ -5,13 +5,26 @@ Concurrent Statements * :ref:`vhdlmodel-con-assertstatement` * :ref:`vhdlmodel-con-signalassignment` -* :ref:`vhdlmodel-instantiation` -* :ref:`vhdlmodel-ifgenerate` -* :ref:`vhdlmodel-casegenerate` -* :ref:`vhdlmodel-forgenerate` +* :ref:`vhdlmodel-instantiations` + + * :ref:`vhdlmodel-entityinstantiation` + * :ref:`vhdlmodel-componentinstantiation` + * :ref:`vhdlmodel-configurationinstantiation` + +* :ref:`vhdlmodel-generates` + + * :ref:`vhdlmodel-ifgenerate` + * :ref:`vhdlmodel-casegenerate` + * :ref:`vhdlmodel-forgenerate` + * :ref:`vhdlmodel-con-procedurecall` * :ref:`vhdlmodel-process` +.. rubric:: Class Hierarchy + +.. inheritance-diagram:: pyVHDLModel.VHDLModel.ConcurrentAssertStatement pyVHDLModel.VHDLModel.ConcurrentSignalAssignment pyVHDLModel.VHDLModel.ConcurrentBlockStatement pyVHDLModel.VHDLModel.ProcessStatement pyVHDLModel.VHDLModel.IfGenerateStatement pyVHDLModel.VHDLModel.CaseGenerateStatement pyVHDLModel.VHDLModel.ForGenerateStatement pyVHDLModel.VHDLModel.ComponentInstantiation pyVHDLModel.VHDLModel.ConfigurationInstantiation pyVHDLModel.VHDLModel.EntityInstantiation pyVHDLModel.VHDLModel.ConcurrentProcedureCall + :parts: 1 + .. _vhdlmodel-con-assertstatement: Assert @@ -30,19 +43,48 @@ Signal Assignment Write documentation. -.. _vhdlmodel-instantiation: +.. _vhdlmodel-con-blockstatement: -Instantiation -============= +Concurrent Block Statement +========================== .. todo:: Write documentation. +.. _vhdlmodel-instantiations: + +Instantiations +============== + +.. todo:: + + Write documentation. + +.. _vhdlmodel-entityinstantiation: + +EntityInstantiation +------------------- + +.. _vhdlmodel-componentinstantiation: + +ComponentInstantiation +---------------------- + +.. _vhdlmodel-configurationinstantiation: + +ConfigurationInstantiation +-------------------------- + +.. _vhdlmodel-generates: + +Generate Statements +=================== + .. _vhdlmodel-ifgenerate: If Generate -=========== +----------- .. todo:: @@ -51,7 +93,7 @@ If Generate .. _vhdlmodel-casegenerate: Case Generate -============= +------------- .. todo:: @@ -60,7 +102,7 @@ Case Generate .. _vhdlmodel-forgenerate: For Generate -============ +------------ .. todo:: diff --git a/pyVHDLModel/VHDLModel.py b/pyVHDLModel/VHDLModel.py index e22c09cb9..736a41912 100644 --- a/pyVHDLModel/VHDLModel.py +++ b/pyVHDLModel/VHDLModel.py @@ -1267,24 +1267,27 @@ def Actual(self) -> Expression: class GenericAssociationItem(AssociationItem): pass + @export class PortAssociationItem(AssociationItem): pass + @export class ParameterAssociationItem(AssociationItem): pass @export -class Instantiation: +class GenericEntityInstantiation: pass + @export -class SubprogramInstantiation(ModelEntity, Instantiation): +class SubprogramInstantiation(ModelEntity, GenericEntityInstantiation): def __init__(self): super().__init__() - Instantiation.__init__(self) + GenericEntityInstantiation.__init__(self) self._subprogramReference = None @@ -1340,13 +1343,13 @@ def DeclaredItems(self) -> List: @export -class PackageInstantiation(PrimaryUnit, Instantiation): +class PackageInstantiation(PrimaryUnit, GenericEntityInstantiation): _packageReference: Package _genericAssociations: List[GenericAssociationItem] def __init__(self, name: str): super().__init__(name) - Instantiation.__init__(self) + GenericEntityInstantiation.__init__(self) self._genericAssociations = [] @@ -1380,6 +1383,24 @@ class SequentialStatement(Statement): """ +@export +class Instantiation(ConcurrentStatement): + pass + + +@export +class ComponentInstantiation(Instantiation): + pass + +@export +class EntityInstantiation(Instantiation): + pass + +@export +class ConfigurationInstantiation(Instantiation): + pass + + @export class ProcessStatement(ConcurrentStatement): _parameterItems: List[Signal] @@ -1405,6 +1426,18 @@ def DeclaredItems(self) -> List: def BodyItems(self) -> List[SequentialStatement]: return self._bodyItems +@export +class ProcedureCall: + pass + +@export +class ConcurrentProcedureCall(ConcurrentStatement, ProcedureCall): + pass + +@export +class SequentialProcedureCall(SequentialStatement, ProcedureCall): + pass + # TODO: could be unified with ProcessStatement if 'List[ConcurrentStatement]' becomes parametric to T class BlockStatement: @@ -1543,6 +1576,9 @@ def __init__(self, label: str = None): self._elsifBranches = [] +@export +class CaseGenerateStatement(GenerateStatement): + pass @export class ForGenerateStatement(GenerateStatement): From a16beb8d5c719e4859399d025815b54c74499218 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Sat, 12 Jun 2021 13:29:07 +0200 Subject: [PATCH 28/39] AAdded class hierarchy for sequential statements. --- doc/LanguageModel/SequentialStatements.rst | 94 +++++++++++++++++++--- pyVHDLModel/VHDLModel.py | 15 +++- 2 files changed, 93 insertions(+), 16 deletions(-) diff --git a/doc/LanguageModel/SequentialStatements.rst b/doc/LanguageModel/SequentialStatements.rst index af9bd7e99..6caa72794 100644 --- a/doc/LanguageModel/SequentialStatements.rst +++ b/doc/LanguageModel/SequentialStatements.rst @@ -5,13 +5,31 @@ Sequential Statements * :ref:`vhdlmodel-seq-signalassignment` * :ref:`vhdlmodel-variableassignment` -* :ref:`vhdlmodel-ifstatement` -* :ref:`vhdlmodel-casestatement` -* :ref:`vhdlmodel-forloop` -* :ref:`vhdlmodel-whileloop` -* :ref:`vhdlmodel-seq-reportstatement` -* :ref:`vhdlmodel-seq-assertstatement` +* :ref:`vhdlmodel-branching` + + * :ref:`vhdlmodel-ifstatement` + * :ref:`vhdlmodel-casestatement` + +* :ref:`vhdlmodel-loops` + + * :ref:`vhdlmodel-forloop` + * :ref:`vhdlmodel-whileloop` + * :ref:`vhdlmodel-nextstatement` + * :ref:`vhdlmodel-exitstatement` + +* :ref:`vhdlmodel-reporting` + + * :ref:`vhdlmodel-seq-reportstatement` + * :ref:`vhdlmodel-seq-assertstatement` + * :ref:`vhdlmodel-seq-procedurecall` +* :ref:`vhdlmodel-waitstatement` +* :ref:`vhdlmodel-returnstatement` + +.. rubric:: Class Hierarchy + +.. inheritance-diagram:: pyVHDLModel.VHDLModel.SequentialAssertStatement pyVHDLModel.VHDLModel.SequentialReportStatement pyVHDLModel.VHDLModel.SequentialSignalAssignment pyVHDLModel.VHDLModel.VariableAssignment pyVHDLModel.VHDLModel.IfStatement pyVHDLModel.VHDLModel.CaseStatement pyVHDLModel.VHDLModel.ForLoopStatement pyVHDLModel.VHDLModel.WhileLoopStatement pyVHDLModel.VHDLModel.NextStatement pyVHDLModel.VHDLModel.ExitStatement pyVHDLModel.VHDLModel.SequentialProcedureCall pyVHDLModel.VHDLModel.WaitStatement pyVHDLModel.VHDLModel.ReturnStatement + :parts: 1 .. _vhdlmodel-seq-signalassignment: @@ -31,10 +49,15 @@ Variable Assignment Write documentation. +.. _vhdlmodel-branching: + +Branching +========= + .. _vhdlmodel-ifstatement: If Statement -============ +------------ .. todo:: @@ -43,16 +66,21 @@ If Statement .. _vhdlmodel-casestatement: Case Statement -============== +-------------- .. todo:: Write documentation. +.. _vhdlmodel-loops: + +Loops +===== + .. _vhdlmodel-forloop: For Loop -======== +-------- .. todo:: @@ -61,16 +89,40 @@ For Loop .. _vhdlmodel-whileloop: While Loop -========== +---------- + +.. todo:: + + Write documentation. + +.. _vhdlmodel-nextstatement: + +Next Statement +-------------- + +.. todo:: + + Write documentation. + +.. _vhdlmodel-exitstatement: + +Exit Statement +-------------- .. todo:: Write documentation. +.. _vhdlmodel-reporting: + +Reporting +========= + + .. _vhdlmodel-seq-reportstatement: Report Statement -================ +---------------- .. todo:: @@ -79,7 +131,7 @@ Report Statement .. _vhdlmodel-seq-assertstatement: Assert Statement -================ +---------------- .. todo:: @@ -93,3 +145,21 @@ Procedure Call .. todo:: Write documentation. + +.. _vhdlmodel-waitstatement: + +Wait Statement +============== + +.. todo:: + + Write documentation. + +.. _vhdlmodel-returnstatement: + +Return Statement +================ + +.. todo:: + + Write documentation. diff --git a/pyVHDLModel/VHDLModel.py b/pyVHDLModel/VHDLModel.py index 736a41912..dae254cb6 100644 --- a/pyVHDLModel/VHDLModel.py +++ b/pyVHDLModel/VHDLModel.py @@ -389,7 +389,7 @@ class FileType(BaseType): @export class EnumeratedType(ScalarType, DiscreteType): - _elements: List[str] + _elements: List['EnumerationLiteral'] def __init__(self, name: str): super().__init__(name) @@ -397,7 +397,7 @@ def __init__(self, name: str): self._elements = [] @property - def Elements(self) -> List[str]: + def Elements(self) -> List['EnumerationLiteral']: return self._elements @@ -1781,6 +1781,9 @@ def ElsIfBranches(self) -> List['ElsifBranch']: def ElseBranch(self) -> ElseBranch: return self._elseBranch +@export +class CaseStatement(CompoundStatement): + pass @export class LoopStatement(CompoundStatement): @@ -1814,7 +1817,7 @@ def __init__(self): @export -class LoopControlStatement(ModelEntity, BaseConditional): +class LoopControlStatement(SequentialStatement, BaseConditional): """ A ``LoopControlStatement`` is a base-class for all loop controlling statements. """ @@ -1838,5 +1841,9 @@ class ExitStatement(LoopControlStatement): pass @export -class ReturnStatement(SequentialStatement): +class WaitStatement(SequentialStatement): + pass + +@export +class ReturnStatement(SequentialStatement, BaseConditional): pass From 516f41ab4d15ef6c000d132e35db16845037b6ad Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Sat, 12 Jun 2021 13:31:05 +0200 Subject: [PATCH 29/39] Grouped sequential assignments. --- doc/LanguageModel/SequentialStatements.rst | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/doc/LanguageModel/SequentialStatements.rst b/doc/LanguageModel/SequentialStatements.rst index 6caa72794..a9c866150 100644 --- a/doc/LanguageModel/SequentialStatements.rst +++ b/doc/LanguageModel/SequentialStatements.rst @@ -3,8 +3,11 @@ Sequential Statements ##################### -* :ref:`vhdlmodel-seq-signalassignment` -* :ref:`vhdlmodel-variableassignment` +* :ref:`vhdlmodel-seq-assignments` + + * :ref:`vhdlmodel-seq-signalassignment` + * :ref:`vhdlmodel-variableassignment` + * :ref:`vhdlmodel-branching` * :ref:`vhdlmodel-ifstatement` @@ -31,10 +34,15 @@ Sequential Statements .. inheritance-diagram:: pyVHDLModel.VHDLModel.SequentialAssertStatement pyVHDLModel.VHDLModel.SequentialReportStatement pyVHDLModel.VHDLModel.SequentialSignalAssignment pyVHDLModel.VHDLModel.VariableAssignment pyVHDLModel.VHDLModel.IfStatement pyVHDLModel.VHDLModel.CaseStatement pyVHDLModel.VHDLModel.ForLoopStatement pyVHDLModel.VHDLModel.WhileLoopStatement pyVHDLModel.VHDLModel.NextStatement pyVHDLModel.VHDLModel.ExitStatement pyVHDLModel.VHDLModel.SequentialProcedureCall pyVHDLModel.VHDLModel.WaitStatement pyVHDLModel.VHDLModel.ReturnStatement :parts: 1 +.. _vhdlmodel-seq-assignments: + +Assignments +=========== + .. _vhdlmodel-seq-signalassignment: Signal Assignment -================= +----------------- .. todo:: @@ -43,7 +51,7 @@ Signal Assignment .. _vhdlmodel-variableassignment: Variable Assignment -=================== +------------------- .. todo:: From c7178c0286e542b047405c2488521c8203ea424d Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Sat, 12 Jun 2021 13:37:52 +0200 Subject: [PATCH 30/39] Fine tuning. --- doc/LanguageModel/ConcurrentStatements.rst | 16 ++++++------ doc/LanguageModel/ObjectDeclarations.rst | 28 ++++++++++----------- doc/LanguageModel/SubprogramDefinitions.rst | 24 +++++++++--------- 3 files changed, 34 insertions(+), 34 deletions(-) diff --git a/doc/LanguageModel/ConcurrentStatements.rst b/doc/LanguageModel/ConcurrentStatements.rst index fcb463316..4c6124e58 100644 --- a/doc/LanguageModel/ConcurrentStatements.rst +++ b/doc/LanguageModel/ConcurrentStatements.rst @@ -27,8 +27,8 @@ Concurrent Statements .. _vhdlmodel-con-assertstatement: -Assert -====== +Assert Statement +================ .. todo:: @@ -63,18 +63,18 @@ Instantiations .. _vhdlmodel-entityinstantiation: -EntityInstantiation -------------------- +Entity Instantiation +-------------------- .. _vhdlmodel-componentinstantiation: -ComponentInstantiation ----------------------- +Component Instantiation +----------------------- .. _vhdlmodel-configurationinstantiation: -ConfigurationInstantiation --------------------------- +Configuration Instantiation +--------------------------- .. _vhdlmodel-generates: diff --git a/doc/LanguageModel/ObjectDeclarations.rst b/doc/LanguageModel/ObjectDeclarations.rst index 9ec9c52f8..cf2ba1c77 100644 --- a/doc/LanguageModel/ObjectDeclarations.rst +++ b/doc/LanguageModel/ObjectDeclarations.rst @@ -80,8 +80,8 @@ a deferred constant. See :ref:`vhdlmodel-deferredconstant` in next section. .. _vhdlmodel-deferredconstant: -DeferredConstant ----------------- +Deferred Constant +----------------- If a constant's value is delayed in calculation, it's a deferred constant. Such a deferred constant has a reference to the *regular* constant of the same name. @@ -112,8 +112,8 @@ a deferred constant has a reference to the *regular* constant of the same name. .. _vhdlmodel-obj-genericconstant: -GenericConstantInterfaceItem ----------------------------- +Generic Constant +---------------- A generic without object class or a generic constant is a *regular* constant. @@ -123,8 +123,8 @@ A generic without object class or a generic constant is a *regular* constant. .. _vhdlmodel-obj-parameterconstant: -ParameterConstantInterfaceItem ------------------------------- +Constant as Parameter +--------------------- A subprogram parameter without object class of mode *in* or a parameter constant is a *regular* constant. @@ -177,8 +177,8 @@ expression. .. _vhdlmodel-obj-parametervariable: -ParameterVariableInterfaceItem ------------------------------- +Variable as Parameter +--------------------- A subprogram parameter without object class of mode *out* or a parameter variable is a *regular* variable. @@ -239,8 +239,8 @@ assigned via a default expression. .. _vhdlmodel-obj-portsignal: -PortSignalInterfaceItem ------------------------ +Signal as Port +-------------- A port signal is a *regular* signal. @@ -250,8 +250,8 @@ A port signal is a *regular* signal. .. _vhdlmodel-obj-parametersignal: -ParameterSignalInterfaceItem ----------------------------- +Signal as Parameter +------------------- A parameter signal is a *regular* signal. @@ -278,8 +278,8 @@ File .. _vhdlmodel-obj-parameterfile: -ParameterFileInterfaceItem --------------------------- +File as Parameter +----------------- A parameter file is a *regular* file. diff --git a/doc/LanguageModel/SubprogramDefinitions.rst b/doc/LanguageModel/SubprogramDefinitions.rst index af6a7ab05..615b6d49c 100644 --- a/doc/LanguageModel/SubprogramDefinitions.rst +++ b/doc/LanguageModel/SubprogramDefinitions.rst @@ -72,8 +72,8 @@ Procedure .. _vhdlmodel-procedureinstantiation: -ProcedureInstantiation ----------------------- +Procedure Instantiation +----------------------- .. todo:: @@ -83,8 +83,8 @@ ProcedureInstantiation .. _vhdlmodel-proceduremethod: -ProcedureMethod ---------------- +Procedure as Method +------------------- **Condensed definition of class** :class:`~pyVHDLModel.VHDLModel.ProcedureMethod`: @@ -129,8 +129,8 @@ ProcedureMethod .. _vhdlmodel-sub-genericprocedure: -GenericProcedureInterfaceItem ------------------------------ +Generic Procedure +----------------- A generic procedure is a *regular* procedure. @@ -195,8 +195,8 @@ Function .. _vhdlmodel-functioninstantiation: -FunctionInstantiation ---------------------- +Function Instantiation +---------------------- .. todo:: @@ -206,8 +206,8 @@ FunctionInstantiation .. _vhdlmodel-functionmethod: -FunctionMethod --------------- +Function as Method +------------------ **Condensed definition of class** :class:`~pyVHDLModel.VHDLModel.FunctionMethod`: @@ -256,8 +256,8 @@ FunctionMethod .. _vhdlmodel-sub-genericfunction: -GenericFunctionInterfaceItem ----------------------------- +Generic Function +---------------- A generic function is a *regular* function. From 81d16ed0e70af9a7cf565cdcd722bcf99e3a7b62 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Sat, 12 Jun 2021 23:27:56 +0200 Subject: [PATCH 31/39] Model refinements. --- pyVHDLModel/VHDLModel.py | 271 ++++++++++++++++++++++++++++----------- 1 file changed, 195 insertions(+), 76 deletions(-) diff --git a/pyVHDLModel/VHDLModel.py b/pyVHDLModel/VHDLModel.py index dae254cb6..761c5bb67 100644 --- a/pyVHDLModel/VHDLModel.py +++ b/pyVHDLModel/VHDLModel.py @@ -1383,6 +1383,53 @@ class SequentialStatement(Statement): """ +@export +class ConcurrentDeclarations: + _declaredItems: List + + def __init__(self): + self._declaredItems = [] + + @property + def DeclaredItems(self) -> List: + return self._declaredItems + + +@export +class ConcurrentStatements: + _statements: List[ConcurrentStatement] + + def __init__(self): + self._statements = [] + + @property + def Statements(self) -> List[ConcurrentStatement]: + return self._statements + +@export +class SequentialDeclarations: + _declaredItems: List + + def __init__(self): + self._declaredItems = [] + + @property + def DeclaredItems(self) -> List: + return self._declaredItems + + +@export +class SequentialStatements: + _statements: List[SequentialStatement] + + def __init__(self): + self._statements = [] + + @property + def Statements(self) -> List[SequentialStatement]: + return self._statements + + @export class Instantiation(ConcurrentStatement): pass @@ -1402,59 +1449,40 @@ class ConfigurationInstantiation(Instantiation): @export -class ProcessStatement(ConcurrentStatement): - _parameterItems: List[Signal] - _declaredItems: List # TODO: create a union for (concurrent / sequential) DeclaredItems - _bodyItems: List[SequentialStatement] +class ProcessStatement(ConcurrentStatement, SequentialDeclarations, SequentialStatements): + _sensitivityList: List[Signal] def __init__(self, label: str = None): super().__init__(label=label) - - self._parameterItems = [] - self._declaredItems = [] - self._bodyItems = [] - - @property - def ParameterItems(self) -> List[Signal]: - return self._parameterItems + SequentialDeclarations.__init__(self) + SequentialStatements.__init__(self) @property - def DeclaredItems(self) -> List: - return self._declaredItems + def SensitivityList(self) -> List[Signal]: + return self._sensitivityList - @property - def BodyItems(self) -> List[SequentialStatement]: - return self._bodyItems @export class ProcedureCall: pass + @export class ConcurrentProcedureCall(ConcurrentStatement, ProcedureCall): pass + @export class SequentialProcedureCall(SequentialStatement, ProcedureCall): pass # TODO: could be unified with ProcessStatement if 'List[ConcurrentStatement]' becomes parametric to T -class BlockStatement: - _declaredItems: List # TODO: create a union for (concurrent / sequential) DeclaredItems - _bodyItems: List[ConcurrentStatement] - +class BlockStatement(ConcurrentStatement, ConcurrentDeclarations, ConcurrentStatements): def __init__(self): - self._declaredItems = [] - self._bodyItems = [] - - @property - def DeclaredItems(self) -> List: - return self._declaredItems - - @property - def BodyItems(self) -> List[ConcurrentStatement]: - return self._bodyItems + super().__init__() + ConcurrentDeclarations.__init__(self) + ConcurrentStatements.__init__(self) @export @@ -1475,7 +1503,7 @@ def PortItems(self) -> List[PortInterfaceItem]: @export class BaseConditional: """ - A ``BaseConditional`` is a base-class for all conditional statements. + A ``BaseConditional`` is a base-class for all statements with a condition. """ _condition: Expression @@ -1487,13 +1515,14 @@ def Condition(self) -> Expression: @export class BaseBranch: """ - A ``BaseBranch`` is a base-class for all statements with branches. + A ``BaseBranch`` is a mixin-class for all statements with branches. """ + @export class BaseConditionalBranch(BaseBranch, BaseConditional): """ - A ``BaseBranch`` is a base-class for all conditional statements with branches. + A ``BaseBranch`` is a mixin-class for all branch statements with a condition. """ def __init__(self): super().__init__() @@ -1503,30 +1532,36 @@ def __init__(self): @export class BaseIfBranch(BaseConditionalBranch): """ - A ``BaseIfBranch`` is a base-class for all conditional statements with - if-branches. + A ``BaseIfBranch`` is a mixin-class for all if-branches. """ + @export class BaseElsifBranch(BaseConditionalBranch): """ - A ``BaseElsifBranch`` is a base-class for all conditional statements with - elsif-branches. + A ``BaseElsifBranch`` is a mixin-class for all elsif-branches. """ + @export class BaseElseBranch(BaseBranch): """ - A ``BaseElseBranch`` is a base-class for all conditional statements with - else-branches. + A ``BaseElseBranch`` is a mixin-class for all else-branches. """ + @export -class GenerateBranch(ModelEntity): +class GenerateBranch(ModelEntity, ConcurrentDeclarations, ConcurrentStatements): """ A ``GenerateBranch`` is a base-class for all branches in a generate statements. """ + def __init__(self): + super().__init__() + ConcurrentDeclarations.__init__(self) + ConcurrentStatements.__init__(self) + + @export class IfGenerateBranch(GenerateBranch, BaseIfBranch): def __init__(self): @@ -1550,43 +1585,103 @@ def __init__(self): @export class GenerateStatement(ConcurrentStatement): + """ + A ``GenerateStatement`` is a base-class for all generate statements. + """ + def __init__(self, label: str = None): super().__init__(label=label) - self._declaredItems = [] - self._bodyItems = [] + +@export +class IfGenerateStatement(GenerateStatement): + _ifBranch: IfGenerateBranch + _elsifBranches: List[ElsifGenerateBranch] + _elseBranch: ElseGenerateBranch + + def __init__(self, label: str = None): + super().__init__(label=label) + + self._elsifBranches = [] @property - def DeclaredItems(self): - return self._declaredItems + def IfBranch(self) -> IfGenerateBranch: + return self._ifBranch @property - def BodyItems(self): - return self._bodyItems + def ElsifBranches(self) -> List[ElsifGenerateBranch]: + return self._elsifBranches + + @property + def ElseBranch(self) -> ElseGenerateBranch: + return self._elseBranch @export -class IfGenerateStatement(GenerateStatement): - _ifBranch: IfGenerateBranch - _elsifBranch: List['ElsifGenerateBranch'] - _elseBranch: ElseGenerateBranch +class Choice(ModelEntity): + """ + A ``Choice`` is a base-class for all choices. + """ + + +@export +class Case(ModelEntity): + """ + A ``Case`` is a base-class for all cases. + """ + + +@export +class ConcurrentCase(Case, LabeledEntity, ConcurrentDeclarations, ConcurrentStatements): + _choices: List def __init__(self, label: str = None): - super().__init__(label=label) + super().__init__() + LabeledEntity.__init__(self, label) + ConcurrentDeclarations.__init__(self) + ConcurrentStatements.__init__(self) + + @property + def Choises(self) -> List[Choice]: + return self._choices + + +@export +class SequentialCase(Case, SequentialStatements): + _choices: List + + def __init__(self): + super().__init__() + SequentialStatements.__init__(self) + + @property + def Choises(self) -> List[Choice]: + return self._choices - self._elsifBranches = [] @export class CaseGenerateStatement(GenerateStatement): - pass + _selectExpression: Expression + _cases: List[ConcurrentCase] + + @property + def SelectExpression(self) -> Expression: + return self._selectExpression + + @property + def Cases(self) -> List[ConcurrentCase]: + return self._cases + @export -class ForGenerateStatement(GenerateStatement): +class ForGenerateStatement(GenerateStatement, ConcurrentDeclarations, ConcurrentStatements): _loopIndex: Constant _range: Range def __init__(self, label: str = None): super().__init__(label=label) + ConcurrentDeclarations.__init__(self) + ConcurrentStatements.__init__(self) @property def LoopIndex(self) -> Constant: @@ -1596,18 +1691,13 @@ def LoopIndex(self) -> Constant: def Range(self) -> Range: return self._range -# TODO: CaseGenerateStatement -# class CaseGenerateStatement(GenerateStatement): -# def __init__(self): -# super().__init__() -# self._expression = None -# self._cases = [] @export class Assignment: """ An ``Assignment`` is a base-class for all assignment statements. """ + _target: Object _expression: Expression @@ -1641,7 +1731,6 @@ class VariableAssignment(Assignment): class ConcurrentSignalAssignment(ConcurrentStatement, SignalAssignment): def __init__(self, label: str = None): super().__init__(label=label) - SignalAssignment.__init__(self) @@ -1659,7 +1748,6 @@ def __init__(self): VariableAssignment.__init__(self) - @export class ReportStatement: """ @@ -1718,7 +1806,9 @@ def __init__(self): @export class Branch(ModelEntity): - pass + """ + A ``Branch`` is a base-class for all branches. + """ @export class IfBranch(Branch, BaseIfBranch): @@ -1742,20 +1832,14 @@ def __init__(self): @export -class CompoundStatement(SequentialStatement): +class CompoundStatement(SequentialStatement, SequentialStatements): """ A ``CompoundStatement`` is a base-class for all compound statements. """ - _bodyItems: List[SequentialStatement] def __init__(self): super().__init__() - - self._bodyItems = [] - - @property - def BodyItems(self) -> List[SequentialStatement]: - return self._bodyItems + SequentialStatements.__init__(self) @export @@ -1781,9 +1865,20 @@ def ElsIfBranches(self) -> List['ElsifBranch']: def ElseBranch(self) -> ElseBranch: return self._elseBranch + @export class CaseStatement(CompoundStatement): - pass + _selectExpression: Expression + _cases: List[SequentialCase] + + @property + def SelectExpression(self) -> Expression: + return self._selectExpression + + @property + def Cases(self) -> List[SequentialCase]: + return self._cases + @export class LoopStatement(CompoundStatement): @@ -1836,14 +1931,38 @@ def LoopReference(self) -> LoopStatement: class NextStatement(LoopControlStatement): pass + @export class ExitStatement(LoopControlStatement): pass + @export -class WaitStatement(SequentialStatement): - pass +class WaitStatement(SequentialStatement, BaseConditional): + _sensitivityList : List[Signal] + _timeout: Expression + + def __init__(self): + super().__init__() + BaseConditional.__init__(self) + + @property + def SensitivityList(self) -> List[Signal]: + return self._sensitivityList + + @property + def Timeout(self) -> Expression: + return self._timeout + @export class ReturnStatement(SequentialStatement, BaseConditional): - pass + _returnValue: Expression + + def __init__(self): + super().__init__() + BaseConditional.__init__(self) + + @property + def ReturnValue(self) -> Expression: + return self._returnValue From 949f6f2f6c8b0eb7375f5799d3bf7de92c587922 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Sat, 12 Jun 2021 23:56:37 +0200 Subject: [PATCH 32/39] Fixed MRO problem. --- pyVHDLModel/VHDLModel.py | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/pyVHDLModel/VHDLModel.py b/pyVHDLModel/VHDLModel.py index 761c5bb67..328d7d956 100644 --- a/pyVHDLModel/VHDLModel.py +++ b/pyVHDLModel/VHDLModel.py @@ -1478,20 +1478,21 @@ class SequentialProcedureCall(SequentialStatement, ProcedureCall): # TODO: could be unified with ProcessStatement if 'List[ConcurrentStatement]' becomes parametric to T -class BlockStatement(ConcurrentStatement, ConcurrentDeclarations, ConcurrentStatements): - def __init__(self): - super().__init__() - ConcurrentDeclarations.__init__(self) - ConcurrentStatements.__init__(self) +class BlockStatement: + """ + A ``BlockStatement`` is a mixin-class for all block statements. + """ @export -class ConcurrentBlockStatement(ConcurrentStatement, BlockStatement): +class ConcurrentBlockStatement(ConcurrentStatement, BlockStatement, ConcurrentDeclarations, ConcurrentStatements): _portItems: List[PortInterfaceItem] def __init__(self, label: str = None): super().__init__(label=label) BlockStatement.__init__(self) + ConcurrentDeclarations.__init__(self) + ConcurrentStatements.__init__(self) self._portItems = [] From 9a7367f6a84a2c81ca7d99eac1bbd5d1ad24a2a5 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Sun, 13 Jun 2021 00:46:25 +0200 Subject: [PATCH 33/39] Added endless loop. --- doc/LanguageModel/SequentialStatements.rst | 32 +++++++++++++++++++++- pyVHDLModel/VHDLModel.py | 23 ++++++++++++---- 2 files changed, 49 insertions(+), 6 deletions(-) diff --git a/doc/LanguageModel/SequentialStatements.rst b/doc/LanguageModel/SequentialStatements.rst index a9c866150..4752d6b30 100644 --- a/doc/LanguageModel/SequentialStatements.rst +++ b/doc/LanguageModel/SequentialStatements.rst @@ -15,6 +15,7 @@ Sequential Statements * :ref:`vhdlmodel-loops` + * :ref:`vhdlmodel-endlessloop` * :ref:`vhdlmodel-forloop` * :ref:`vhdlmodel-whileloop` * :ref:`vhdlmodel-nextstatement` @@ -31,7 +32,7 @@ Sequential Statements .. rubric:: Class Hierarchy -.. inheritance-diagram:: pyVHDLModel.VHDLModel.SequentialAssertStatement pyVHDLModel.VHDLModel.SequentialReportStatement pyVHDLModel.VHDLModel.SequentialSignalAssignment pyVHDLModel.VHDLModel.VariableAssignment pyVHDLModel.VHDLModel.IfStatement pyVHDLModel.VHDLModel.CaseStatement pyVHDLModel.VHDLModel.ForLoopStatement pyVHDLModel.VHDLModel.WhileLoopStatement pyVHDLModel.VHDLModel.NextStatement pyVHDLModel.VHDLModel.ExitStatement pyVHDLModel.VHDLModel.SequentialProcedureCall pyVHDLModel.VHDLModel.WaitStatement pyVHDLModel.VHDLModel.ReturnStatement +.. inheritance-diagram:: pyVHDLModel.VHDLModel.SequentialAssertStatement pyVHDLModel.VHDLModel.SequentialReportStatement pyVHDLModel.VHDLModel.SequentialSignalAssignment pyVHDLModel.VHDLModel.VariableAssignment pyVHDLModel.VHDLModel.IfStatement pyVHDLModel.VHDLModel.CaseStatement pyVHDLModel.VHDLModel.EndlessLoopStatement pyVHDLModel.VHDLModel.ForLoopStatement pyVHDLModel.VHDLModel.WhileLoopStatement pyVHDLModel.VHDLModel.NextStatement pyVHDLModel.VHDLModel.ExitStatement pyVHDLModel.VHDLModel.SequentialProcedureCall pyVHDLModel.VHDLModel.WaitStatement pyVHDLModel.VHDLModel.ReturnStatement :parts: 1 .. _vhdlmodel-seq-assignments: @@ -39,6 +40,8 @@ Sequential Statements Assignments =========== + + .. _vhdlmodel-seq-signalassignment: Signal Assignment @@ -48,6 +51,8 @@ Signal Assignment Write documentation. + + .. _vhdlmodel-variableassignment: Variable Assignment @@ -57,6 +62,8 @@ Variable Assignment Write documentation. + + .. _vhdlmodel-branching: Branching @@ -71,6 +78,8 @@ If Statement Write documentation. + + .. _vhdlmodel-casestatement: Case Statement @@ -80,11 +89,22 @@ Case Statement Write documentation. + + .. _vhdlmodel-loops: Loops ===== +.. _vhdlmodel-endlessloop: + +Endless Loop +------------ + +.. todo:: + + Write documentation. + .. _vhdlmodel-forloop: For Loop @@ -94,6 +114,8 @@ For Loop Write documentation. + + .. _vhdlmodel-whileloop: While Loop @@ -103,6 +125,8 @@ While Loop Write documentation. + + .. _vhdlmodel-nextstatement: Next Statement @@ -136,6 +160,8 @@ Report Statement Write documentation. + + .. _vhdlmodel-seq-assertstatement: Assert Statement @@ -145,6 +171,8 @@ Assert Statement Write documentation. + + .. _vhdlmodel-seq-procedurecall: Procedure Call @@ -154,6 +182,8 @@ Procedure Call Write documentation. + + .. _vhdlmodel-waitstatement: Wait Statement diff --git a/pyVHDLModel/VHDLModel.py b/pyVHDLModel/VHDLModel.py index 328d7d956..b5daee26c 100644 --- a/pyVHDLModel/VHDLModel.py +++ b/pyVHDLModel/VHDLModel.py @@ -1504,7 +1504,7 @@ def PortItems(self) -> List[PortInterfaceItem]: @export class BaseConditional: """ - A ``BaseConditional`` is a base-class for all statements with a condition. + A ``BaseConditional`` is a mixin-class for all statements with a condition. """ _condition: Expression @@ -1806,11 +1806,16 @@ def __init__(self): @export -class Branch(ModelEntity): +class Branch(ModelEntity, SequentialStatements): """ A ``Branch`` is a base-class for all branches. """ + def __init__(self): + super().__init__() + SequentialStatements.__init__(self) + + @export class IfBranch(Branch, BaseIfBranch): def __init__(self): @@ -1833,14 +1838,13 @@ def __init__(self): @export -class CompoundStatement(SequentialStatement, SequentialStatements): +class CompoundStatement(SequentialStatement): """ A ``CompoundStatement`` is a base-class for all compound statements. """ def __init__(self): super().__init__() - SequentialStatements.__init__(self) @export @@ -1882,11 +1886,20 @@ def Cases(self) -> List[SequentialCase]: @export -class LoopStatement(CompoundStatement): +class LoopStatement(CompoundStatement, SequentialStatements): """ A ``LoopStatement`` is a base-class for all loop statements. """ + def __init__(self): + super().__init__() + SequentialStatements.__init__(self) + + +@export +class EndlessLoopStatement(LoopStatement): + pass + @export class ForLoopStatement(LoopStatement): From 3841333a5aea5e4ecef1f09f48e909934c017470 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Sun, 13 Jun 2021 00:47:11 +0200 Subject: [PATCH 34/39] More condensed views for return, next, exit and wait statements. --- doc/LanguageModel/SequentialStatements.rst | 97 ++++++++++++++++++++++ 1 file changed, 97 insertions(+) diff --git a/doc/LanguageModel/SequentialStatements.rst b/doc/LanguageModel/SequentialStatements.rst index 4752d6b30..8f77dbca0 100644 --- a/doc/LanguageModel/SequentialStatements.rst +++ b/doc/LanguageModel/SequentialStatements.rst @@ -136,6 +136,30 @@ Next Statement Write documentation. +**Condensed definition of class** :class:`~pyVHDLModel.VHDLModel.NextStatement`: + +.. code-block:: Python + + @export + class NextStatement(SequentialStatement, BaseConditional): + # inherited from ModelEntity + @property + def Parent(self) -> 'ModelEntity': + + # inherited from LabeledEntity + @property + def Label(self) -> str: + + # inherited from BaseCondition + @property + def Condition(self) -> Expression: + + # inherited from LoopControlStatement + @property + def LoopReference(self) -> LoopStatement: + + + .. _vhdlmodel-exitstatement: Exit Statement @@ -145,6 +169,30 @@ Exit Statement Write documentation. +**Condensed definition of class** :class:`~pyVHDLModel.VHDLModel.ExitStatement`: + +.. code-block:: Python + + @export + class ExitStatement(SequentialStatement, BaseConditional): + # inherited from ModelEntity + @property + def Parent(self) -> 'ModelEntity': + + # inherited from LabeledEntity + @property + def Label(self) -> str: + + # inherited from BaseCondition + @property + def Condition(self) -> Expression: + + # inherited from LoopControlStatement + @property + def LoopReference(self) -> LoopStatement: + + + .. _vhdlmodel-reporting: Reporting @@ -193,6 +241,33 @@ Wait Statement Write documentation. +**Condensed definition of class** :class:`~pyVHDLModel.VHDLModel.WaitStatement`: + +.. code-block:: Python + + @export + class WaitStatement(SequentialStatement, BaseConditional): + # inherited from ModelEntity + @property + def Parent(self) -> 'ModelEntity': + + # inherited from LabeledEntity + @property + def Label(self) -> str: + + # inherited from BaseCondition + @property + def Condition(self) -> Expression: + + # from WaitStatement + @property + def SensitivityList(self) -> List[Signal]: + + @property + def Timeout(self) -> Expression: + + + .. _vhdlmodel-returnstatement: Return Statement @@ -201,3 +276,25 @@ Return Statement .. todo:: Write documentation. + +**Condensed definition of class** :class:`~pyVHDLModel.VHDLModel.ReturnStatement`: + +.. code-block:: Python + + @export + class ReturnStatement(SequentialStatement, BaseConditional): + # inherited from ModelEntity + @property + def Parent(self) -> 'ModelEntity': + + # inherited from LabeledEntity + @property + def Label(self) -> str: + + # inherited from BaseCondition + @property + def Condition(self) -> Expression: + + # from ReturnStatement + @property + def ReturnValue(self) -> Expression: From 8297fe354cbfe04ac9d89173bb6a03f3a47ab2ae Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Sun, 13 Jun 2021 18:52:52 +0200 Subject: [PATCH 35/39] Partially documented sequential and concurrent statements. --- doc/LanguageModel/ConcurrentStatements.rst | 180 +++++++++++++++++++++ doc/LanguageModel/SequentialStatements.rst | 175 ++++++++++++++++++++ pyVHDLModel/VHDLModel.py | 4 +- 3 files changed, 357 insertions(+), 2 deletions(-) diff --git a/doc/LanguageModel/ConcurrentStatements.rst b/doc/LanguageModel/ConcurrentStatements.rst index 4c6124e58..96e0890f6 100644 --- a/doc/LanguageModel/ConcurrentStatements.rst +++ b/doc/LanguageModel/ConcurrentStatements.rst @@ -34,6 +34,33 @@ Assert Statement Write documentation. +**Condensed definition of class** :class:`~pyVHDLModel.VHDLModel.ConcurrentSignalAssignment`: + +.. code-block:: Python + + @export + class ConcurrentAssertStatement(ConcurrentStatement, AssertStatement): + # inherited from ModelEntity + @property + def Parent(self) -> 'ModelEntity': + + # inherited from LabeledEntity + @property + def Label(self) -> str: + + # inherited from ReportStatement + @property + def Message(self) -> Expression: + + @property + def Severity(self) -> Expression: + + # inherited from AssertStatement + @property + def Condition(self) -> Expression: + + + .. _vhdlmodel-con-signalassignment: Signal Assignment @@ -43,6 +70,29 @@ Signal Assignment Write documentation. +**Condensed definition of class** :class:`~pyVHDLModel.VHDLModel.ConcurrentSignalAssignment`: + +.. code-block:: Python + + @export + class ConcurrentSignalAssignment(ConcurrentStatement, SignalAssignment): + # inherited from ModelEntity + @property + def Parent(self) -> 'ModelEntity': + + # inherited from LabeledEntity + @property + def Label(self) -> str: + + # inherited from Assignment + @property + def Target(self) -> Object: + + @property + def Expression(self) -> Expression: + + + .. _vhdlmodel-con-blockstatement: Concurrent Block Statement @@ -52,6 +102,32 @@ Concurrent Block Statement Write documentation. +**Condensed definition of class** :class:`~pyVHDLModel.VHDLModel.ConcurrentBlockStatement`: + +.. code-block:: Python + + @export + class ConcurrentBlockStatement(ConcurrentStatement, BlockStatement, ConcurrentDeclarations, ConcurrentStatements): + # inherited from ModelEntity + @property + def Parent(self) -> 'ModelEntity': + + # inherited from LabeledEntity + @property + def Label(self) -> str: + + # inherited from ConcurrentDeclarations + @property + def DeclaredItems(self) -> List: + + # inherited from ConcurrentStatements + @property + def Statements(self) -> List[ConcurrentStatement]: + + # from ConcurrentBlockStatement + @property + def PortItems(self) -> List[PortInterfaceItem]: + .. _vhdlmodel-instantiations: Instantiations @@ -90,6 +166,32 @@ If Generate Write documentation. +**Condensed definition of class** :class:`~pyVHDLModel.VHDLModel.IfGenerateStatement`: + +.. code-block:: Python + + @export + class IfGenerateStatement(GenerateStatement): + # inherited from ModelEntity + @property + def Parent(self) -> 'ModelEntity': + + # inherited from LabeledEntity + @property + def Label(self) -> str: + + # from IfGenerateStatement + @property + def IfBranch(self) -> IfGenerateBranch: + + @property + def ElsifBranches(self) -> List[ElsifGenerateBranch]: + + @property + def ElseBranch(self) -> ElseGenerateBranch: + + + .. _vhdlmodel-casegenerate: Case Generate @@ -99,6 +201,29 @@ Case Generate Write documentation. +**Condensed definition of class** :class:`~pyVHDLModel.VHDLModel.CaseGenerateStatement`: + +.. code-block:: Python + + @export + class CaseGenerateStatement(GenerateStatement): + # inherited from ModelEntity + @property + def Parent(self) -> 'ModelEntity': + + # inherited from LabeledEntity + @property + def Label(self) -> str: + + # from CaseGenerateStatement + @property + def SelectExpression(self) -> Expression: + + @property + def Cases(self) -> List[ConcurrentCase]: + + + .. _vhdlmodel-forgenerate: For Generate @@ -108,6 +233,37 @@ For Generate Write documentation. +**Condensed definition of class** :class:`~pyVHDLModel.VHDLModel.ForGenerateStatement`: + +.. code-block:: Python + + @export + class ForGenerateStatement(GenerateStatement): + # inherited from ModelEntity + @property + def Parent(self) -> 'ModelEntity': + + # inherited from LabeledEntity + @property + def Label(self) -> str: + + # inherited from ConcurrentDeclarations + @property + def DeclaredItems(self) -> List: + + # inherited from ConcurrentStatements + @property + def Statements(self) -> List[ConcurrentStatement]: + + # from ForGenerateStatement + @property + def LoopIndex(self) -> Constant: + + @property + def Range(self) -> Range: + + + .. _vhdlmodel-con-procedurecall: Procedure Call @@ -126,3 +282,27 @@ Process Write documentation. +**Condensed definition of class** :class:`~pyVHDLModel.VHDLModel.ForGenerateStatement`: + +.. code-block:: Python + + class ProcessStatement(ConcurrentStatement, SequentialDeclarations, SequentialStatements): + # inherited from ModelEntity + @property + def Parent(self) -> 'ModelEntity': + + # inherited from LabeledEntity + @property + def Label(self) -> str: + + # inherited from SequentialDeclarations + @property + def DeclaredItems(self) -> List: + + # inherited from SequentialStatements + @property + def Statements(self) -> List[SequentialStatement]: + + # from ProcessStatement + @property + def SensitivityList(self) -> List[Signal]: diff --git a/doc/LanguageModel/SequentialStatements.rst b/doc/LanguageModel/SequentialStatements.rst index 8f77dbca0..3562457b1 100644 --- a/doc/LanguageModel/SequentialStatements.rst +++ b/doc/LanguageModel/SequentialStatements.rst @@ -51,6 +51,27 @@ Signal Assignment Write documentation. +**Condensed definition of class** :class:`~pyVHDLModel.VHDLModel.SequentialSignalAssignment`: + +.. code-block:: Python + + @export + class SequentialSignalAssignment(SequentialStatement, SignalAssignment): + # inherited from ModelEntity + @property + def Parent(self) -> 'ModelEntity': + + # inherited from LabeledEntity + @property + def Label(self) -> str: + + # inherited from Assignment + @property + def Target(self) -> Object: + + @property + def Expression(self) -> Expression: + .. _vhdlmodel-variableassignment: @@ -62,6 +83,27 @@ Variable Assignment Write documentation. +**Condensed definition of class** :class:`~pyVHDLModel.VHDLModel.SequentialVariableAssignment`: + +.. code-block:: Python + + @export + class SequentialVariableAssignment(SequentialStatement, VariableAssignment): + # inherited from ModelEntity + @property + def Parent(self) -> 'ModelEntity': + + # inherited from LabeledEntity + @property + def Label(self) -> str: + + # inherited from Assignment + @property + def Target(self) -> Object: + + @property + def Expression(self) -> Expression: + .. _vhdlmodel-branching: @@ -89,6 +131,27 @@ Case Statement Write documentation. +**Condensed definition of class** :class:`~pyVHDLModel.VHDLModel.CaseStatement`: + +.. code-block:: Python + + @export + class CaseStatement(CompoundStatement): + # inherited from ModelEntity + @property + def Parent(self) -> 'ModelEntity': + + # inherited from LabeledEntity + @property + def Label(self) -> str: + + # from CaseGenerateStatement + @property + def SelectExpression(self) -> Expression: + + @property + def Cases(self) -> List[SequentialCase]: + .. _vhdlmodel-loops: @@ -105,6 +168,26 @@ Endless Loop Write documentation. +**Condensed definition of class** :class:`~pyVHDLModel.VHDLModel.EndlessLoopStatement`: + +.. code-block:: Python + + @export + class EndlessLoopStatement(LoopStatement): + # inherited from ModelEntity + @property + def Parent(self) -> 'ModelEntity': + + # inherited from LabeledEntity + @property + def Label(self) -> str: + + # inherited from SequentialStatements + @property + def Statements(self) -> List[SequentialStatement]: + + + .. _vhdlmodel-forloop: For Loop @@ -114,6 +197,31 @@ For Loop Write documentation. +**Condensed definition of class** :class:`~pyVHDLModel.VHDLModel.ForLoopStatement`: + +.. code-block:: Python + + @export + class ForLoopStatement(LoopStatement): + # inherited from ModelEntity + @property + def Parent(self) -> 'ModelEntity': + + # inherited from LabeledEntity + @property + def Label(self) -> str: + + # inherited from SequentialStatements + @property + def Statements(self) -> List[SequentialStatement]: + + # from ForLoopStatement + @property + def LoopIndex(self) -> Constant: + + @property + def Range(self) -> Range: + .. _vhdlmodel-whileloop: @@ -125,6 +233,27 @@ While Loop Write documentation. +**Condensed definition of class** :class:`~pyVHDLModel.VHDLModel.WhileLoopStatement`: + +.. code-block:: Python + + @export + class WhileLoopStatement(LoopStatement, BaseConditional): + # inherited from ModelEntity + @property + def Parent(self) -> 'ModelEntity': + + # inherited from LabeledEntity + @property + def Label(self) -> str: + + # inherited from SequentialStatements + @property + def Statements(self) -> List[SequentialStatement]: + + # inherited from BaseConditional + @property + def Condition(self) -> Expression: .. _vhdlmodel-nextstatement: @@ -208,6 +337,27 @@ Report Statement Write documentation. +**Condensed definition of class** :class:`~pyVHDLModel.VHDLModel.SequentialReportStatement`: + +.. code-block:: Python + + @export + class SequentialReportStatement(SequentialStatement, ReportStatement): + # inherited from ModelEntity + @property + def Parent(self) -> 'ModelEntity': + + # inherited from LabeledEntity + @property + def Label(self) -> str: + + # inherited from ReportStatement + @property + def Message(self) -> Expression: + + @property + def Severity(self) -> Expression: + .. _vhdlmodel-seq-assertstatement: @@ -219,6 +369,31 @@ Assert Statement Write documentation. +**Condensed definition of class** :class:`~pyVHDLModel.VHDLModel.SequentialAssertStatement`: + +.. code-block:: Python + + @export + class SequentialAssertStatement(SequentialStatement, AssertStatement): + # inherited from ModelEntity + @property + def Parent(self) -> 'ModelEntity': + + # inherited from LabeledEntity + @property + def Label(self) -> str: + + # inherited from ReportStatement + @property + def Message(self) -> Expression: + + @property + def Severity(self) -> Expression: + + # inherited from AssertStatement + @property + def Condition(self) -> Expression: + .. _vhdlmodel-seq-procedurecall: diff --git a/pyVHDLModel/VHDLModel.py b/pyVHDLModel/VHDLModel.py index b5daee26c..8bc0525c8 100644 --- a/pyVHDLModel/VHDLModel.py +++ b/pyVHDLModel/VHDLModel.py @@ -1752,7 +1752,7 @@ def __init__(self): @export class ReportStatement: """ - A ``ReportStatement`` is a base-class for all report and assert statements. + A ``ReportStatement`` is a mixin-class for all report and assert statements. """ _message: Expression _severity: Expression @@ -1772,7 +1772,7 @@ def Severity(self) -> Expression: @export class AssertStatement(ReportStatement): """ - A ``AssertStatement`` is a base-class for all assert statements. + A ``AssertStatement`` is a mixin-class for all assert statements. """ _condition: Expression From 974e3024178e7dba7a0b4647aedc749611fdc224 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Sun, 13 Jun 2021 19:10:04 +0200 Subject: [PATCH 36/39] Some cleanup and refactoring. --- doc/LanguageModel/ConcurrentStatements.rst | 6 +- doc/LanguageModel/DesignUnits.rst | 36 +++---- doc/LanguageModel/Miscellaneous.rst | 55 +++++------ doc/LanguageModel/SequentialStatements.rst | 10 +- doc/LanguageModel/SubprogramDefinitions.rst | 24 ++--- doc/LanguageModel/TypeDefinitions.rst | 2 +- pyVHDLModel/VHDLModel.py | 102 ++++++++++---------- 7 files changed, 114 insertions(+), 121 deletions(-) diff --git a/doc/LanguageModel/ConcurrentStatements.rst b/doc/LanguageModel/ConcurrentStatements.rst index 96e0890f6..b8bf712c6 100644 --- a/doc/LanguageModel/ConcurrentStatements.rst +++ b/doc/LanguageModel/ConcurrentStatements.rst @@ -39,7 +39,7 @@ Assert Statement .. code-block:: Python @export - class ConcurrentAssertStatement(ConcurrentStatement, AssertStatement): + class ConcurrentAssertStatement(ConcurrentStatement, MixinAssertStatement): # inherited from ModelEntity @property def Parent(self) -> 'ModelEntity': @@ -48,14 +48,14 @@ Assert Statement @property def Label(self) -> str: - # inherited from ReportStatement + # inherited from MixinReportStatement @property def Message(self) -> Expression: @property def Severity(self) -> Expression: - # inherited from AssertStatement + # inherited from MixinAssertStatement @property def Condition(self) -> Expression: diff --git a/doc/LanguageModel/DesignUnits.rst b/doc/LanguageModel/DesignUnits.rst index 975fa8962..66d543c10 100644 --- a/doc/LanguageModel/DesignUnits.rst +++ b/doc/LanguageModel/DesignUnits.rst @@ -69,7 +69,7 @@ types). An entity's list of statements is called body items. .. code-block:: Python @export - class Entity(PrimaryUnit, DesignUnitWithContext): + class Entity(PrimaryUnit, MixinDesignUnitWithContext): # inherited from ModelEntity @property def Parent(self) -> 'ModelEntity': @@ -78,15 +78,15 @@ types). An entity's list of statements is called body items. @property def Name(self) -> str: - # inherited from DesignUnitWithContext + # inherited from MixinDesignUnitWithContext @property - def LibraryReferences(self) -> List[LibraryReference]: + def LibraryReferences(self) -> List[Library]: @property def PackageReferences(self) -> List[PackageReference]: @property - def ContextReferences(self) -> List[ContextReference]: + def ContextReferences(self) -> List[Context]: # from Entity def __init__(self, name: str): @@ -101,7 +101,7 @@ types). An entity's list of statements is called body items. def DeclaredItems(self) -> List: @property - def BodyItems(self) -> List['ConcurrentStatement']: + def BodyItems(self) -> List[ConcurrentStatement]: @@ -119,7 +119,7 @@ Package .. code-block:: Python @export - class Package(PrimaryUnit, DesignUnitWithContext): + class Package(PrimaryUnit, MixinDesignUnitWithContext): # inherited from ModelEntity @property def Parent(self) -> 'ModelEntity': @@ -128,15 +128,15 @@ Package @property def Name(self) -> str: - # inherited from DesignUnitWithContext + # inherited from MixinDesignUnitWithContext @property - def LibraryReferences(self) -> List[LibraryReference]: + def LibraryReferences(self) -> List[Library]: @property def PackageReferences(self) -> List[PackageReference]: @property - def ContextReferences(self) -> List[ContextReference]: + def ContextReferences(self) -> List[Context]: # from Package def __init__(self, name: str): @@ -168,7 +168,7 @@ Architeture .. code-block:: Python @export - class Architecture(SecondaryUnit, DesignUnitWithContext): + class Architecture(SecondaryUnit, MixinDesignUnitWithContext): # inherited from ModelEntity @property def Parent(self) -> 'ModelEntity': @@ -177,15 +177,15 @@ Architeture @property def Name(self) -> str: - # inherited from DesignUnitWithContext + # inherited from MixinDesignUnitWithContext @property - def LibraryReferences(self) -> List[LibraryReference]: + def LibraryReferences(self) -> List[Library]: @property def PackageReferences(self) -> List[PackageReference]: @property - def ContextReferences(self) -> List[ContextReference]: + def ContextReferences(self) -> List[Context]: # from Architecture def __init__(self, name: str): @@ -197,7 +197,7 @@ Architeture def DeclaredItems(self) -> List: @property - def BodyItems(self) -> List['ConcurrentStatement']: + def BodyItems(self) -> List[ConcurrentStatement]: @@ -215,7 +215,7 @@ Package Body .. code-block:: Python @export - class PackageBody(SecondaryUnit, DesignUnitWithContext): + class PackageBody(SecondaryUnit, MixinDesignUnitWithContext): # inherited from ModelEntity @property def Parent(self) -> 'ModelEntity': @@ -224,15 +224,15 @@ Package Body @property def Name(self) -> str: - # inherited from DesignUnitWithContext + # inherited from MixinDesignUnitWithContext @property - def LibraryReferences(self) -> List[LibraryReference]: + def LibraryReferences(self) -> List[Library]: @property def PackageReferences(self) -> List[PackageReference]: @property - def ContextReferences(self) -> List[ContextReference]: + def ContextReferences(self) -> List[Context]: # from Package Body def __init__(self, name: str): diff --git a/doc/LanguageModel/Miscellaneous.rst b/doc/LanguageModel/Miscellaneous.rst index 9703a0f38..aa576f024 100644 --- a/doc/LanguageModel/Miscellaneous.rst +++ b/doc/LanguageModel/Miscellaneous.rst @@ -30,16 +30,16 @@ a design has the two child nodes: ``Libraries`` and ``Documents``. Each is a @export class Design(ModelEntity): - _libraries: List['Library'] #: List of all libraries defined for a design - _documents: List['Document'] #: List of all documents loaded for a design - - def __init__(self): + # inherited from ModelEntity + @property + def Parent(self) -> 'ModelEntity': + # from Design @property - def Libraries(self) -> List['Library']: + def Libraries(self) -> List[Library]: @property - def Documents(self) -> List['Document']: + def Documents(self) -> List[Document]: @@ -58,24 +58,22 @@ is a *primary* design unit like: ``configuration``, ``entity``, ``package`` or @export class Library(ModelEntity): - _contexts: List['Context'] #: List of all contexts defined in a library. - _configurations: List['Configuration'] #: List of all configurations defined in a library. - _entities: List['Entity'] #: List of all entities defined in a library. - _packages: List['Package'] #: List of all packages defined in a library. - - def __init__(self): + # inherited from ModelEntity + @property + def Parent(self) -> 'ModelEntity': + # from Library @property - def Contexts(self) -> List['Context']: + def Contexts(self) -> List[Context]: @property - def Configurations(self) -> List['Configuration']: + def Configurations(self) -> List[Configuration]: @property - def Entities(self) -> List['Entity']: + def Entities(self) -> List[Entity]: @property - def Packages(self) -> List['Package']: + def Packages(self) -> List[Package]: @@ -101,33 +99,28 @@ investigate the consumed contexts. @export class Document(ModelEntity): - _path: Path #: path to the document. ``None`` if virtual document. - _contexts: List['Context'] #: List of all contexts defined in a document. - _configurations: List['Configuration'] #: List of all configurations defined in a document. - _entities: List['Entity'] #: List of all entities defined in a document. - _architectures: List['Architecture'] #: List of all architectures defined in a document. - _packages: List['Package'] #: List of all packages defined in a document. - _packageBodies: List['PackageBody'] #: List of all package bodies defined in a document. - - def __init__(self, path: Path): + # inherited from ModelEntity + @property + def Parent(self) -> 'ModelEntity': + # from Document @property def Path(self) -> Path: @property - def Contexts(self) -> List['Context']: + def Contexts(self) -> List[Context]: @property - def Configurations(self) -> List['Configuration']: + def Configurations(self) -> List[Configuration]: @property - def Entities(self) -> List['Entity']: + def Entities(self) -> List[Entity]: @property - def Architectures(self) -> List['Architecture']: + def Architectures(self) -> List[Architecture]: @property - def Packages(self) -> List['Package']: + def Packages(self) -> List[Package]: @property - def PackageBodies(self) -> List['PackageBody']: + def PackageBodies(self) -> List[PackageBody]: diff --git a/doc/LanguageModel/SequentialStatements.rst b/doc/LanguageModel/SequentialStatements.rst index 3562457b1..8a9db81cd 100644 --- a/doc/LanguageModel/SequentialStatements.rst +++ b/doc/LanguageModel/SequentialStatements.rst @@ -342,7 +342,7 @@ Report Statement .. code-block:: Python @export - class SequentialReportStatement(SequentialStatement, ReportStatement): + class SequentialReportStatement(SequentialStatement, MixinReportStatement): # inherited from ModelEntity @property def Parent(self) -> 'ModelEntity': @@ -351,7 +351,7 @@ Report Statement @property def Label(self) -> str: - # inherited from ReportStatement + # inherited from MixinReportStatement @property def Message(self) -> Expression: @@ -374,7 +374,7 @@ Assert Statement .. code-block:: Python @export - class SequentialAssertStatement(SequentialStatement, AssertStatement): + class SequentialAssertStatement(SequentialStatement, MixinAssertStatement): # inherited from ModelEntity @property def Parent(self) -> 'ModelEntity': @@ -383,14 +383,14 @@ Assert Statement @property def Label(self) -> str: - # inherited from ReportStatement + # inherited from MixinReportStatement @property def Message(self) -> Expression: @property def Severity(self) -> Expression: - # inherited from AssertStatement + # inherited from MixinAssertStatement @property def Condition(self) -> Expression: diff --git a/doc/LanguageModel/SubprogramDefinitions.rst b/doc/LanguageModel/SubprogramDefinitions.rst index 615b6d49c..ff09f70ed 100644 --- a/doc/LanguageModel/SubprogramDefinitions.rst +++ b/doc/LanguageModel/SubprogramDefinitions.rst @@ -54,16 +54,16 @@ Procedure def __init__(self, name: str): @property - def GenericItems(self) -> List['GenericInterfaceItem']: + def GenericItems(self) -> List[GenericInterfaceItem]: @property - def ParameterItems(self) -> List['ParameterInterfaceItem']: + def ParameterItems(self) -> List[ParameterInterfaceItem]: @property def DeclaredItems(self) -> List: @property - def BodyItems(self) -> List['SequentialStatement']: + def BodyItems(self) -> List[SequentialStatement]: @property def IsPure(self) -> bool: @@ -104,16 +104,16 @@ Procedure as Method def __init__(self, name: str): @property - def GenericItems(self) -> List['GenericInterfaceItem']: + def GenericItems(self) -> List[GenericInterfaceItem]: @property - def ParameterItems(self) -> List['ParameterInterfaceItem']: + def ParameterItems(self) -> List[ParameterInterfaceItem]: @property def DeclaredItems(self) -> List: @property - def BodyItems(self) -> List['SequentialStatement']: + def BodyItems(self) -> List[SequentialStatement]: @property def IsPure(self) -> bool: @@ -171,16 +171,16 @@ Function # inherited from Subprogram @property - def GenericItems(self) -> List['GenericInterfaceItem']: + def GenericItems(self) -> List[GenericInterfaceItem]: @property - def ParameterItems(self) -> List['ParameterInterfaceItem']: + def ParameterItems(self) -> List[ParameterInterfaceItem]: @property def DeclaredItems(self) -> List: @property - def BodyItems(self) -> List['SequentialStatement']: + def BodyItems(self) -> List[SequentialStatement]: @property def IsPure(self) -> bool: @@ -225,16 +225,16 @@ Function as Method # inherited from Subprogram @property - def GenericItems(self) -> List['GenericInterfaceItem']: + def GenericItems(self) -> List[GenericInterfaceItem]: @property - def ParameterItems(self) -> List['ParameterInterfaceItem']: + def ParameterItems(self) -> List[ParameterInterfaceItem]: @property def DeclaredItems(self) -> List: @property - def BodyItems(self) -> List['SequentialStatement']: + def BodyItems(self) -> List[SequentialStatement]: @property def IsPure(self) -> bool: diff --git a/doc/LanguageModel/TypeDefinitions.rst b/doc/LanguageModel/TypeDefinitions.rst index 28f0870ab..61f9afb76 100644 --- a/doc/LanguageModel/TypeDefinitions.rst +++ b/doc/LanguageModel/TypeDefinitions.rst @@ -200,7 +200,7 @@ Array # from ArrayType @property - def Dimensions(self) -> List['Range']: + def Dimensions(self) -> List[Range]: @property def ElementType(self) -> SubType: diff --git a/pyVHDLModel/VHDLModel.py b/pyVHDLModel/VHDLModel.py index 8bc0525c8..17c21ee96 100644 --- a/pyVHDLModel/VHDLModel.py +++ b/pyVHDLModel/VHDLModel.py @@ -1120,13 +1120,13 @@ def __init__(self, name: str): NamedEntity.__init__(self, name)\ @export -class DesignUnitWithContext: +class MixinDesignUnitWithContext: """ A ``DesignUnitWithReferences`` is a base-class for all design units with contexts. """ - _libraryReferences: List[LibraryReference] + _libraryReferences: List[Library] _packageReferences: List[PackageReference] - _contextReferences: List[ContextReference] + _contextReferences: List['Context'] def __init__(self): self._libraryReferences = [] @@ -1142,7 +1142,7 @@ def PackageReferences(self) -> List[PackageReference]: return self._packageReferences @property - def ContextReferences(self) -> List[ContextReference]: + def ContextReferences(self) -> List['Context']: return self._contextReferences @@ -1181,7 +1181,7 @@ def PackageReferences(self) -> List[PackageReference]: @export -class Entity(PrimaryUnit, DesignUnitWithContext): +class Entity(PrimaryUnit, MixinDesignUnitWithContext): _genericItems: List[GenericInterfaceItem] _portItems: List[PortInterfaceItem] _declaredItems: List # FIXME: define list element type e.g. via Union @@ -1189,7 +1189,7 @@ class Entity(PrimaryUnit, DesignUnitWithContext): def __init__(self, name: str): super().__init__(name) - DesignUnitWithContext.__init__(self) + MixinDesignUnitWithContext.__init__(self) self._genericItems = [] self._portItems = [] @@ -1214,14 +1214,14 @@ def BodyItems(self) -> List['ConcurrentStatement']: @export -class Architecture(SecondaryUnit, DesignUnitWithContext): +class Architecture(SecondaryUnit, MixinDesignUnitWithContext): _entity: Entity _declaredItems: List # FIXME: define list element type e.g. via Union _bodyItems: List['ConcurrentStatement'] def __init__(self, name: str): super().__init__(name) - DesignUnitWithContext.__init__(self) + MixinDesignUnitWithContext.__init__(self) self._declaredItems = [] self._bodyItems = [] @@ -1240,10 +1240,10 @@ def BodyItems(self) -> List['ConcurrentStatement']: @export -class Configuration(PrimaryUnit, DesignUnitWithContext): +class Configuration(PrimaryUnit, MixinDesignUnitWithContext): def __init__(self, name: str): super().__init__(name) - DesignUnitWithContext.__init__(self) + MixinDesignUnitWithContext.__init__(self) @export @@ -1302,13 +1302,13 @@ class FunctionInstantiation(Function, SubprogramInstantiation): @export -class Package(PrimaryUnit, DesignUnitWithContext): +class Package(PrimaryUnit, MixinDesignUnitWithContext): _genericItems: List[GenericInterfaceItem] _declaredItems: List def __init__(self, name: str): super().__init__(name) - DesignUnitWithContext.__init__(self) + MixinDesignUnitWithContext.__init__(self) self._genericItems = [] self._declaredItems = [] @@ -1323,13 +1323,13 @@ def DeclaredItems(self) -> List: @export -class PackageBody(SecondaryUnit, DesignUnitWithContext): +class PackageBody(SecondaryUnit, MixinDesignUnitWithContext): _package: Package _declaredItems: List def __init__(self, name: str): super().__init__(name) - DesignUnitWithContext.__init__(self) + MixinDesignUnitWithContext.__init__(self) self._declaredItems = [] @@ -1502,7 +1502,7 @@ def PortItems(self) -> List[PortInterfaceItem]: @export -class BaseConditional: +class MixinConditional: """ A ``BaseConditional`` is a mixin-class for all statements with a condition. """ @@ -1514,38 +1514,38 @@ def Condition(self) -> Expression: @export -class BaseBranch: +class MixinBranch: """ A ``BaseBranch`` is a mixin-class for all statements with branches. """ @export -class BaseConditionalBranch(BaseBranch, BaseConditional): +class MixinConditionalBranch(MixinBranch, MixinConditional): """ A ``BaseBranch`` is a mixin-class for all branch statements with a condition. """ def __init__(self): super().__init__() - BaseConditional.__init__(self) + MixinConditional.__init__(self) @export -class BaseIfBranch(BaseConditionalBranch): +class MixinIfBranch(MixinConditionalBranch): """ A ``BaseIfBranch`` is a mixin-class for all if-branches. """ @export -class BaseElsifBranch(BaseConditionalBranch): +class MixinElsifBranch(MixinConditionalBranch): """ A ``BaseElsifBranch`` is a mixin-class for all elsif-branches. """ @export -class BaseElseBranch(BaseBranch): +class MixinElseBranch(MixinBranch): """ A ``BaseElseBranch`` is a mixin-class for all else-branches. """ @@ -1564,24 +1564,24 @@ def __init__(self): @export -class IfGenerateBranch(GenerateBranch, BaseIfBranch): +class IfGenerateBranch(GenerateBranch, MixinIfBranch): def __init__(self): super().__init__() - BaseIfBranch.__init__(self) + MixinIfBranch.__init__(self) @export -class ElsifGenerateBranch(GenerateBranch, BaseElsifBranch): +class ElsifGenerateBranch(GenerateBranch, MixinElsifBranch): def __init__(self): super().__init__() - BaseElsifBranch.__init__(self) + MixinElsifBranch.__init__(self) @export -class ElseGenerateBranch(GenerateBranch, BaseElseBranch): +class ElseGenerateBranch(GenerateBranch, MixinElseBranch): def __init__(self): super().__init__() - BaseElseBranch.__init__(self) + MixinElseBranch.__init__(self) @export @@ -1750,9 +1750,9 @@ def __init__(self): @export -class ReportStatement: +class MixinReportStatement: """ - A ``ReportStatement`` is a mixin-class for all report and assert statements. + A ``MixinReportStatement`` is a mixin-class for all report and assert statements. """ _message: Expression _severity: Expression @@ -1770,9 +1770,9 @@ def Severity(self) -> Expression: @export -class AssertStatement(ReportStatement): +class MixinAssertStatement(MixinReportStatement): """ - A ``AssertStatement`` is a mixin-class for all assert statements. + A ``MixinAssertStatement`` is a mixin-class for all assert statements. """ _condition: Expression @@ -1785,24 +1785,24 @@ def Condition(self) -> Expression: @export -class ConcurrentAssertStatement(ConcurrentStatement, AssertStatement): +class ConcurrentAssertStatement(ConcurrentStatement, MixinAssertStatement): def __init__(self, label: str = None): super().__init__(label=label) - AssertStatement.__init__(self) + MixinAssertStatement.__init__(self) @export -class SequentialReportStatement(SequentialStatement, ReportStatement): +class SequentialReportStatement(SequentialStatement, MixinReportStatement): def __init__(self): super().__init__() - ReportStatement.__init__(self) + MixinReportStatement.__init__(self) @export -class SequentialAssertStatement(SequentialStatement, AssertStatement): +class SequentialAssertStatement(SequentialStatement, MixinAssertStatement): def __init__(self): super().__init__() - AssertStatement.__init__(self) + MixinAssertStatement.__init__(self) @export @@ -1817,24 +1817,24 @@ def __init__(self): @export -class IfBranch(Branch, BaseIfBranch): +class IfBranch(Branch, MixinIfBranch): def __init__(self): super().__init__() - BaseIfBranch.__init__(self) + MixinIfBranch.__init__(self) @export -class ElsifBranch(Branch, BaseElsifBranch): +class ElsifBranch(Branch, MixinElsifBranch): def __init__(self): super().__init__() - BaseElsifBranch.__init__(self) + MixinElsifBranch.__init__(self) @export -class ElseBranch(Branch, BaseElseBranch): +class ElseBranch(Branch, MixinElseBranch): def __init__(self): super().__init__() - BaseElseBranch.__init__(self) + MixinElseBranch.__init__(self) @export @@ -1919,14 +1919,14 @@ def Range(self) -> Range: @export -class WhileLoopStatement(LoopStatement, BaseConditional): +class WhileLoopStatement(LoopStatement, MixinConditional): def __init__(self): super().__init__() - BaseConditional.__init__(self) + MixinConditional.__init__(self) @export -class LoopControlStatement(SequentialStatement, BaseConditional): +class LoopControlStatement(SequentialStatement, MixinConditional): """ A ``LoopControlStatement`` is a base-class for all loop controlling statements. """ @@ -1934,7 +1934,7 @@ class LoopControlStatement(SequentialStatement, BaseConditional): def __init__(self): super().__init__() - BaseConditional.__init__(self) + MixinConditional.__init__(self) @property def LoopReference(self) -> LoopStatement: @@ -1952,13 +1952,13 @@ class ExitStatement(LoopControlStatement): @export -class WaitStatement(SequentialStatement, BaseConditional): +class WaitStatement(SequentialStatement, MixinConditional): _sensitivityList : List[Signal] _timeout: Expression def __init__(self): super().__init__() - BaseConditional.__init__(self) + MixinConditional.__init__(self) @property def SensitivityList(self) -> List[Signal]: @@ -1970,12 +1970,12 @@ def Timeout(self) -> Expression: @export -class ReturnStatement(SequentialStatement, BaseConditional): +class ReturnStatement(SequentialStatement, MixinConditional): _returnValue: Expression def __init__(self): super().__init__() - BaseConditional.__init__(self) + MixinConditional.__init__(self) @property def ReturnValue(self) -> Expression: From 3d275410e9b951c0cfbfcdde095d976994a64f86 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Sun, 13 Jun 2021 19:14:51 +0200 Subject: [PATCH 37/39] More cleanup. --- doc/LanguageModel/ConcurrentStatements.rst | 14 ++++++------ doc/LanguageModel/DesignUnits.rst | 16 ++++---------- doc/LanguageModel/InterfaceItems.rst | 10 ++++----- doc/LanguageModel/Miscellaneous.rst | 6 +++--- doc/LanguageModel/ObjectDeclarations.rst | 8 +++---- doc/LanguageModel/SequentialStatements.rst | 24 ++++++++++----------- doc/LanguageModel/SubprogramDefinitions.rst | 22 ++++--------------- doc/LanguageModel/TypeDefinitions.rst | 12 +++++------ 8 files changed, 45 insertions(+), 67 deletions(-) diff --git a/doc/LanguageModel/ConcurrentStatements.rst b/doc/LanguageModel/ConcurrentStatements.rst index b8bf712c6..fa4e43ed5 100644 --- a/doc/LanguageModel/ConcurrentStatements.rst +++ b/doc/LanguageModel/ConcurrentStatements.rst @@ -42,7 +42,7 @@ Assert Statement class ConcurrentAssertStatement(ConcurrentStatement, MixinAssertStatement): # inherited from ModelEntity @property - def Parent(self) -> 'ModelEntity': + def Parent(self) -> ModelEntity: # inherited from LabeledEntity @property @@ -78,7 +78,7 @@ Signal Assignment class ConcurrentSignalAssignment(ConcurrentStatement, SignalAssignment): # inherited from ModelEntity @property - def Parent(self) -> 'ModelEntity': + def Parent(self) -> ModelEntity: # inherited from LabeledEntity @property @@ -110,7 +110,7 @@ Concurrent Block Statement class ConcurrentBlockStatement(ConcurrentStatement, BlockStatement, ConcurrentDeclarations, ConcurrentStatements): # inherited from ModelEntity @property - def Parent(self) -> 'ModelEntity': + def Parent(self) -> ModelEntity: # inherited from LabeledEntity @property @@ -174,7 +174,7 @@ If Generate class IfGenerateStatement(GenerateStatement): # inherited from ModelEntity @property - def Parent(self) -> 'ModelEntity': + def Parent(self) -> ModelEntity: # inherited from LabeledEntity @property @@ -209,7 +209,7 @@ Case Generate class CaseGenerateStatement(GenerateStatement): # inherited from ModelEntity @property - def Parent(self) -> 'ModelEntity': + def Parent(self) -> ModelEntity: # inherited from LabeledEntity @property @@ -241,7 +241,7 @@ For Generate class ForGenerateStatement(GenerateStatement): # inherited from ModelEntity @property - def Parent(self) -> 'ModelEntity': + def Parent(self) -> ModelEntity: # inherited from LabeledEntity @property @@ -289,7 +289,7 @@ Process class ProcessStatement(ConcurrentStatement, SequentialDeclarations, SequentialStatements): # inherited from ModelEntity @property - def Parent(self) -> 'ModelEntity': + def Parent(self) -> ModelEntity: # inherited from LabeledEntity @property diff --git a/doc/LanguageModel/DesignUnits.rst b/doc/LanguageModel/DesignUnits.rst index 66d543c10..4883240b6 100644 --- a/doc/LanguageModel/DesignUnits.rst +++ b/doc/LanguageModel/DesignUnits.rst @@ -72,7 +72,7 @@ types). An entity's list of statements is called body items. class Entity(PrimaryUnit, MixinDesignUnitWithContext): # inherited from ModelEntity @property - def Parent(self) -> 'ModelEntity': + def Parent(self) -> ModelEntity: # inherited from NamedEntity @property @@ -89,8 +89,6 @@ types). An entity's list of statements is called body items. def ContextReferences(self) -> List[Context]: # from Entity - def __init__(self, name: str): - @property def GenericItems(self) -> List[GenericInterfaceItem]: @@ -122,7 +120,7 @@ Package class Package(PrimaryUnit, MixinDesignUnitWithContext): # inherited from ModelEntity @property - def Parent(self) -> 'ModelEntity': + def Parent(self) -> ModelEntity: # inherited from NamedEntity @property @@ -139,8 +137,6 @@ Package def ContextReferences(self) -> List[Context]: # from Package - def __init__(self, name: str): - @property def GenericItems(self) -> List[GenericInterfaceItem]: @@ -171,7 +167,7 @@ Architeture class Architecture(SecondaryUnit, MixinDesignUnitWithContext): # inherited from ModelEntity @property - def Parent(self) -> 'ModelEntity': + def Parent(self) -> ModelEntity: # inherited from NamedEntity @property @@ -188,8 +184,6 @@ Architeture def ContextReferences(self) -> List[Context]: # from Architecture - def __init__(self, name: str): - @property def Entity(self) -> Entity: @@ -218,7 +212,7 @@ Package Body class PackageBody(SecondaryUnit, MixinDesignUnitWithContext): # inherited from ModelEntity @property - def Parent(self) -> 'ModelEntity': + def Parent(self) -> ModelEntity: # inherited from NamedEntity @property @@ -235,8 +229,6 @@ Package Body def ContextReferences(self) -> List[Context]: # from Package Body - def __init__(self, name: str): - @property def Package(self) -> Package: diff --git a/doc/LanguageModel/InterfaceItems.rst b/doc/LanguageModel/InterfaceItems.rst index de7cd60d8..c36a0c832 100644 --- a/doc/LanguageModel/InterfaceItems.rst +++ b/doc/LanguageModel/InterfaceItems.rst @@ -54,7 +54,7 @@ GenericConstantInterfaceItem class GenericConstantInterfaceItem(Constant, GenericInterfaceItem): # inherited from ModelEntity @property - def Parent(self) -> 'ModelEntity': + def Parent(self) -> ModelEntity: # inherited from NamedEntity @property @@ -166,7 +166,7 @@ PortSignalInterfaceItem class PortSignalInterfaceItem(Signal, PortInterfaceItem): # inherited from ModelEntity @property - def Parent(self) -> 'ModelEntity': + def Parent(self) -> ModelEntity: # inherited from NamedEntity @property @@ -208,7 +208,7 @@ ParameterConstantInterfaceItem class ParameterConstantInterfaceItem(Constant, ParameterInterfaceItem): # inherited from ModelEntity @property - def Parent(self) -> 'ModelEntity': + def Parent(self) -> ModelEntity: # inherited from NamedEntity @property @@ -245,7 +245,7 @@ ParameterVariableInterfaceItem class ParameterVariableInterfaceItem(Variable, ParameterInterfaceItem): # inherited from ModelEntity @property - def Parent(self) -> 'ModelEntity': + def Parent(self) -> ModelEntity: # inherited from NamedEntity @property @@ -282,7 +282,7 @@ ParameterSignalInterfaceItem class ParameterSignalInterfaceItem(Signal, ParameterInterfaceItem): # inherited from ModelEntity @property - def Parent(self) -> 'ModelEntity': + def Parent(self) -> ModelEntity: # inherited from NamedEntity @property diff --git a/doc/LanguageModel/Miscellaneous.rst b/doc/LanguageModel/Miscellaneous.rst index aa576f024..f58518b43 100644 --- a/doc/LanguageModel/Miscellaneous.rst +++ b/doc/LanguageModel/Miscellaneous.rst @@ -32,7 +32,7 @@ a design has the two child nodes: ``Libraries`` and ``Documents``. Each is a class Design(ModelEntity): # inherited from ModelEntity @property - def Parent(self) -> 'ModelEntity': + def Parent(self) -> ModelEntity: # from Design @property @@ -60,7 +60,7 @@ is a *primary* design unit like: ``configuration``, ``entity``, ``package`` or class Library(ModelEntity): # inherited from ModelEntity @property - def Parent(self) -> 'ModelEntity': + def Parent(self) -> ModelEntity: # from Library @property @@ -101,7 +101,7 @@ investigate the consumed contexts. class Document(ModelEntity): # inherited from ModelEntity @property - def Parent(self) -> 'ModelEntity': + def Parent(self) -> ModelEntity: # from Document @property diff --git a/doc/LanguageModel/ObjectDeclarations.rst b/doc/LanguageModel/ObjectDeclarations.rst index cf2ba1c77..c1d1bf883 100644 --- a/doc/LanguageModel/ObjectDeclarations.rst +++ b/doc/LanguageModel/ObjectDeclarations.rst @@ -63,7 +63,7 @@ a deferred constant. See :ref:`vhdlmodel-deferredconstant` in next section. class Constant(BaseConstant): # inherited from ModelEntity @property - def Parent(self) -> 'ModelEntity': + def Parent(self) -> ModelEntity: # inherited from NamedEntity @property @@ -94,7 +94,7 @@ a deferred constant has a reference to the *regular* constant of the same name. class DeferredConstant(BaseConstant): # inherited from ModelEntity @property - def Parent(self) -> 'ModelEntity': + def Parent(self) -> ModelEntity: # inherited from NamedEntity @property @@ -159,7 +159,7 @@ expression. class Variable(Object): # inherited from ModelEntity @property - def Parent(self) -> 'ModelEntity': + def Parent(self) -> ModelEntity: # inherited from NamedEntity @property @@ -221,7 +221,7 @@ assigned via a default expression. class Signal(Object): # inherited from ModelEntity @property - def Parent(self) -> 'ModelEntity': + def Parent(self) -> ModelEntity: # inherited from NamedEntity @property diff --git a/doc/LanguageModel/SequentialStatements.rst b/doc/LanguageModel/SequentialStatements.rst index 8a9db81cd..f75f3ac36 100644 --- a/doc/LanguageModel/SequentialStatements.rst +++ b/doc/LanguageModel/SequentialStatements.rst @@ -59,7 +59,7 @@ Signal Assignment class SequentialSignalAssignment(SequentialStatement, SignalAssignment): # inherited from ModelEntity @property - def Parent(self) -> 'ModelEntity': + def Parent(self) -> ModelEntity: # inherited from LabeledEntity @property @@ -91,7 +91,7 @@ Variable Assignment class SequentialVariableAssignment(SequentialStatement, VariableAssignment): # inherited from ModelEntity @property - def Parent(self) -> 'ModelEntity': + def Parent(self) -> ModelEntity: # inherited from LabeledEntity @property @@ -139,7 +139,7 @@ Case Statement class CaseStatement(CompoundStatement): # inherited from ModelEntity @property - def Parent(self) -> 'ModelEntity': + def Parent(self) -> ModelEntity: # inherited from LabeledEntity @property @@ -176,7 +176,7 @@ Endless Loop class EndlessLoopStatement(LoopStatement): # inherited from ModelEntity @property - def Parent(self) -> 'ModelEntity': + def Parent(self) -> ModelEntity: # inherited from LabeledEntity @property @@ -205,7 +205,7 @@ For Loop class ForLoopStatement(LoopStatement): # inherited from ModelEntity @property - def Parent(self) -> 'ModelEntity': + def Parent(self) -> ModelEntity: # inherited from LabeledEntity @property @@ -241,7 +241,7 @@ While Loop class WhileLoopStatement(LoopStatement, BaseConditional): # inherited from ModelEntity @property - def Parent(self) -> 'ModelEntity': + def Parent(self) -> ModelEntity: # inherited from LabeledEntity @property @@ -273,7 +273,7 @@ Next Statement class NextStatement(SequentialStatement, BaseConditional): # inherited from ModelEntity @property - def Parent(self) -> 'ModelEntity': + def Parent(self) -> ModelEntity: # inherited from LabeledEntity @property @@ -306,7 +306,7 @@ Exit Statement class ExitStatement(SequentialStatement, BaseConditional): # inherited from ModelEntity @property - def Parent(self) -> 'ModelEntity': + def Parent(self) -> ModelEntity: # inherited from LabeledEntity @property @@ -345,7 +345,7 @@ Report Statement class SequentialReportStatement(SequentialStatement, MixinReportStatement): # inherited from ModelEntity @property - def Parent(self) -> 'ModelEntity': + def Parent(self) -> ModelEntity: # inherited from LabeledEntity @property @@ -377,7 +377,7 @@ Assert Statement class SequentialAssertStatement(SequentialStatement, MixinAssertStatement): # inherited from ModelEntity @property - def Parent(self) -> 'ModelEntity': + def Parent(self) -> ModelEntity: # inherited from LabeledEntity @property @@ -424,7 +424,7 @@ Wait Statement class WaitStatement(SequentialStatement, BaseConditional): # inherited from ModelEntity @property - def Parent(self) -> 'ModelEntity': + def Parent(self) -> ModelEntity: # inherited from LabeledEntity @property @@ -460,7 +460,7 @@ Return Statement class ReturnStatement(SequentialStatement, BaseConditional): # inherited from ModelEntity @property - def Parent(self) -> 'ModelEntity': + def Parent(self) -> ModelEntity: # inherited from LabeledEntity @property diff --git a/doc/LanguageModel/SubprogramDefinitions.rst b/doc/LanguageModel/SubprogramDefinitions.rst index ff09f70ed..7cb12dbdb 100644 --- a/doc/LanguageModel/SubprogramDefinitions.rst +++ b/doc/LanguageModel/SubprogramDefinitions.rst @@ -44,15 +44,13 @@ Procedure class Procedure(SubProgramm): # inherited from ModelEntity @property - def Parent(self) -> 'ModelEntity': + def Parent(self) -> ModelEntity: # inherited from NamedEntity @property def Name(self) -> str: # inherited from Subprogram - def __init__(self, name: str): - @property def GenericItems(self) -> List[GenericInterfaceItem]: @@ -94,15 +92,13 @@ Procedure as Method class ProcedureMethod(SubProgramm): # inherited from ModelEntity @property - def Parent(self) -> 'ModelEntity': + def Parent(self) -> ModelEntity: # inherited from NamedEntity @property def Name(self) -> str: # inherited from Subprogram - def __init__(self, name: str): - @property def GenericItems(self) -> List[GenericInterfaceItem]: @@ -122,9 +118,6 @@ Procedure as Method @property def ProtectedType(self) -> ProtectedType: - # from ProcedureMethod - def __init__(self, name: str, protectedType: ProtectedType): - .. _vhdlmodel-sub-genericprocedure: @@ -163,7 +156,7 @@ Function class Function(SubProgramm): # inherited from ModelEntity @property - def Parent(self) -> 'ModelEntity': + def Parent(self) -> ModelEntity: # inherited from NamedEntity @property @@ -186,8 +179,6 @@ Function def IsPure(self) -> bool: # from Function - def __init__(self, name: str, isPure: bool = True): - @property def ReturnType(self) -> SubType: @@ -217,7 +208,7 @@ Function as Method class Function(SubProgramm): # inherited from ModelEntity @property - def Parent(self) -> 'ModelEntity': + def Parent(self) -> ModelEntity: # inherited from NamedEntity @property @@ -240,8 +231,6 @@ Function as Method def IsPure(self) -> bool: # inherited from Function - def __init__(self, name: str, isPure: bool = True): - @property def ReturnType(self) -> SubType: @@ -249,9 +238,6 @@ Function as Method @property def ProtectedType(self) -> ProtectedType: - # from FunctionMethod - def __init__(self, name: str, protectedType: ProtectedType): - .. _vhdlmodel-sub-genericfunction: diff --git a/doc/LanguageModel/TypeDefinitions.rst b/doc/LanguageModel/TypeDefinitions.rst index 61f9afb76..ec5ece9a1 100644 --- a/doc/LanguageModel/TypeDefinitions.rst +++ b/doc/LanguageModel/TypeDefinitions.rst @@ -55,7 +55,7 @@ Enumeration class EnumeratedType(ScalarType, DiscreteType): # inherited from ModelEntity @property - def Parent(self) -> 'ModelEntity': + def Parent(self) -> ModelEntity: # inherited from NamedEntity @property @@ -84,7 +84,7 @@ Integer class IntegerType(RangedScalarType, NumericType, DiscreteType): # inherited from ModelEntity @property - def Parent(self) -> 'ModelEntity': + def Parent(self) -> ModelEntity: # inherited from NamedEntity @property @@ -116,7 +116,7 @@ Real class RealType(RangedScalarType, NumericType): # inherited from ModelEntity @property - def Parent(self) -> 'ModelEntity': + def Parent(self) -> ModelEntity: # inherited from NamedEntity @property @@ -148,7 +148,7 @@ Physical class PhysicalType(RangedScalarType, NumericType): # inherited from ModelEntity @property - def Parent(self) -> 'ModelEntity': + def Parent(self) -> ModelEntity: # inherited from NamedEntity @property @@ -192,7 +192,7 @@ Array class ArrayType(CompositeType): # inherited from ModelEntity @property - def Parent(self) -> 'ModelEntity': + def Parent(self) -> ModelEntity: # inherited from NamedEntity @property @@ -224,7 +224,7 @@ Record class RecordType(CompositeType): # inherited from ModelEntity @property - def Parent(self) -> 'ModelEntity': + def Parent(self) -> ModelEntity: # inherited from NamedEntity @property From dcc1037fc8cd4388cb68c40910b469ebef83d240 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Sun, 13 Jun 2021 23:23:32 +0200 Subject: [PATCH 38/39] Fixed THE problem. --- pyVHDLModel/VHDLModel.py | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/pyVHDLModel/VHDLModel.py b/pyVHDLModel/VHDLModel.py index 17c21ee96..f6ff8c4f4 100644 --- a/pyVHDLModel/VHDLModel.py +++ b/pyVHDLModel/VHDLModel.py @@ -63,6 +63,9 @@ class ModelEntity: """ _parent: 'ModelEntity' #: Reference to a parent entity in the model. + def __init__(self): + pass + @property def Parent(self) -> 'ModelEntity': """Returns a reference to the parent entity.""" @@ -1117,7 +1120,7 @@ class DesignUnit(ModelEntity, NamedEntity): def __init__(self, name: str): super().__init__() - NamedEntity.__init__(self, name)\ + NamedEntity.__init__(self, name) @export class MixinDesignUnitWithContext: From b241320d4888abefda54ae812292eb2658238bac Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Sun, 13 Jun 2021 23:35:27 +0200 Subject: [PATCH 39/39] Bumped version to v0.9.0. --- doc/conf.py | 4 ++-- doc/index.rst | 8 +++++++- setup.py | 2 +- 3 files changed, 10 insertions(+), 4 deletions(-) diff --git a/doc/conf.py b/doc/conf.py index b6cfd5032..3c87dd689 100644 --- a/doc/conf.py +++ b/doc/conf.py @@ -36,8 +36,8 @@ def _LatestTagName(): return check_output(["git", "describe", "--abbrev=0", "--tags"], universal_newlines=True).strip() # The full version, including alpha/beta/rc tags -version = "0.8" # The short X.Y version. -release = "0.8.2" # The full version, including alpha/beta/rc tags. +version = "0.9" # The short X.Y version. +release = "0.9.0" # The full version, including alpha/beta/rc tags. try: if _IsUnderGitControl: latestTagName = _LatestTagName()[1:] # remove prefix "v" diff --git a/doc/index.rst b/doc/index.rst index d3a8eb1c3..cd9627ce5 100644 --- a/doc/index.rst +++ b/doc/index.rst @@ -67,11 +67,17 @@ News .. rubric:: Model and documentation enhancements * Made generic, port, and parameter items a subclass of the matching object classes. -* Finalized literals, expressions and types. +* Added missing object representations for language features. + * Finalized literals, expressions and types. + * Added properties to empty placeholder classes * Corrected class hierarchy according to LRM. * Enhanced class documentation and cross references. * New documentation chapter for literals and expressions. * Added inheritance diagrams as overviews to documentation sections. +* Added condensed code snippets outlining the main interface of a model's object. +* New Single-File GitHub Action workflow (pipeline) including tests, documentation, packaging and publishing. +* Added Dependabot configuration file. +* Removed 2 dependencies to patched Sphinx extensions (now fixed in Sphinx). * ... .. only:: html diff --git a/setup.py b/setup.py index 0ad30917a..a98a49bc2 100644 --- a/setup.py +++ b/setup.py @@ -53,7 +53,7 @@ # Assemble all package information setuptools_setup( name=projectName, - version="0.8.2", + version="0.9.0", author="Patrick Lehmann", author_email="Paebbels@gmail.com",