From 17e00ad7cf24801df1b11bbfafcf0f63a5beaea9 Mon Sep 17 00:00:00 2001 From: Oscar Gustafsson Date: Mon, 4 Nov 2024 09:33:59 +0100 Subject: [PATCH] Minor documentation fixes --- doc/DataStructure/index.rst | 14 +++++++------- doc/GettingStarted.rst | 6 +++--- doc/index.rst | 4 ++-- 3 files changed, 12 insertions(+), 12 deletions(-) diff --git a/doc/DataStructure/index.rst b/doc/DataStructure/index.rst index fc5d67b3f..4db2dc9f2 100644 --- a/doc/DataStructure/index.rst +++ b/doc/DataStructure/index.rst @@ -9,7 +9,7 @@ cross-references or dedicated data structure (tree, graph, …) for connecting m Graphs ****** -pyVHDLModel uses the graph implementation from :pyTool:mod:`pyTooling.Graph` as it provides an object oriented programming +pyVHDLModel uses the graph implementation from :py:mod:`pyTooling.Graph` as it provides an object oriented programming interface to vertices and edges. Dependency Graph @@ -29,7 +29,7 @@ The dependency graph describes dependencies between: The relation can be: -* Defined in source file +* defined in source file * references * implements * instantiates @@ -55,11 +55,11 @@ Compile Order Graph The compile order can be derived from dependency graph by: 1. copying all document vertices -2. iterating all edges in the dependency graph. - 1. resolve the source and the destination to the referenced design units - 2. resolved further to the documents these design units are declared in - 3. resolve further which vertices correspond in the compile order graph - 4. if edges does not yet exist, add an edge between two documents in the compile order graph +2. iterating all edges in the dependency graph + #. resolve the source and the destination to the referenced design units + #. resolved further to the documents these design units are declared in + #. resolve further which vertices correspond in the compile order graph + #. if edges does not yet exist, add an edge between two documents in the compile order graph .. toctree:: diff --git a/doc/GettingStarted.rst b/doc/GettingStarted.rst index ab14c1ade..dd20a4282 100644 --- a/doc/GettingStarted.rst +++ b/doc/GettingStarted.rst @@ -14,7 +14,7 @@ pyVHDLParser ************ The pyVHDLParser is a token-stream based parser creating a code document object model (CodeDOM) derived from -pyVHDLModel. Actually, pyVHDlModel was originally part of that parser, until it got refactored into this standalone +pyVHDLModel. Actually, pyVHDLModel was originally part of that parser, until it got refactored into this standalone package so multiple frontends (parsers) and backends (analysis tools) can use this VHDL language model as a common API. .. warning:: Currently, pyVHDLParser is not aligned with latest updates in pyVHDLModel. @@ -227,8 +227,8 @@ On Mac Using libghdl with Python ========================= -An environment variable :envvar:`GHDL_PREFIX=C:\\Tools\\GHDL\\3.0.0-dev\\lib\\ghdl` is needed for libghdl. The path is -constructed from installation path plus ``lib\\ghdl``. +An environment variable :envvar:`GHDL_PREFIX=C:\\Tools\\GHDL\\3.0.0-dev\\lib\\ghdl` is needed for ``libghdl``. The path is +constructed from installation path plus ``lib\ghdl``. .. admonition:: GettingStarted.py diff --git a/doc/index.rst b/doc/index.rst index 69f206552..ee8bbe5cf 100644 --- a/doc/index.rst +++ b/doc/index.rst @@ -54,8 +54,8 @@ frontends. Use Cases ********* -* High-level API for `GHDL's `__ `libghdl` offered via `pyGHDL `__. -* Code Document-Object-Model (Code-DOM) in `pyVHDLParser `__. +* High-level API for `GHDL's `__ `libghdl` offered via `pyGHDL `__. +* Code Document-Object-Model (Code-DOM) in `pyVHDLParser `__. .. _news: