diff --git a/examples/vhdl/array/src/test/tb_sobel_x.vhd b/examples/vhdl/array/src/test/tb_sobel_x.vhd index 087b0abb93..0d80d670b2 100644 --- a/examples/vhdl/array/src/test/tb_sobel_x.vhd +++ b/examples/vhdl/array/src/test/tb_sobel_x.vhd @@ -12,41 +12,53 @@ library vunit_lib; context vunit_lib.vunit_context; library osvvm; -use osvvm.RandomPkg.all; +use osvvm.RandomPkg.RandomPType; entity tb_sobel_x is generic ( runner_cfg : string; - tb_path : string); + tb_path : string + ); end entity; architecture tb of tb_sobel_x is - signal clk : std_logic := '0'; - signal input_tvalid : std_logic := '0'; - signal input_tlast : std_logic := '0'; - signal input_tdata : unsigned(14-1 downto 0) := (others => '0'); + + signal clk : std_logic := '0'; + signal input_tvalid : std_logic := '0'; + signal input_tlast : std_logic := '0'; + signal input_tdata : unsigned(13 downto 0) := (others => '0'); signal output_tvalid : std_logic; - signal output_tlast : std_logic; - signal output_tdata : signed(input_tdata'length downto 0); + signal output_tlast : std_logic; + signal output_tdata : signed(input_tdata'length downto 0); - shared variable image, reference_image : integer_array_t; + shared variable image, ref_image : integer_array_t; signal start, data_check_done, stimuli_done : boolean := false; + begin main : process - procedure sobel_x(variable image : inout integer_array_t; - variable result : inout integer_array_t) is - begin - result := new_2d(width => width(image), - height => height(image), - bit_width => bit_width(image)+1, - is_signed => true); + procedure sobel_x( + variable image : inout integer_array_t; + variable result : inout integer_array_t + ) is begin + result := new_2d( + width => width(image), + height => height(image), + bit_width => bit_width(image)+1, + is_signed => true + ); for y in 0 to height(image)-1 loop for x in 0 to width(image)-1 loop - set(result, x => x, y => y, - value => (get(image, minimum(x+1, width(image)-1),y) - - get(image, maximum(x-1, 0), y))); + set( + result, + x => x, + y => y, + value => ( + get(image, minimum(x+1, width(image)-1),y) + - get(image, maximum(x-1, 0), y) + ) + ); end loop; end loop; @@ -54,13 +66,6 @@ begin variable rnd : RandomPType; - procedure randomize(variable arr : inout integer_array_t) is - begin - for idx in 0 to arr.length-1 loop - set(arr, idx, value => rnd.RandInt(arr.lower_limit, arr.upper_limit)); - end loop; - end procedure; - procedure run_test is begin wait until rising_edge(clk); @@ -68,18 +73,31 @@ begin wait until rising_edge(clk); start <= false; - wait until (stimuli_done and - data_check_done and - rising_edge(clk)); + wait until ( + stimuli_done and + data_check_done and + rising_edge(clk) + ); end procedure; procedure test_random_image(width, height : natural) is begin - image := new_2d(width => width, height => height, - bit_width => input_tdata'length, - is_signed => false); - randomize(image); - sobel_x(image, result => reference_image); + image := new_2d( + width => width, + height => height, + bit_width => input_tdata'length, + is_signed => false + ); + + for idx in 0 to image.length-1 loop + set( + image, + idx, + value => rnd.RandInt(image.lower_limit, image.upper_limit) + ); + end loop; + + sobel_x(image, result => ref_image); run_test; end procedure; @@ -94,7 +112,7 @@ begin test_random_image(1, 1); elsif run("test_input_file_against_output_file") then image := load_csv(tb_path & "input.csv"); - reference_image := load_csv(tb_path & "output.csv"); + ref_image := load_csv(tb_path & "output.csv"); run_test; end if; end loop; @@ -107,9 +125,11 @@ begin wait until start and rising_edge(clk); stimuli_done <= false; - report ("Sending image of size " & - to_string(width(image)) & "x" & - to_string(height(image))); + report ( + "Sending image of size " & + to_string(width(image)) & "x" & + to_string(height(image)) + ); for y in 0 to height(image)-1 loop for x in 0 to width(image)-1 loop @@ -120,7 +140,7 @@ begin else input_tlast <= '0'; end if; - input_tdata <= to_unsigned(get(image,x,y), input_tdata'length); + input_tdata <= to_unsigned(get(image, x, y), input_tdata'length); end loop; end loop; @@ -134,17 +154,19 @@ begin begin wait until start and rising_edge(clk); data_check_done <= false; - for y in 0 to height(reference_image)-1 loop - for x in 0 to width(reference_image)-1 loop + for y in 0 to height(ref_image)-1 loop + for x in 0 to width(ref_image)-1 loop wait until output_tvalid = '1' and rising_edge(clk); - check_equal(output_tlast, x = width(reference_image)-1); - check_equal(output_tdata, get(reference_image, x, y), + check_equal(output_tlast, x = width(ref_image)-1); + check_equal(output_tdata, get(ref_image, x, y), "x=" & to_string(x) & " y=" & to_string(y)); end loop; end loop; - report ("Done checking image of size " & - to_string(width(reference_image)) & "x" & - to_string(height(reference_image))); + report ( + "Done checking image of size " & + to_string(width(ref_image)) & "x" & + to_string(height(ref_image)) + ); data_check_done <= true; end process; @@ -152,7 +174,8 @@ begin dut : entity work.sobel_x generic map ( - data_width => input_tdata'length) + data_width => input_tdata'length + ) port map ( clk => clk, input_tvalid => input_tvalid, @@ -160,6 +183,7 @@ begin input_tdata => input_tdata, output_tvalid => output_tvalid, output_tlast => output_tlast, - output_tdata => output_tdata); + output_tdata => output_tdata + ); end architecture; diff --git a/examples/vhdl/array_axis_vcs/src/test/tb_axis_loop.vhd b/examples/vhdl/array_axis_vcs/src/test/tb_axis_loop.vhd index 4670026297..d524e353c6 100644 --- a/examples/vhdl/array_axis_vcs/src/test/tb_axis_loop.vhd +++ b/examples/vhdl/array_axis_vcs/src/test/tb_axis_loop.vhd @@ -31,13 +31,13 @@ architecture tb of tb_axis_loop is -- Simulation constants - constant clk_period : time := 20 ns; + constant clk_period : time := 20 ns; constant data_width : natural := 32; -- AXI4Stream Verification Components constant master_axi_stream : axi_stream_master_t := new_axi_stream_master(data_length => data_width); - constant slave_axi_stream : axi_stream_slave_t := new_axi_stream_slave(data_length => data_width); + constant slave_axi_stream : axi_stream_slave_t := new_axi_stream_slave(data_length => data_width); -- Signals to/from the UUT from/to the verification components @@ -136,23 +136,27 @@ begin vunit_axism: entity vunit_lib.axi_stream_master generic map ( - master => master_axi_stream) + master => master_axi_stream + ) port map ( aclk => clk, tvalid => m_valid, tready => m_ready, tdata => m_data, - tlast => m_last); + tlast => m_last + ); vunit_axiss: entity vunit_lib.axi_stream_slave generic map ( - slave => slave_axi_stream) + slave => slave_axi_stream + ) port map ( aclk => clk, tvalid => s_valid, tready => s_ready, tdata => s_data, - tlast => s_last); + tlast => s_last + ); --