diff --git a/docs/conf.py b/docs/conf.py index a771d03e1..4787dada8 100644 --- a/docs/conf.py +++ b/docs/conf.py @@ -2,7 +2,7 @@ import os import sys -from os.path import join +from pathlib import Path # blog_title = u"VUnit Blog" # blog_baseurl = "http://vunit.github.io" @@ -70,9 +70,9 @@ html_static_path = ["_static"] -html_logo = join(html_static_path[0], "VUnit_logo_420x420.png") +html_logo = str(Path(html_static_path[0]) / "VUnit_logo_420x420.png") -html_favicon = join(html_static_path[0], "vunit.ico") +html_favicon = str(Path(html_static_path[0]) / "vunit.ico") # Output file base name for HTML help builder. htmlhelp_basename = "vunitdoc" diff --git a/examples/vhdl/vivado/vivado_util.py b/examples/vhdl/vivado/vivado_util.py index 6ef8c5219..ac11b6e27 100644 --- a/examples/vhdl/vivado/vivado_util.py +++ b/examples/vhdl/vivado/vivado_util.py @@ -5,7 +5,7 @@ # Copyright (c) 2014-2020, Lars Asplund lars.anders.asplund@gmail.com import sys -from os.path import join, exists, abspath, dirname +from pathlib import Path from vunit.sim_if.factory import SIMULATOR_FACTORY from vunit.vivado import ( run_vivado, @@ -19,14 +19,16 @@ def add_vivado_ip(vunit_obj, output_path, project_file): Add vivado (and compile if necessary) vivado ip to vunit project. """ - if not exists(project_file): + if not Path(project_file).exists(): print("Could not find vivado project %s" % project_file) sys.exit(1) - standard_library_path = join(output_path, "standard") + opath = Path(output_path) + + standard_library_path = str(opath / "standard") compile_standard_libraries(vunit_obj, standard_library_path) - project_ip_path = join(output_path, "project_ip") + project_ip_path = str(opath / "project_ip") add_project_ip(vunit_obj, project_file, project_ip_path) @@ -34,12 +36,15 @@ def compile_standard_libraries(vunit_obj, output_path): """ Compile Xilinx standard libraries using Vivado TCL command """ - done_token = join(output_path, "all_done.txt") + done_token = str(Path(output_path) / "all_done.txt") simulator_class = SIMULATOR_FACTORY.select_simulator() - if not exists(done_token): - print("Compiling standard libraries into %s ..." % abspath(output_path)) + if not Path(done_token).exists(): + print( + "Compiling standard libraries into %s ..." + % str(Path(output_path).resolve()) + ) simname = simulator_class.name # Vivado calls rivierapro for riviera @@ -47,7 +52,7 @@ def compile_standard_libraries(vunit_obj, output_path): simname = "riviera" run_vivado( - join(dirname(__file__), "tcl", "compile_standard_libs.tcl"), + str(Path(__file__).parent / "tcl" / "compile_standard_libs.tcl"), tcl_args=[ simname, simulator_class.find_prefix().replace("\\", "/"), @@ -57,12 +62,13 @@ def compile_standard_libraries(vunit_obj, output_path): else: print( - "Standard libraries already exists in %s, skipping" % abspath(output_path) + "Standard libraries already exists in %s, skipping" + % str(Path(output_path).resolve()) ) for library_name in ["unisim", "unimacro", "unifast", "secureip", "xpm"]: - path = join(output_path, library_name) - if exists(path): + path = str(Path(output_path) / library_name) + if Path(path).exists(): vunit_obj.add_external_library(library_name, path) with open(done_token, "w") as fptr: @@ -79,16 +85,16 @@ def add_project_ip(vunit_obj, project_file, output_path, vivado_path=None, clean returns the list of SourceFile objects added """ - compile_order_file = join(output_path, "compile_order.txt") + compile_order_file = str(Path(output_path) / "compile_order.txt") - if clean or not exists(compile_order_file): + if clean or not Path(compile_order_file).exists(): create_compile_order_file( project_file, compile_order_file, vivado_path=vivado_path ) else: print( "Vivado project Compile order already exists, re-using: %s" - % abspath(compile_order_file) + % str(Path(compile_order_file).resolve()) ) return add_from_compile_order_file(vunit_obj, compile_order_file) diff --git a/tests/acceptance/artificial/verilog/run.py b/tests/acceptance/artificial/verilog/run.py index 7d36e8202..2852d418e 100644 --- a/tests/acceptance/artificial/verilog/run.py +++ b/tests/acceptance/artificial/verilog/run.py @@ -4,14 +4,14 @@ # # Copyright (c) 2014-2020, Lars Asplund lars.anders.asplund@gmail.com -from os.path import join, dirname +from pathlib import Path from vunit.verilog import VUnit -root = dirname(__file__) +ROOT = Path(__file__).parent VU = VUnit.from_argv() LIB = VU.add_library("lib") -LIB.add_source_files(join(root, "*.sv"), defines={"DEFINE_FROM_RUN_PY": ""}) +LIB.add_source_files(ROOT / "*.sv", defines={"DEFINE_FROM_RUN_PY": ""}) def configure_tb_with_parameter_config(): @@ -35,7 +35,7 @@ def configure_tb_with_parameter_config(): ) def post_check(output_path): - with open(join(output_path, "post_check.txt"), "r") as fptr: + with (Path(output_path) / "post_check.txt").open("r") as fptr: return fptr.read() == "Test 4 was here" tests[4].add_config( @@ -49,7 +49,7 @@ def post_check(output_path): def configure_tb_same_sim_all_pass(ui): def post_check(output_path): - with open(join(output_path, "post_check.txt"), "r") as fptr: + with (Path(output_path) / "post_check.txt").open("r") as fptr: return fptr.read() == "Test 3 was here" module = ui.library("lib").module("tb_same_sim_all_pass") @@ -59,6 +59,6 @@ def post_check(output_path): configure_tb_with_parameter_config() configure_tb_same_sim_all_pass(VU) LIB.module("tb_other_file_tests").scan_tests_from_file( - join(root, "other_file_tests.sv") + str(ROOT / "other_file_tests.sv") ) VU.main() diff --git a/tests/acceptance/artificial/vhdl/run.py b/tests/acceptance/artificial/vhdl/run.py index 4c2ecb47a..274d10efb 100644 --- a/tests/acceptance/artificial/vhdl/run.py +++ b/tests/acceptance/artificial/vhdl/run.py @@ -4,14 +4,14 @@ # # Copyright (c) 2014-2020, Lars Asplund lars.anders.asplund@gmail.com -from os.path import join, dirname +from pathlib import Path from vunit import VUnit -root = dirname(__file__) +ROOT = Path(__file__).parent VU = VUnit.from_argv() LIB = VU.add_library("lib") -LIB.add_source_files(join(root, "*.vhd")) +LIB.add_source_files(ROOT / "*.vhd") def configure_tb_with_generic_config(): @@ -33,7 +33,7 @@ def configure_tb_with_generic_config(): ) def post_check(output_path): - with open(join(output_path, "post_check.txt"), "r") as fptr: + with (Path(output_path) / "post_check.txt").open("r") as fptr: return "Test 4 was here" in fptr.read() tests[4].add_config( @@ -45,7 +45,7 @@ def post_check(output_path): def configure_tb_same_sim_all_pass(ui): def post_check(output_path): - with open(join(output_path, "post_check.txt"), "r") as fptr: + with (Path(output_path) / "post_check.txt").open("r") as fptr: return "Test 3 was here" in fptr.read() ent = ui.library("lib").entity("tb_same_sim_all_pass") @@ -93,6 +93,6 @@ def configure_tb_assert_stop_level(ui): LIB.entity("tb_no_generic_override").set_generic("g_val", False) LIB.entity("tb_ieee_warning").test("pass").set_sim_option("disable_ieee_warnings", True) LIB.entity("tb_other_file_tests").scan_tests_from_file( - join(root, "other_file_tests.vhd") + str(ROOT / "other_file_tests.vhd") ) VU.main() diff --git a/tests/acceptance/test_artificial.py b/tests/acceptance/test_artificial.py index bc30cc0cf..b6917f1f8 100644 --- a/tests/acceptance/test_artificial.py +++ b/tests/acceptance/test_artificial.py @@ -9,13 +9,15 @@ """ import unittest -from os.path import join, dirname +from pathlib import Path from os import environ from subprocess import call import sys from tests.common import check_report from vunit.sim_if.common import has_simulator, simulator_is +ROOT = Path(__file__).parent + @unittest.skipUnless(has_simulator(), "Requires simulator") class TestVunitArtificial(unittest.TestCase): @@ -26,18 +28,14 @@ class TestVunitArtificial(unittest.TestCase): def setUp(self): if simulator_is("activehdl"): - self.output_path = join(dirname(__file__), "artificial_out") + self.output_path = str(ROOT / "artificial_out") else: # Spaces in path intentional to verify that it is supported - self.output_path = join(dirname(__file__), "artificial _out") + self.output_path = str(ROOT / "artificial _out") - self.report_file = join(self.output_path, "xunit.xml") - self.artificial_run_vhdl = join( - dirname(__file__), "artificial", "vhdl", "run.py" - ) - self.artificial_run_verilog = join( - dirname(__file__), "artificial", "verilog", "run.py" - ) + self.report_file = str(Path(self.output_path) / "xunit.xml") + self.artificial_run_vhdl = str(ROOT / "artificial" / "vhdl" / "run.py") + self.artificial_run_verilog = str(ROOT / "artificial" / "verilog" / "run.py") @unittest.skipUnless( simulator_is("modelsim", "rivierapro"), diff --git a/tests/acceptance/test_dependencies.py b/tests/acceptance/test_dependencies.py index 7099a5d9c..4a89ab8b6 100644 --- a/tests/acceptance/test_dependencies.py +++ b/tests/acceptance/test_dependencies.py @@ -11,9 +11,11 @@ import unittest -from os.path import join, dirname +from pathlib import Path from vunit import VUnit +ROOT = Path(__file__).parent + class TestDependencies(unittest.TestCase): """ @@ -21,8 +23,8 @@ class TestDependencies(unittest.TestCase): """ def setUp(self): - self.data_path = join(dirname(__file__), "dependencies") - self.output_path = join(dirname(__file__), "dependencies_vunit_out") + self.data_path = str(ROOT / "dependencies") + self.output_path = str(ROOT / "dependencies_vunit_out") def test_package_body_dependencies(self): """ @@ -36,9 +38,11 @@ def run(value): Utility function to first run with pkg_body1 then pkg_body2 """ - tb_pkg_file_name = join(self.data_path, "tb_pkg.vhd") - pkg_file_name = join(self.data_path, "pkg.vhd") - pkg_body_file_name = join(self.data_path, "pkg_body%i.vhd" % value) + dpath = Path(self.data_path) + + tb_pkg_file_name = str(dpath / "tb_pkg.vhd") + pkg_file_name = str(dpath / "pkg.vhd") + pkg_body_file_name = str(dpath / ("pkg_body%i.vhd" % value)) argv = ["--output-path=%s" % self.output_path, "-v"] if value == 1: diff --git a/tests/acceptance/test_external_run_scripts.py b/tests/acceptance/test_external_run_scripts.py index 90e979bf0..3fdba5a69 100644 --- a/tests/acceptance/test_external_run_scripts.py +++ b/tests/acceptance/test_external_run_scripts.py @@ -9,15 +9,17 @@ """ import unittest +from pathlib import Path from os import environ -from os.path import join, dirname from subprocess import call import sys from tests.common import check_report -from vunit import ROOT +from vunit import ROOT as RSTR from vunit.builtins import VHDL_PATH from vunit.sim_if.common import has_simulator, simulator_is, simulator_check +ROOT = Path(RSTR) + def simulator_supports_verilog(): """ @@ -34,15 +36,15 @@ class TestExternalRunScripts(unittest.TestCase): """ def test_vhdl_uart_example_project(self): - self.check(join(ROOT, "examples", "vhdl", "uart", "run.py")) + self.check(ROOT / "examples" / "vhdl" / "uart" / "run.py") @unittest.skipUnless(simulator_supports_verilog(), "Verilog") def test_verilog_uart_example_project(self): - self.check(join(ROOT, "examples", "verilog", "uart", "run.py")) + self.check(ROOT / "examples" / "verilog" / "uart" / "run.py") @unittest.skipUnless(simulator_supports_verilog(), "Verilog") def test_verilog_ams_example(self): - self.check(join(ROOT, "examples", "verilog", "verilog_ams", "run.py")) + self.check(ROOT / "examples" / "verilog" / "verilog_ams" / "run.py") check_report( self.report_file, [ @@ -52,10 +54,10 @@ def test_verilog_ams_example(self): ) def test_vhdl_logging_example_project(self): - self.check(join(ROOT, "examples", "vhdl", "logging", "run.py")) + self.check(ROOT / "examples" / "vhdl" / "logging" / "run.py") def test_vhdl_run_example_project(self): - self.check(join(ROOT, "examples", "vhdl", "run", "run.py"), exit_code=1) + self.check(ROOT / "examples" / "vhdl" / "run" / "run.py", exit_code=1) check_report( self.report_file, [ @@ -98,7 +100,7 @@ def test_vhdl_run_example_project(self): def test_vhdl_third_party_integration_example_project(self): self.check( - join(ROOT, "examples", "vhdl", "third_party_integration", "run.py"), + ROOT / "examples" / "vhdl" / "third_party_integration" / "run.py", exit_code=1, ) check_report( @@ -117,10 +119,10 @@ def test_vhdl_third_party_integration_example_project(self): ) def test_vhdl_check_example_project(self): - self.check(join(ROOT, "examples", "vhdl", "check", "run.py")) + self.check(ROOT / "examples" / "vhdl" / "check" / "run.py") def test_vhdl_generate_tests_example_project(self): - self.check(join(ROOT, "examples", "vhdl", "generate_tests", "run.py")) + self.check(ROOT / "examples" / "vhdl" / "generate_tests" / "run.py") check_report( self.report_file, [ @@ -137,7 +139,7 @@ def test_vhdl_generate_tests_example_project(self): ) def test_vhdl_composite_generics_example_project(self): - self.check(join(ROOT, "examples", "vhdl", "composite_generics", "run.py")) + self.check(ROOT / "examples" / "vhdl" / "composite_generics" / "run.py") check_report( self.report_file, [ @@ -150,19 +152,19 @@ def test_vhdl_composite_generics_example_project(self): simulator_is("ghdl"), "Support complex JSON strings as generic" ) def test_vhdl_json4vhdl_example_project(self): - self.check(join(ROOT, "examples", "vhdl", "json4vhdl", "run.py")) + self.check(ROOT / "examples" / "vhdl" / "json4vhdl" / "run.py") def test_vhdl_array_example_project(self): - self.check(join(ROOT, "examples", "vhdl", "array", "run.py")) + self.check(ROOT / "examples" / "vhdl" / "array" / "run.py") def test_vhdl_array_axis_vcs_example_project(self): - self.check(join(ROOT, "examples", "vhdl", "array_axis_vcs", "run.py")) + self.check(ROOT / "examples" / "vhdl" / "array_axis_vcs" / "run.py") def test_vhdl_axi_dma_example_project(self): - self.check(join(ROOT, "examples", "vhdl", "axi_dma", "run.py")) + self.check(ROOT / "examples" / "vhdl" / "axi_dma" / "run.py") def test_vhdl_user_guide_example_project(self): - self.check(join(ROOT, "examples", "vhdl", "user_guide", "run.py"), exit_code=1) + self.check(ROOT / "examples" / "vhdl" / "user_guide" / "run.py", exit_code=1) check_report( self.report_file, [ @@ -174,9 +176,7 @@ def test_vhdl_user_guide_example_project(self): @unittest.skipUnless(simulator_supports_verilog(), "Verilog") def test_verilog_user_guide_example_project(self): - self.check( - join(ROOT, "examples", "verilog", "user_guide", "run.py"), exit_code=1 - ) + self.check(ROOT / "examples" / "verilog" / "user_guide" / "run.py", exit_code=1) check_report( self.report_file, [ @@ -194,85 +194,85 @@ def test_verilog_user_guide_example_project(self): ) def test_vhdl_com_example_project(self): - self.check(join(ROOT, "examples", "vhdl", "com", "run.py")) + self.check(ROOT / "examples" / "vhdl" / "com" / "run.py") def test_array_vhdl_2008(self): - self.check(join(VHDL_PATH, "array", "run.py")) + self.check(VHDL_PATH / "array" / "run.py") def test_data_types_vhdl_2008(self): - self.check(join(VHDL_PATH, "data_types", "run.py")) + self.check(VHDL_PATH / "data_types" / "run.py") def test_data_types_vhdl_2002(self): - self.check(join(VHDL_PATH, "data_types", "run.py"), vhdl_standard="2002") + self.check(VHDL_PATH / "data_types" / "run.py", vhdl_standard="2002") def test_data_types_vhdl_93(self): - self.check(join(VHDL_PATH, "data_types", "run.py"), vhdl_standard="93") + self.check(VHDL_PATH / "data_types" / "run.py", vhdl_standard="93") def test_random_vhdl_2008(self): - self.check(join(VHDL_PATH, "random", "run.py")) + self.check(VHDL_PATH / "random" / "run.py") def test_check_vhdl_2008(self): - self.check(join(VHDL_PATH, "check", "run.py")) + self.check(VHDL_PATH / "check" / "run.py") def test_check_vhdl_2002(self): - self.check(join(VHDL_PATH, "check", "run.py"), vhdl_standard="2002") + self.check(VHDL_PATH / "check" / "run.py", vhdl_standard="2002") def test_check_vhdl_93(self): - self.check(join(VHDL_PATH, "check", "run.py"), vhdl_standard="93") + self.check(VHDL_PATH / "check" / "run.py", vhdl_standard="93") def test_logging_vhdl_2008(self): - self.check(join(VHDL_PATH, "logging", "run.py")) + self.check(VHDL_PATH / "logging" / "run.py") def test_logging_vhdl_2002(self): - self.check(join(VHDL_PATH, "logging", "run.py"), vhdl_standard="2002") + self.check(VHDL_PATH / "logging" / "run.py", vhdl_standard="2002") def test_logging_vhdl_93(self): - self.check(join(VHDL_PATH, "logging", "run.py"), vhdl_standard="93") + self.check(VHDL_PATH / "logging" / "run.py", vhdl_standard="93") def test_run_vhdl_2008(self): - self.check(join(VHDL_PATH, "run", "run.py")) + self.check(VHDL_PATH / "run" / "run.py") def test_run_vhdl_2002(self): - self.check(join(VHDL_PATH, "run", "run.py"), vhdl_standard="2002") + self.check(VHDL_PATH / "run" / "run.py", vhdl_standard="2002") def test_run_vhdl_93(self): - self.check(join(VHDL_PATH, "run", "run.py"), vhdl_standard="93") + self.check(VHDL_PATH / "run" / "run.py", vhdl_standard="93") def test_string_ops_vhdl_2008(self): - self.check(join(VHDL_PATH, "string_ops", "run.py")) + self.check(VHDL_PATH / "string_ops" / "run.py") def test_string_ops_vhdl_2002(self): - self.check(join(VHDL_PATH, "string_ops", "run.py"), vhdl_standard="2002") + self.check(VHDL_PATH / "string_ops" / "run.py", vhdl_standard="2002") def test_string_ops_vhdl_93(self): - self.check(join(VHDL_PATH, "string_ops", "run.py"), vhdl_standard="93") + self.check(VHDL_PATH / "string_ops" / "run.py", vhdl_standard="93") def test_dictionary_vhdl_2008(self): - self.check(join(VHDL_PATH, "dictionary", "run.py")) + self.check(VHDL_PATH / "dictionary" / "run.py") def test_dictionary_vhdl_2002(self): - self.check(join(VHDL_PATH, "dictionary", "run.py"), vhdl_standard="2002") + self.check(VHDL_PATH / "dictionary" / "run.py", vhdl_standard="2002") def test_dictionary_vhdl_93(self): - self.check(join(VHDL_PATH, "dictionary", "run.py"), vhdl_standard="93") + self.check(VHDL_PATH / "dictionary" / "run.py", vhdl_standard="93") def test_path_vhdl_2008(self): - self.check(join(VHDL_PATH, "path", "run.py")) + self.check(VHDL_PATH / "path" / "run.py") def test_path_vhdl_2002(self): - self.check(join(VHDL_PATH, "path", "run.py"), vhdl_standard="2002") + self.check(VHDL_PATH / "path" / "run.py", vhdl_standard="2002") def test_path_vhdl_93(self): - self.check(join(VHDL_PATH, "path", "run.py"), vhdl_standard="93") + self.check(VHDL_PATH / "path" / "run.py", vhdl_standard="93") def test_com_vhdl_2008(self): - self.check(join(VHDL_PATH, "com", "run.py")) + self.check(VHDL_PATH / "com" / "run.py") def setUp(self): - self.output_path = join(dirname(__file__), "external_run_out") - self.report_file = join(self.output_path, "xunit.xml") + self.output_path = str(Path(__file__).parent / "external_run_out") + self.report_file = str(Path(self.output_path) / "xunit.xml") - def check(self, run_file, args=None, vhdl_standard="2008", exit_code=0): + def check(self, run_file: Path, args=None, vhdl_standard="2008", exit_code=0): """ Run external run file and verify exit code """ diff --git a/tests/lint/test_license.py b/tests/lint/test_license.py index 33afcc374..8e90c687b 100644 --- a/tests/lint/test_license.py +++ b/tests/lint/test_license.py @@ -10,14 +10,17 @@ import unittest from warnings import simplefilter, catch_warnings -from os.path import join, splitext, abspath, commonprefix +from pathlib import Path +from os.path import commonprefix from os import walk import re -from vunit import ROOT +from vunit import ROOT as RSTR from vunit.builtins import VHDL_PATH from vunit import ostools from vunit.about import license_text +ROOT = Path(RSTR) + RE_LICENSE_NOTICE = re.compile( r"(?P#|--|//) This Source Code Form is subject to the terms of the Mozilla Public" + "\n" @@ -48,13 +51,13 @@ def test_that_a_valid_license_exists_in_source_files_and_that_global_licensing_i for file_name in find_licensed_files(): code = ostools.read_file(file_name) self._check_license(code, file_name) - if splitext(file_name)[1] in (".vhd", ".vhdl", ".v", ".sv"): + if Path(file_name).suffix in (".vhd", ".vhdl", ".v", ".sv"): self._check_no_trailing_whitespace(code, file_name) def test_that_license_file_matches_vunit_license_text(self): with catch_warnings(): simplefilter("ignore", category=DeprecationWarning) - with open(join(ROOT, "LICENSE.txt"), "rU") as lic: + with (ROOT / "LICENSE.txt").open("rU") as lic: self.assertEqual(lic.read(), license_text()) def _check_license(self, code, file_name): @@ -128,34 +131,37 @@ def find_licensed_files(): Return all licensed files """ licensed_files = [] - osvvm_directory = abspath(join(VHDL_PATH, "osvvm")) - json4vhdl_directory = abspath(join(VHDL_PATH, "JSON-for-VHDL")) - for root, _, files in walk(ROOT): + for root, _, files in walk(RSTR): for file_name in files: if "preprocessed" in root: continue if "codecs" in root: continue - if root == join(ROOT, "docs"): + if root == str(ROOT / "docs"): continue - if join(ROOT, "venv") in root: + if str(ROOT / "venv") in root: continue - if join(ROOT, ".tox") in root: + if str(ROOT / ".tox") in root: continue - if is_prefix_of(osvvm_directory, abspath(join(root, file_name))): + if is_prefix_of( + (VHDL_PATH / "osvvm").resolve(), (Path(root) / file_name).resolve(), + ): continue - if is_prefix_of(json4vhdl_directory, abspath(join(root, file_name))): + if is_prefix_of( + (VHDL_PATH / "JSON-for-VHDL").resolve(), + (Path(root) / file_name).resolve(), + ): continue - if splitext(file_name)[1] in (".vhd", ".vhdl", ".py", ".v", ".sv"): - licensed_files.append(join(root, file_name)) + if Path(file_name).suffix in (".vhd", ".vhdl", ".py", ".v", ".sv"): + licensed_files.append(str(Path(root) / file_name)) return licensed_files -def is_prefix_of(prefix, of_path): +def is_prefix_of(prefix: Path, of_path: Path): """ Return True if 'prefix' is a prefix of 'of_path' """ - return commonprefix([prefix, of_path]) == prefix + return commonprefix([str(prefix), str(of_path)]) == str(prefix) def main(): diff --git a/tests/lint/test_pycodestyle.py b/tests/lint/test_pycodestyle.py index b730c41ed..9e48feeaf 100644 --- a/tests/lint/test_pycodestyle.py +++ b/tests/lint/test_pycodestyle.py @@ -12,8 +12,10 @@ from subprocess import check_call import sys from glob import glob -from os.path import join -from vunit import ROOT +from pathlib import Path +from vunit import ROOT as RSTR + +ROOT = Path(RSTR) class TestPycodestyle(unittest.TestCase): @@ -43,7 +45,7 @@ def get_files_and_folders(): """ Return all files and folders which shall be arguments to pycodestyle and pylint """ - ret = [join(ROOT, "vunit")] - ret += list(glob(join(ROOT, "*.py"))) - ret += list(glob(join(ROOT, "tools", "*.py"))) + ret = [str(ROOT / "vunit")] + ret += list(glob(str(ROOT / "*.py"))) + ret += list(glob(str(ROOT / "tools" / "*.py"))) return ret diff --git a/tests/lint/test_pylint.py b/tests/lint/test_pylint.py index b9ccdc02d..d71ce3054 100644 --- a/tests/lint/test_pylint.py +++ b/tests/lint/test_pylint.py @@ -11,7 +11,7 @@ import unittest from subprocess import check_call -from os.path import join, dirname +from pathlib import Path import sys from tests.lint.test_pycodestyle import get_files_and_folders @@ -28,7 +28,7 @@ def test_pylint(): sys.executable, "-m", "pylint", - "--rcfile=" + join(dirname(__file__), "pylintrc"), + "--rcfile=" + str(Path(__file__).parent / "pylintrc"), ] + get_files_and_folders() ) diff --git a/tests/lint/test_readme.py b/tests/lint/test_readme.py index a7b5e2f52..16e962d34 100644 --- a/tests/lint/test_readme.py +++ b/tests/lint/test_readme.py @@ -10,7 +10,7 @@ import unittest from warnings import simplefilter, catch_warnings -from os.path import join +from pathlib import Path from vunit import ROOT from vunit.about import doc @@ -23,5 +23,5 @@ class TestReadMe(unittest.TestCase): def test_that_readme_file_matches_vunit_docstring(self): with catch_warnings(): simplefilter("ignore", category=DeprecationWarning) - with open(join(ROOT, "README.rst"), "rU") as readme: + with Path(ROOT, "README.rst").open("rU") as readme: self.assertEqual(readme.read(), doc()) diff --git a/tests/unit/test_activehdl_interface.py b/tests/unit/test_activehdl_interface.py index 0848df920..d01952fc2 100644 --- a/tests/unit/test_activehdl_interface.py +++ b/tests/unit/test_activehdl_interface.py @@ -10,7 +10,7 @@ import unittest -from os.path import join, dirname, exists +from pathlib import Path import os from shutil import rmtree from unittest import mock @@ -58,18 +58,18 @@ def test_compile_project_vhdl_2008(self, process, check_output): ) simif.compile_project(project) process.assert_any_call( - [join("prefix", "vlib"), "lib", "lib_path"], + [str(Path("prefix") / "vlib"), "lib", "lib_path"], cwd=self.output_path, env=simif.get_env(), ) process.assert_called_with( - [join("prefix", "vmap"), "lib", "lib_path"], + [str(Path("prefix") / "vmap"), "lib", "lib_path"], cwd=self.output_path, env=simif.get_env(), ) check_output.assert_called_once_with( [ - join("prefix", "vcom"), + str(Path("prefix") / "vcom"), "-quiet", "-j", self.output_path, @@ -93,18 +93,18 @@ def test_compile_project_vhdl_2002(self, process, check_output): ) simif.compile_project(project) process.assert_any_call( - [join("prefix", "vlib"), "lib", "lib_path"], + [str(Path("prefix") / "vlib"), "lib", "lib_path"], cwd=self.output_path, env=simif.get_env(), ) process.assert_called_with( - [join("prefix", "vmap"), "lib", "lib_path"], + [str(Path("prefix") / "vmap"), "lib", "lib_path"], cwd=self.output_path, env=simif.get_env(), ) check_output.assert_called_once_with( [ - join("prefix", "vcom"), + str(Path("prefix") / "vcom"), "-quiet", "-j", self.output_path, @@ -128,18 +128,18 @@ def test_compile_project_vhdl_93(self, process, check_output): ) simif.compile_project(project) process.assert_any_call( - [join("prefix", "vlib"), "lib", "lib_path"], + [str(Path("prefix") / "vlib"), "lib", "lib_path"], cwd=self.output_path, env=simif.get_env(), ) process.assert_called_with( - [join("prefix", "vmap"), "lib", "lib_path"], + [str(Path("prefix") / "vmap"), "lib", "lib_path"], cwd=self.output_path, env=simif.get_env(), ) check_output.assert_called_once_with( [ - join("prefix", "vcom"), + str(Path("prefix") / "vcom"), "-quiet", "-j", self.output_path, @@ -162,18 +162,18 @@ def test_compile_project_vhdl_extra_flags(self, process, check_output): source_file.set_compile_option("activehdl.vcom_flags", ["custom", "flags"]) simif.compile_project(project) process.assert_any_call( - [join("prefix", "vlib"), "lib", "lib_path"], + [str(Path("prefix") / "vlib"), "lib", "lib_path"], cwd=self.output_path, env=simif.get_env(), ) process.assert_called_with( - [join("prefix", "vmap"), "lib", "lib_path"], + [str(Path("prefix") / "vmap"), "lib", "lib_path"], cwd=self.output_path, env=simif.get_env(), ) check_output.assert_called_once_with( [ - join("prefix", "vcom"), + str(Path("prefix") / "vcom"), "-quiet", "-j", self.output_path, @@ -190,7 +190,7 @@ def test_compile_project_vhdl_extra_flags(self, process, check_output): @mock.patch("vunit.sim_if.check_output", autospec=True, return_value="") @mock.patch("vunit.sim_if.activehdl.Process", autospec=True) def test_compile_project_verilog(self, process, check_output): - library_cfg = join(self.output_path, "library.cfg") + library_cfg = str(Path(self.output_path) / "library.cfg") simif = ActiveHDLInterface(prefix="prefix", output_path=self.output_path) project = Project() project.add_library("lib", "lib_path") @@ -198,18 +198,18 @@ def test_compile_project_verilog(self, process, check_output): project.add_source_file("file.v", "lib", file_type="verilog") simif.compile_project(project) process.assert_any_call( - [join("prefix", "vlib"), "lib", "lib_path"], + [str(Path("prefix") / "vlib"), "lib", "lib_path"], cwd=self.output_path, env=simif.get_env(), ) process.assert_called_with( - [join("prefix", "vmap"), "lib", "lib_path"], + [str(Path("prefix") / "vmap"), "lib", "lib_path"], cwd=self.output_path, env=simif.get_env(), ) check_output.assert_called_once_with( [ - join("prefix", "vlog"), + str(Path("prefix") / "vlog"), "-quiet", "-lc", library_cfg, @@ -225,7 +225,7 @@ def test_compile_project_verilog(self, process, check_output): @mock.patch("vunit.sim_if.check_output", autospec=True, return_value="") @mock.patch("vunit.sim_if.activehdl.Process", autospec=True) def test_compile_project_system_verilog(self, process, check_output): - library_cfg = join(self.output_path, "library.cfg") + library_cfg = str(Path(self.output_path) / "library.cfg") simif = ActiveHDLInterface(prefix="prefix", output_path=self.output_path) project = Project() project.add_library("lib", "lib_path") @@ -233,18 +233,18 @@ def test_compile_project_system_verilog(self, process, check_output): project.add_source_file("file.sv", "lib", file_type="systemverilog") simif.compile_project(project) process.assert_any_call( - [join("prefix", "vlib"), "lib", "lib_path"], + [str(Path("prefix") / "vlib"), "lib", "lib_path"], cwd=self.output_path, env=simif.get_env(), ) process.assert_called_with( - [join("prefix", "vmap"), "lib", "lib_path"], + [str(Path("prefix") / "vmap"), "lib", "lib_path"], cwd=self.output_path, env=simif.get_env(), ) check_output.assert_called_once_with( [ - join("prefix", "vlog"), + str(Path("prefix") / "vlog"), "-quiet", "-lc", library_cfg, @@ -260,7 +260,7 @@ def test_compile_project_system_verilog(self, process, check_output): @mock.patch("vunit.sim_if.check_output", autospec=True, return_value="") @mock.patch("vunit.sim_if.activehdl.Process", autospec=True) def test_compile_project_verilog_extra_flags(self, process, check_output): - library_cfg = join(self.output_path, "library.cfg") + library_cfg = str(Path(self.output_path) / "library.cfg") simif = ActiveHDLInterface(prefix="prefix", output_path=self.output_path) project = Project() project.add_library("lib", "lib_path") @@ -269,18 +269,18 @@ def test_compile_project_verilog_extra_flags(self, process, check_output): source_file.set_compile_option("activehdl.vlog_flags", ["custom", "flags"]) simif.compile_project(project) process.assert_any_call( - [join("prefix", "vlib"), "lib", "lib_path"], + [str(Path("prefix") / "vlib"), "lib", "lib_path"], cwd=self.output_path, env=simif.get_env(), ) process.assert_called_with( - [join("prefix", "vmap"), "lib", "lib_path"], + [str(Path("prefix") / "vmap"), "lib", "lib_path"], cwd=self.output_path, env=simif.get_env(), ) check_output.assert_called_once_with( [ - join("prefix", "vlog"), + str(Path("prefix") / "vlog"), "-quiet", "-lc", library_cfg, @@ -298,7 +298,7 @@ def test_compile_project_verilog_extra_flags(self, process, check_output): @mock.patch("vunit.sim_if.check_output", autospec=True, return_value="") @mock.patch("vunit.sim_if.activehdl.Process", autospec=True) def test_compile_project_verilog_include(self, process, check_output): - library_cfg = join(self.output_path, "library.cfg") + library_cfg = str(Path(self.output_path) / "library.cfg") simif = ActiveHDLInterface(prefix="prefix", output_path=self.output_path) project = Project() project.add_library("lib", "lib_path") @@ -308,18 +308,18 @@ def test_compile_project_verilog_include(self, process, check_output): ) simif.compile_project(project) process.assert_any_call( - [join("prefix", "vlib"), "lib", "lib_path"], + [str(Path("prefix") / "vlib"), "lib", "lib_path"], cwd=self.output_path, env=simif.get_env(), ) process.assert_called_with( - [join("prefix", "vmap"), "lib", "lib_path"], + [str(Path("prefix") / "vmap"), "lib", "lib_path"], cwd=self.output_path, env=simif.get_env(), ) check_output.assert_called_once_with( [ - join("prefix", "vlog"), + str(Path("prefix") / "vlog"), "-quiet", "-lc", library_cfg, @@ -336,7 +336,7 @@ def test_compile_project_verilog_include(self, process, check_output): @mock.patch("vunit.sim_if.check_output", autospec=True, return_value="") @mock.patch("vunit.sim_if.activehdl.Process", autospec=True) def test_compile_project_verilog_define(self, process, check_output): - library_cfg = join(self.output_path, "library.cfg") + library_cfg = str(Path(self.output_path) / "library.cfg") simif = ActiveHDLInterface(prefix="prefix", output_path=self.output_path) project = Project() project.add_library("lib", "lib_path") @@ -346,18 +346,18 @@ def test_compile_project_verilog_define(self, process, check_output): ) simif.compile_project(project) process.assert_any_call( - [join("prefix", "vlib"), "lib", "lib_path"], + [str(Path("prefix") / "vlib"), "lib", "lib_path"], cwd=self.output_path, env=simif.get_env(), ) process.assert_called_with( - [join("prefix", "vmap"), "lib", "lib_path"], + [str(Path("prefix") / "vmap"), "lib", "lib_path"], cwd=self.output_path, env=simif.get_env(), ) check_output.assert_called_once_with( [ - join("prefix", "vlog"), + str(Path("prefix") / "vlog"), "-quiet", "-lc", library_cfg, @@ -390,7 +390,7 @@ def test_supports_vhdl_package_generics_false(self, find_prefix): self.assertFalse(simif.supports_vhdl_package_generics()) def setUp(self): - self.output_path = join(dirname(__file__), "test_activehdl_out") + self.output_path = str(Path(__file__).parent / "test_activehdl_out") renew_path(self.output_path) self.project = Project() self.cwd = os.getcwd() @@ -398,7 +398,7 @@ def setUp(self): def tearDown(self): os.chdir(self.cwd) - if exists(self.output_path): + if Path(self.output_path).exists(): rmtree(self.output_path) diff --git a/tests/unit/test_configuration.py b/tests/unit/test_configuration.py index da56de9cc..aa6b598ea 100644 --- a/tests/unit/test_configuration.py +++ b/tests/unit/test_configuration.py @@ -13,7 +13,7 @@ import unittest import contextlib -from os.path import join +from pathlib import Path from unittest import mock from tests.common import with_tempdir, create_tempdir from tests.unit.test_test_bench import Entity @@ -61,10 +61,12 @@ def test_does_not_add_tb_path_generic(self): @with_tempdir def test_adds_tb_path_generic(self, tempdir): design_unit_tb_path = Entity( - "tb_entity_without_tb_path", file_name=join(tempdir, "file.vhd") + "tb_entity_without_tb_path", file_name=str(Path(tempdir) / "file.vhd") + ) + tb_path = str(Path(tempdir) / "other_path") + design_unit_tb_path.original_file_name = str( + Path(tb_path) / "original_file.vhd" ) - tb_path = join(tempdir, "other_path") - design_unit_tb_path.original_file_name = join(tb_path, "original_file.vhd") design_unit_tb_path.generic_names = ["runner_cfg", "tb_path"] config_tb_path = Configuration("name", design_unit_tb_path) self.assertEqual( @@ -298,7 +300,7 @@ def _create_config(**kwargs): Helper function to create a config """ with create_tempdir() as tempdir: - design_unit = Entity("tb_entity", file_name=join(tempdir, "file.vhd")) + design_unit = Entity("tb_entity", file_name=str(Path(tempdir) / "file.vhd")) design_unit.generic_names = ["runner_cfg"] yield Configuration("name", design_unit, **kwargs) diff --git a/tests/unit/test_csv_logs.py b/tests/unit/test_csv_logs.py index 34fd1c9fb..cca5bd5a7 100644 --- a/tests/unit/test_csv_logs.py +++ b/tests/unit/test_csv_logs.py @@ -11,7 +11,7 @@ import unittest from shutil import rmtree from os import remove -from os.path import join +from pathlib import Path from tempfile import NamedTemporaryFile, mkdtemp from vunit.csv_logs import CsvLogs @@ -25,8 +25,8 @@ def setUp(self): self._log_files = [] self._all_fields_dir = mkdtemp() self._few_fields_dir = mkdtemp() - self._all_fields_files = join(self._all_fields_dir, "*.csv") - self._few_fields_files = join(self._few_fields_dir, "*.csv") + self._all_fields_files = str(Path(self._all_fields_dir) / "*.csv") + self._few_fields_files = str(Path(self._few_fields_dir) / "*.csv") def make_log(directory, contents): """ diff --git a/tests/unit/test_database.py b/tests/unit/test_database.py index f01bd47ae..f07104bd6 100644 --- a/tests/unit/test_database.py +++ b/tests/unit/test_database.py @@ -9,7 +9,7 @@ """ import unittest -from os.path import join +from pathlib import Path from tests.common import with_tempdir from vunit.database import DataBase, PickledDataBase @@ -26,7 +26,7 @@ class TestDataBase(unittest.TestCase): @staticmethod def create_database(tempdir, new=False): - return DataBase(join(tempdir, "database"), new=new) + return DataBase(str(Path(tempdir) / "database"), new=new) def _test_add_items(self, tempdir): """ diff --git a/tests/unit/test_ghdl_interface.py b/tests/unit/test_ghdl_interface.py index 9414ccdf1..2698f4d2d 100644 --- a/tests/unit/test_ghdl_interface.py +++ b/tests/unit/test_ghdl_interface.py @@ -9,7 +9,7 @@ """ import unittest -from os.path import join, dirname, exists +from pathlib import Path import os from shutil import rmtree from unittest import mock @@ -120,7 +120,7 @@ def test_compile_project_2008(self, check_output): simif.compile_project(project) check_output.assert_called_once_with( [ - join("prefix", "ghdl"), + str(Path("prefix") / "ghdl"), "-a", "--workdir=lib_path", "--work=lib", @@ -146,7 +146,7 @@ def test_compile_project_2002(self, check_output): simif.compile_project(project) check_output.assert_called_once_with( [ - join("prefix", "ghdl"), + str(Path("prefix") / "ghdl"), "-a", "--workdir=lib_path", "--work=lib", @@ -172,7 +172,7 @@ def test_compile_project_93(self, check_output): simif.compile_project(project) check_output.assert_called_once_with( [ - join("prefix", "ghdl"), + str(Path("prefix") / "ghdl"), "-a", "--workdir=lib_path", "--work=lib", @@ -197,7 +197,7 @@ def test_compile_project_extra_flags(self, check_output): simif.compile_project(project) check_output.assert_called_once_with( [ - join("prefix", "ghdl"), + str(Path("prefix") / "ghdl"), "-a", "--workdir=lib_path", "--work=lib", @@ -211,9 +211,9 @@ def test_compile_project_extra_flags(self, check_output): ) def test_elaborate_e_project(self): - design_unit = Entity("tb_entity", file_name=join("tempdir", "file.vhd")) - design_unit.original_file_name = join( - "tempdir", "other_path", "original_file.vhd" + design_unit = Entity("tb_entity", file_name=str(Path("tempdir") / "file.vhd")) + design_unit.original_file_name = str( + Path("tempdir") / "other_path" / "original_file.vhd" ) design_unit.generic_names = ["runner_cfg", "tb_path"] @@ -228,17 +228,17 @@ def test_elaborate_e_project(self): self.assertEqual( simif._get_command( # pylint: disable=protected-access - config, join("output_path", "ghdl"), True, True, None + config, str(Path("output_path") / "ghdl"), True, True, None ), [ - join("prefix", "ghdl"), + str(Path("prefix") / "ghdl"), "-e", "--std=08", "--work=lib", "--workdir=lib_path", "-Plib_path", "-o", - join("output_path", "ghdl", "tb_entity-arch"), + str(Path("output_path") / "ghdl" / "tb_entity-arch"), "tb_entity", "arch", ], @@ -254,7 +254,7 @@ def test_compile_project_verilog_error(self): self.assertRaises(CompileError, simif.compile_project, project) def setUp(self): - self.output_path = join(dirname(__file__), "test_ghdl_interface_out") + self.output_path = str(Path(__file__).parent / "test_ghdl_interface_out") renew_path(self.output_path) self.project = Project() self.cwd = os.getcwd() @@ -262,5 +262,5 @@ def setUp(self): def tearDown(self): os.chdir(self.cwd) - if exists(self.output_path): + if Path(self.output_path).exists(): rmtree(self.output_path) diff --git a/tests/unit/test_incisive_interface.py b/tests/unit/test_incisive_interface.py index c584f991a..7f6829c10 100644 --- a/tests/unit/test_incisive_interface.py +++ b/tests/unit/test_incisive_interface.py @@ -12,7 +12,7 @@ import unittest -from os.path import join, dirname, exists, basename +from pathlib import Path import os from shutil import rmtree from unittest import mock @@ -44,9 +44,9 @@ def test_compile_project_vhdl_2008( "file.vhd", "lib", file_type="vhdl", vhdl_standard=VHDL.standard("2008") ) simif.compile_project(project) - args_file = join(self.output_path, "irun_compile_vhdl_file_lib.args") + args_file = str(Path(self.output_path) / "irun_compile_vhdl_file_lib.args") check_output.assert_called_once_with( - [join("prefix", "irun"), "-f", args_file], env=simif.get_env() + [str(Path("prefix") / "irun"), "-f", args_file], env=simif.get_env() ) self.assertEqual( read_file(args_file).splitlines(), @@ -58,10 +58,11 @@ def test_compile_project_vhdl_2008( "-nowarn DLCVAR", "-v200x -extv200x", "-work work", - '-cdslib "%s"' % join(self.output_path, "cds.lib"), - '-log "%s"' % join(self.output_path, "irun_compile_vhdl_file_lib.log"), + '-cdslib "%s"' % str(Path(self.output_path) / "cds.lib"), + '-log "%s"' + % str(Path(self.output_path) / "irun_compile_vhdl_file_lib.log"), "-quiet", - '-nclibdirname ""', + '-nclibdirname "."', "-makelib lib_path", '"file.vhd"', "-endlib", @@ -69,7 +70,7 @@ def test_compile_project_vhdl_2008( ) self.assertEqual( - read_file(join(self.output_path, "cds.lib")), + read_file(str(Path(self.output_path) / "cds.lib")), """\ ## cds.lib: Defines the locations of compiled libraries. softinclude cds_root_irun/tools/inca/files/cds.lib @@ -98,9 +99,9 @@ def test_compile_project_vhdl_2002( "file.vhd", "lib", file_type="vhdl", vhdl_standard=VHDL.standard("2002") ) simif.compile_project(project) - args_file = join(self.output_path, "irun_compile_vhdl_file_lib.args") + args_file = str(Path(self.output_path) / "irun_compile_vhdl_file_lib.args") check_output.assert_called_once_with( - [join("prefix", "irun"), "-f", args_file], env=simif.get_env() + [str(Path("prefix") / "irun"), "-f", args_file], env=simif.get_env() ) self.assertEqual( read_file(args_file).splitlines(), @@ -112,10 +113,11 @@ def test_compile_project_vhdl_2002( "-nowarn DLCVAR", "-v200x -extv200x", "-work work", - '-cdslib "%s"' % join(self.output_path, "cds.lib"), - '-log "%s"' % join(self.output_path, "irun_compile_vhdl_file_lib.log"), + '-cdslib "%s"' % str(Path(self.output_path) / "cds.lib"), + '-log "%s"' + % str(Path(self.output_path) / "irun_compile_vhdl_file_lib.log"), "-quiet", - '-nclibdirname ""', + '-nclibdirname "."', "-makelib lib_path", '"file.vhd"', "-endlib", @@ -138,9 +140,9 @@ def test_compile_project_vhdl_93( "file.vhd", "lib", file_type="vhdl", vhdl_standard=VHDL.standard("93") ) simif.compile_project(project) - args_file = join(self.output_path, "irun_compile_vhdl_file_lib.args") + args_file = str(Path(self.output_path) / "irun_compile_vhdl_file_lib.args") check_output.assert_called_once_with( - [join("prefix", "irun"), "-f", args_file], env=simif.get_env() + [str(Path("prefix") / "irun"), "-f", args_file], env=simif.get_env() ) self.assertEqual( read_file(args_file).splitlines(), @@ -152,10 +154,11 @@ def test_compile_project_vhdl_93( "-nowarn DLCVAR", "-v93", "-work work", - '-cdslib "%s"' % join(self.output_path, "cds.lib"), - '-log "%s"' % join(self.output_path, "irun_compile_vhdl_file_lib.log"), + '-cdslib "%s"' % str(Path(self.output_path) / "cds.lib"), + '-log "%s"' + % str(Path(self.output_path) / "irun_compile_vhdl_file_lib.log"), "-quiet", - '-nclibdirname ""', + '-nclibdirname "."', "-makelib lib_path", '"file.vhd"', "-endlib", @@ -177,9 +180,9 @@ def test_compile_project_vhdl_extra_flags( source_file = project.add_source_file("file.vhd", "lib", file_type="vhdl") source_file.set_compile_option("incisive.irun_vhdl_flags", ["custom", "flags"]) simif.compile_project(project) - args_file = join(self.output_path, "irun_compile_vhdl_file_lib.args") + args_file = str(Path(self.output_path) / "irun_compile_vhdl_file_lib.args") check_output.assert_called_once_with( - [join("prefix", "irun"), "-f", args_file], env=simif.get_env() + [str(Path("prefix") / "irun"), "-f", args_file], env=simif.get_env() ) self.assertEqual( read_file(args_file).splitlines(), @@ -191,12 +194,13 @@ def test_compile_project_vhdl_extra_flags( "-nowarn DLCVAR", "-v200x -extv200x", "-work work", - '-cdslib "%s"' % join(self.output_path, "cds.lib"), - '-log "%s"' % join(self.output_path, "irun_compile_vhdl_file_lib.log"), + '-cdslib "%s"' % str(Path(self.output_path) / "cds.lib"), + '-log "%s"' + % str(Path(self.output_path) / "irun_compile_vhdl_file_lib.log"), "-quiet", "custom", "flags", - '-nclibdirname ""', + '-nclibdirname "."', "-makelib lib_path", '"file.vhd"', "-endlib", @@ -219,9 +223,9 @@ def test_compile_project_vhdl_hdlvar( write_file("file.vhd", "") project.add_source_file("file.vhd", "lib", file_type="vhdl") simif.compile_project(project) - args_file = join(self.output_path, "irun_compile_vhdl_file_lib.args") + args_file = str(Path(self.output_path) / "irun_compile_vhdl_file_lib.args") check_output.assert_called_once_with( - [join("prefix", "irun"), "-f", args_file], env=simif.get_env() + [str(Path("prefix") / "irun"), "-f", args_file], env=simif.get_env() ) self.assertEqual( read_file(args_file).splitlines(), @@ -233,11 +237,12 @@ def test_compile_project_vhdl_hdlvar( "-nowarn DLCVAR", "-v200x -extv200x", "-work work", - '-cdslib "%s"' % join(self.output_path, "cds.lib"), + '-cdslib "%s"' % str(Path(self.output_path) / "cds.lib"), '-hdlvar "custom_hdlvar"', - '-log "%s"' % join(self.output_path, "irun_compile_vhdl_file_lib.log"), + '-log "%s"' + % str(Path(self.output_path) / "irun_compile_vhdl_file_lib.log"), "-quiet", - '-nclibdirname ""', + '-nclibdirname "."', "-makelib lib_path", '"file.vhd"', "-endlib", @@ -258,9 +263,9 @@ def test_compile_project_verilog( write_file("file.v", "") project.add_source_file("file.v", "lib", file_type="verilog") simif.compile_project(project) - args_file = join(self.output_path, "irun_compile_verilog_file_lib.args") + args_file = str(Path(self.output_path) / "irun_compile_verilog_file_lib.args") check_output.assert_called_once_with( - [join("prefix", "irun"), "-f", args_file], env=simif.get_env() + [str(Path("prefix") / "irun"), "-f", args_file], env=simif.get_env() ) self.assertEqual( read_file(args_file).splitlines(), @@ -272,12 +277,12 @@ def test_compile_project_verilog( "-nowarn DLCPTH", "-nowarn DLCVAR", "-work work", - '-cdslib "%s"' % join(self.output_path, "cds.lib"), + '-cdslib "%s"' % str(Path(self.output_path) / "cds.lib"), '-log "%s"' - % join(self.output_path, "irun_compile_verilog_file_lib.log"), + % str(Path(self.output_path) / "irun_compile_verilog_file_lib.log"), "-quiet", '-incdir "cds_root_irun/tools/spectre/etc/ahdl/"', - '-nclibdirname ""', + '-nclibdirname "."', "-makelib lib", '"file.v"', "-endlib", @@ -298,9 +303,9 @@ def test_compile_project_system_verilog( write_file("file.sv", "") project.add_source_file("file.sv", "lib", file_type="systemverilog") simif.compile_project(project) - args_file = join(self.output_path, "irun_compile_verilog_file_lib.args") + args_file = str(Path(self.output_path) / "irun_compile_verilog_file_lib.args") check_output.assert_called_once_with( - [join("prefix", "irun"), "-f", args_file], env=simif.get_env() + [str(Path("prefix") / "irun"), "-f", args_file], env=simif.get_env() ) self.assertEqual( read_file(args_file).splitlines(), @@ -312,12 +317,12 @@ def test_compile_project_system_verilog( "-nowarn DLCPTH", "-nowarn DLCVAR", "-work work", - '-cdslib "%s"' % join(self.output_path, "cds.lib"), + '-cdslib "%s"' % str(Path(self.output_path) / "cds.lib"), '-log "%s"' - % join(self.output_path, "irun_compile_verilog_file_lib.log"), + % str(Path(self.output_path) / "irun_compile_verilog_file_lib.log"), "-quiet", '-incdir "cds_root_irun/tools/spectre/etc/ahdl/"', - '-nclibdirname ""', + '-nclibdirname "."', "-makelib lib", '"file.sv"', "-endlib", @@ -325,7 +330,7 @@ def test_compile_project_system_verilog( ) self.assertEqual( - read_file(join(self.output_path, "cds.lib")), + read_file(str(Path(self.output_path) / "cds.lib")), """\ ## cds.lib: Defines the locations of compiled libraries. softinclude cds_root_irun/tools/inca/files/cds.lib @@ -355,9 +360,9 @@ def test_compile_project_verilog_extra_flags( "incisive.irun_verilog_flags", ["custom", "flags"] ) simif.compile_project(project) - args_file = join(self.output_path, "irun_compile_verilog_file_lib.args") + args_file = str(Path(self.output_path) / "irun_compile_verilog_file_lib.args") check_output.assert_called_once_with( - [join("prefix", "irun"), "-f", args_file], env=simif.get_env() + [str(Path("prefix") / "irun"), "-f", args_file], env=simif.get_env() ) self.assertEqual( read_file(args_file).splitlines(), @@ -371,12 +376,12 @@ def test_compile_project_verilog_extra_flags( "-work work", "custom", "flags", - '-cdslib "%s"' % join(self.output_path, "cds.lib"), + '-cdslib "%s"' % str(Path(self.output_path) / "cds.lib"), '-log "%s"' - % join(self.output_path, "irun_compile_verilog_file_lib.log"), + % str(Path(self.output_path) / "irun_compile_verilog_file_lib.log"), "-quiet", '-incdir "cds_root_irun/tools/spectre/etc/ahdl/"', - '-nclibdirname ""', + '-nclibdirname "."', "-makelib lib", '"file.v"', "-endlib", @@ -399,9 +404,9 @@ def test_compile_project_verilog_include( "file.v", "lib", file_type="verilog", include_dirs=["include"] ) simif.compile_project(project) - args_file = join(self.output_path, "irun_compile_verilog_file_lib.args") + args_file = str(Path(self.output_path) / "irun_compile_verilog_file_lib.args") check_output.assert_called_once_with( - [join("prefix", "irun"), "-f", args_file], env=simif.get_env() + [str(Path("prefix") / "irun"), "-f", args_file], env=simif.get_env() ) self.assertEqual( read_file(args_file).splitlines(), @@ -413,13 +418,13 @@ def test_compile_project_verilog_include( "-nowarn DLCPTH", "-nowarn DLCVAR", "-work work", - '-cdslib "%s"' % join(self.output_path, "cds.lib"), + '-cdslib "%s"' % str(Path(self.output_path) / "cds.lib"), '-log "%s"' - % join(self.output_path, "irun_compile_verilog_file_lib.log"), + % str(Path(self.output_path) / "irun_compile_verilog_file_lib.log"), "-quiet", '-incdir "include"', '-incdir "cds_root_irun/tools/spectre/etc/ahdl/"', - '-nclibdirname ""', + '-nclibdirname "."', "-makelib lib", '"file.v"', "-endlib", @@ -442,9 +447,9 @@ def test_compile_project_verilog_define( "file.v", "lib", file_type="verilog", defines=dict(defname="defval") ) simif.compile_project(project) - args_file = join(self.output_path, "irun_compile_verilog_file_lib.args") + args_file = str(Path(self.output_path) / "irun_compile_verilog_file_lib.args") check_output.assert_called_once_with( - [join("prefix", "irun"), "-f", args_file], env=simif.get_env() + [str(Path("prefix") / "irun"), "-f", args_file], env=simif.get_env() ) self.assertEqual( read_file(args_file).splitlines(), @@ -456,13 +461,13 @@ def test_compile_project_verilog_define( "-nowarn DLCPTH", "-nowarn DLCVAR", "-work work", - '-cdslib "%s"' % join(self.output_path, "cds.lib"), + '-cdslib "%s"' % str(Path(self.output_path) / "cds.lib"), '-log "%s"' - % join(self.output_path, "irun_compile_verilog_file_lib.log"), + % str(Path(self.output_path) / "irun_compile_verilog_file_lib.log"), "-quiet", '-incdir "cds_root_irun/tools/spectre/etc/ahdl/"', "-define defname=defval", - '-nclibdirname ""', + '-nclibdirname "."', "-makelib lib", '"file.v"', "-endlib", @@ -487,9 +492,9 @@ def test_compile_project_verilog_hdlvar( "file.v", "lib", file_type="verilog", defines=dict(defname="defval") ) simif.compile_project(project) - args_file = join(self.output_path, "irun_compile_verilog_file_lib.args") + args_file = str(Path(self.output_path) / "irun_compile_verilog_file_lib.args") check_output.assert_called_once_with( - [join("prefix", "irun"), "-f", args_file], env=simif.get_env() + [str(Path("prefix") / "irun"), "-f", args_file], env=simif.get_env() ) self.assertEqual( read_file(args_file).splitlines(), @@ -501,14 +506,14 @@ def test_compile_project_verilog_hdlvar( "-nowarn DLCPTH", "-nowarn DLCVAR", "-work work", - '-cdslib "%s"' % join(self.output_path, "cds.lib"), + '-cdslib "%s"' % str(Path(self.output_path) / "cds.lib"), '-hdlvar "custom_hdlvar"', '-log "%s"' - % join(self.output_path, "irun_compile_verilog_file_lib.log"), + % str(Path(self.output_path) / "irun_compile_verilog_file_lib.log"), "-quiet", '-incdir "cds_root_irun/tools/spectre/etc/ahdl/"', "-define defname=defval", - '-nclibdirname ""', + '-nclibdirname "."', "-makelib lib", '"file.v"', "-endlib", @@ -522,7 +527,7 @@ def test_create_cds_lib(self, find_cds_root_irun, find_cds_root_virtuoso): find_cds_root_virtuoso.return_value = None IncisiveInterface(prefix="prefix", output_path=self.output_path) self.assertEqual( - read_file(join(self.output_path, "cds.lib")), + read_file(str(Path(self.output_path) / "cds.lib")), """\ ## cds.lib: Defines the locations of compiled libraries. softinclude cds_root_irun/tools/inca/files/cds.lib @@ -541,7 +546,7 @@ def test_create_cds_lib_virtuoso(self, find_cds_root_irun, find_cds_root_virtuos find_cds_root_virtuoso.return_value = "cds_root_virtuoso" IncisiveInterface(prefix="prefix", output_path=self.output_path) self.assertEqual( - read_file(join(self.output_path, "cds.lib")), + read_file(str(Path(self.output_path) / "cds.lib")), """\ ## cds.lib: Defines the locations of compiled libraries. softinclude cds_root_irun/tools/inca/files/cds.lib @@ -574,20 +579,26 @@ def test_simulate_vhdl( config = make_config() self.assertTrue(simif.simulate("suite_output_path", "test_suite_name", config)) - elaborate_args_file = join( - "suite_output_path", simif.name, "irun_elaborate.args" + elaborate_args_file = str( + Path("suite_output_path") / simif.name / "irun_elaborate.args" + ) + simulate_args_file = str( + Path("suite_output_path") / simif.name / "irun_simulate.args" ) - simulate_args_file = join("suite_output_path", simif.name, "irun_simulate.args") run_command.assert_has_calls( [ mock.call( - [join("prefix", "irun"), "-f", basename(elaborate_args_file)], - cwd=dirname(elaborate_args_file), + [ + str(Path("prefix") / "irun"), + "-f", + Path(elaborate_args_file).name, + ], + cwd=str(Path(elaborate_args_file).parent), env=simif.get_env(), ), mock.call( - [join("prefix", "irun"), "-f", basename(simulate_args_file)], - cwd=dirname(simulate_args_file), + [str(Path("prefix") / "irun"), "-f", Path(simulate_args_file).name], + cwd=str(Path(simulate_args_file).parent), env=simif.get_env(), ), ] @@ -607,10 +618,10 @@ def test_simulate_vhdl( "-ncerror EVBSTR", "-ncerror EVBNAT", "-work work", - '-nclibdirname "%s"' % join(self.output_path, "libraries"), - '-cdslib "%s"' % join(self.output_path, "cds.lib"), + '-nclibdirname "%s"' % str(Path(self.output_path) / "libraries"), + '-cdslib "%s"' % str(Path(self.output_path) / "cds.lib"), '-log "%s"' - % join("suite_output_path", simif.name, "irun_elaborate.log"), + % str(Path("suite_output_path") / simif.name / "irun_elaborate.log"), "-quiet", '-reflib "lib_path"', "-access +r", @@ -632,10 +643,10 @@ def test_simulate_vhdl( "-ncerror EVBSTR", "-ncerror EVBNAT", "-work work", - '-nclibdirname "%s"' % join(self.output_path, "libraries"), - '-cdslib "%s"' % join(self.output_path, "cds.lib"), + '-nclibdirname "%s"' % str(Path(self.output_path) / "libraries"), + '-cdslib "%s"' % str(Path(self.output_path) / "cds.lib"), '-log "%s"' - % join("suite_output_path", simif.name, "irun_simulate.log"), + % str(Path("suite_output_path") / simif.name / "irun_simulate.log"), "-quiet", '-reflib "lib_path"', "-access +r", @@ -666,20 +677,26 @@ def test_simulate_verilog( config = make_config(verilog=True) self.assertTrue(simif.simulate("suite_output_path", "test_suite_name", config)) - elaborate_args_file = join( - "suite_output_path", simif.name, "irun_elaborate.args" + elaborate_args_file = str( + Path("suite_output_path") / simif.name / "irun_elaborate.args" + ) + simulate_args_file = str( + Path("suite_output_path") / simif.name / "irun_simulate.args" ) - simulate_args_file = join("suite_output_path", simif.name, "irun_simulate.args") run_command.assert_has_calls( [ mock.call( - [join("prefix", "irun"), "-f", basename(elaborate_args_file)], - cwd=dirname(elaborate_args_file), + [ + str(Path("prefix") / "irun"), + "-f", + Path(elaborate_args_file).name, + ], + cwd=str(Path(elaborate_args_file).parent), env=simif.get_env(), ), mock.call( - [join("prefix", "irun"), "-f", basename(simulate_args_file)], - cwd=dirname(simulate_args_file), + [str(Path("prefix") / "irun"), "-f", Path(simulate_args_file).name], + cwd=str(Path(simulate_args_file).parent), env=simif.get_env(), ), ] @@ -699,10 +716,10 @@ def test_simulate_verilog( "-ncerror EVBSTR", "-ncerror EVBNAT", "-work work", - '-nclibdirname "%s"' % join(self.output_path, "libraries"), - '-cdslib "%s"' % join(self.output_path, "cds.lib"), + '-nclibdirname "%s"' % str(Path(self.output_path) / "libraries"), + '-cdslib "%s"' % str(Path(self.output_path) / "cds.lib"), '-log "%s"' - % join("suite_output_path", simif.name, "irun_elaborate.log"), + % str(Path("suite_output_path") / simif.name / "irun_elaborate.log"), "-quiet", '-reflib "lib_path"', "-access +r", @@ -724,10 +741,10 @@ def test_simulate_verilog( "-ncerror EVBSTR", "-ncerror EVBNAT", "-work work", - '-nclibdirname "%s"' % join(self.output_path, "libraries"), - '-cdslib "%s"' % join(self.output_path, "cds.lib"), + '-nclibdirname "%s"' % str(Path(self.output_path) / "libraries"), + '-cdslib "%s"' % str(Path(self.output_path) / "cds.lib"), '-log "%s"' - % join("suite_output_path", simif.name, "irun_simulate.log"), + % str(Path("suite_output_path") / simif.name / "irun_simulate.log"), "-quiet", '-reflib "lib_path"', "-access +r", @@ -749,20 +766,26 @@ def test_simulate_extra_flags( sim_options={"incisive.irun_sim_flags": ["custom", "flags"]} ) self.assertTrue(simif.simulate("suite_output_path", "test_suite_name", config)) - elaborate_args_file = join( - "suite_output_path", simif.name, "irun_elaborate.args" + elaborate_args_file = str( + Path("suite_output_path") / simif.name / "irun_elaborate.args" + ) + simulate_args_file = str( + Path("suite_output_path") / simif.name / "irun_simulate.args" ) - simulate_args_file = join("suite_output_path", simif.name, "irun_simulate.args") run_command.assert_has_calls( [ mock.call( - [join("prefix", "irun"), "-f", basename(elaborate_args_file)], - cwd=dirname(elaborate_args_file), + [ + str(Path("prefix") / "irun"), + "-f", + Path(elaborate_args_file).name, + ], + cwd=str(Path(elaborate_args_file).parent), env=simif.get_env(), ), mock.call( - [join("prefix", "irun"), "-f", basename(simulate_args_file)], - cwd=dirname(simulate_args_file), + [str(Path("prefix") / "irun"), "-f", Path(simulate_args_file).name], + cwd=str(Path(simulate_args_file).parent), env=simif.get_env(), ), ] @@ -789,20 +812,26 @@ def test_simulate_generics_and_parameters( verilog=True, generics={"genstr": "genval", "genint": 1, "genbool": True} ) self.assertTrue(simif.simulate("suite_output_path", "test_suite_name", config)) - elaborate_args_file = join( - "suite_output_path", simif.name, "irun_elaborate.args" + elaborate_args_file = str( + Path("suite_output_path") / simif.name / "irun_elaborate.args" + ) + simulate_args_file = str( + Path("suite_output_path") / simif.name / "irun_simulate.args" ) - simulate_args_file = join("suite_output_path", simif.name, "irun_simulate.args") run_command.assert_has_calls( [ mock.call( - [join("prefix", "irun"), "-f", basename(elaborate_args_file)], - cwd=dirname(elaborate_args_file), + [ + str(Path("prefix") / "irun"), + "-f", + Path(elaborate_args_file).name, + ], + cwd=str(Path(elaborate_args_file).parent), env=simif.get_env(), ), mock.call( - [join("prefix", "irun"), "-f", basename(simulate_args_file)], - cwd=dirname(simulate_args_file), + [str(Path("prefix") / "irun"), "-f", Path(simulate_args_file).name], + cwd=str(Path(simulate_args_file).parent), env=simif.get_env(), ), ] @@ -827,20 +856,26 @@ def test_simulate_hdlvar( ) config = make_config() self.assertTrue(simif.simulate("suite_output_path", "test_suite_name", config)) - elaborate_args_file = join( - "suite_output_path", simif.name, "irun_elaborate.args" + elaborate_args_file = str( + Path("suite_output_path") / simif.name / "irun_elaborate.args" + ) + simulate_args_file = str( + Path("suite_output_path") / simif.name / "irun_simulate.args" ) - simulate_args_file = join("suite_output_path", simif.name, "irun_simulate.args") run_command.assert_has_calls( [ mock.call( - [join("prefix", "irun"), "-f", basename(elaborate_args_file)], - cwd=dirname(elaborate_args_file), + [ + str(Path("prefix") / "irun"), + "-f", + Path(elaborate_args_file).name, + ], + cwd=str(Path(elaborate_args_file).parent), env=simif.get_env(), ), mock.call( - [join("prefix", "irun"), "-f", basename(simulate_args_file)], - cwd=dirname(simulate_args_file), + [str(Path("prefix") / "irun"), "-f", Path(simulate_args_file).name], + cwd=str(Path(simulate_args_file).parent), env=simif.get_env(), ), ] @@ -863,14 +898,18 @@ def test_elaborate(self, run_command, find_cds_root_irun, find_cds_root_virtuoso "suite_output_path", "test_suite_name", config, elaborate_only=True ) ) - elaborate_args_file = join( - "suite_output_path", simif.name, "irun_elaborate.args" + elaborate_args_file = str( + Path("suite_output_path") / simif.name / "irun_elaborate.args" ) run_command.assert_has_calls( [ mock.call( - [join("prefix", "irun"), "-f", basename(elaborate_args_file)], - cwd=dirname(elaborate_args_file), + [ + str(Path("prefix") / "irun"), + "-f", + Path(elaborate_args_file).name, + ], + cwd=str(Path(elaborate_args_file).parent), env=simif.get_env(), ) ] @@ -890,10 +929,10 @@ def test_elaborate(self, run_command, find_cds_root_irun, find_cds_root_virtuoso "-ncerror EVBSTR", "-ncerror EVBNAT", "-work work", - '-nclibdirname "%s"' % join(self.output_path, "libraries"), - '-cdslib "%s"' % join(self.output_path, "cds.lib"), + '-nclibdirname "%s"' % str(Path(self.output_path) / "libraries"), + '-cdslib "%s"' % str(Path(self.output_path) / "cds.lib"), '-log "%s"' - % join("suite_output_path", simif.name, "irun_elaborate.log"), + % str(Path("suite_output_path") / simif.name / "irun_elaborate.log"), "-quiet", "-access +r", '-input "@run"', @@ -912,14 +951,18 @@ def test_elaborate_fail( simif = IncisiveInterface(prefix="prefix", output_path=self.output_path) config = make_config() self.assertFalse(simif.simulate("suite_output_path", "test_suite_name", config)) - elaborate_args_file = join( - "suite_output_path", simif.name, "irun_elaborate.args" + elaborate_args_file = str( + Path("suite_output_path") / simif.name / "irun_elaborate.args" ) run_command.assert_has_calls( [ mock.call( - [join("prefix", "irun"), "-f", basename(elaborate_args_file)], - cwd=dirname(elaborate_args_file), + [ + str(Path("prefix") / "irun"), + "-f", + Path(elaborate_args_file).name, + ], + cwd=str(Path(elaborate_args_file).parent), env=simif.get_env(), ) ] @@ -938,20 +981,26 @@ def test_simulate_fail( simif = IncisiveInterface(prefix="prefix", output_path=self.output_path) config = make_config() self.assertFalse(simif.simulate("suite_output_path", "test_suite_name", config)) - elaborate_args_file = join( - "suite_output_path", simif.name, "irun_elaborate.args" + elaborate_args_file = str( + Path("suite_output_path") / simif.name / "irun_elaborate.args" + ) + simulate_args_file = str( + Path("suite_output_path") / simif.name / "irun_simulate.args" ) - simulate_args_file = join("suite_output_path", simif.name, "irun_simulate.args") run_command.assert_has_calls( [ mock.call( - [join("prefix", "irun"), "-f", basename(elaborate_args_file)], - cwd=dirname(elaborate_args_file), + [ + str(Path("prefix") / "irun"), + "-f", + Path(elaborate_args_file).name, + ], + cwd=str(Path(elaborate_args_file).parent), env=simif.get_env(), ), mock.call( - [join("prefix", "irun"), "-f", basename(simulate_args_file)], - cwd=dirname(simulate_args_file), + [str(Path("prefix") / "irun"), "-f", Path(simulate_args_file).name], + cwd=str(Path(simulate_args_file).parent), env=simif.get_env(), ), ] @@ -980,20 +1029,26 @@ def test_simulate_gui( simif.compile_project(project) config = make_config() self.assertTrue(simif.simulate("suite_output_path", "test_suite_name", config)) - elaborate_args_file = join( - "suite_output_path", simif.name, "irun_elaborate.args" + elaborate_args_file = str( + Path("suite_output_path") / simif.name / "irun_elaborate.args" + ) + simulate_args_file = str( + Path("suite_output_path") / simif.name / "irun_simulate.args" ) - simulate_args_file = join("suite_output_path", simif.name, "irun_simulate.args") run_command.assert_has_calls( [ mock.call( - [join("prefix", "irun"), "-f", basename(elaborate_args_file)], - cwd=dirname(elaborate_args_file), + [ + str(Path("prefix") / "irun"), + "-f", + Path(elaborate_args_file).name, + ], + cwd=str(Path(elaborate_args_file).parent), env=simif.get_env(), ), mock.call( - [join("prefix", "irun"), "-f", basename(simulate_args_file)], - cwd=dirname(simulate_args_file), + [str(Path("prefix") / "irun"), "-f", Path(simulate_args_file).name], + cwd=str(Path(simulate_args_file).parent), env=simif.get_env(), ), ] @@ -1012,10 +1067,10 @@ def test_simulate_gui( "-ncerror EVBSTR", "-ncerror EVBNAT", "-work work", - '-nclibdirname "%s"' % join(self.output_path, "libraries"), - '-cdslib "%s"' % join(self.output_path, "cds.lib"), + '-nclibdirname "%s"' % str(Path(self.output_path) / "libraries"), + '-cdslib "%s"' % str(Path(self.output_path) / "cds.lib"), '-log "%s"' - % join("suite_output_path", simif.name, "irun_elaborate.log"), + % str(Path("suite_output_path") / simif.name / "irun_elaborate.log"), "-quiet", '-reflib "lib_path"', "-access +rwc", @@ -1037,10 +1092,10 @@ def test_simulate_gui( "-ncerror EVBSTR", "-ncerror EVBNAT", "-work work", - '-nclibdirname "%s"' % join(self.output_path, "libraries"), - '-cdslib "%s"' % join(self.output_path, "cds.lib"), + '-nclibdirname "%s"' % str(Path(self.output_path) / "libraries"), + '-cdslib "%s"' % str(Path(self.output_path) / "cds.lib"), '-log "%s"' - % join("suite_output_path", simif.name, "irun_simulate.log"), + % str(Path("suite_output_path") / simif.name / "irun_simulate.log"), "-quiet", '-reflib "lib_path"', "-access +rwc", @@ -1050,7 +1105,7 @@ def test_simulate_gui( ) def setUp(self): - self.output_path = join(dirname(__file__), "test_incisive_out") + self.output_path = str(Path(__file__).parent / "test_incisive_out") renew_path(self.output_path) self.project = Project() self.cwd = os.getcwd() @@ -1058,7 +1113,7 @@ def setUp(self): def tearDown(self): os.chdir(self.cwd) - if exists(self.output_path): + if Path(self.output_path).exists(): rmtree(self.output_path) diff --git a/tests/unit/test_modelsim_interface.py b/tests/unit/test_modelsim_interface.py index f01e3ef7f..b30c005ab 100644 --- a/tests/unit/test_modelsim_interface.py +++ b/tests/unit/test_modelsim_interface.py @@ -10,7 +10,7 @@ import unittest -from os.path import join, dirname, exists +from pathlib import Path import os from shutil import rmtree from unittest import mock @@ -39,13 +39,13 @@ def test_compile_project_vhdl_2008(self, process, check_output): "file.vhd", "lib", file_type="vhdl", vhdl_standard=VHDL.standard("2008") ) simif.compile_project(project) - process_args = [join(self.prefix_path, "vlib"), "-unix", "lib_path"] + process_args = [str(Path(self.prefix_path) / "vlib"), "-unix", "lib_path"] process.assert_called_once_with(process_args, env=simif.get_env()) check_args = [ - join(self.prefix_path, "vcom"), + str(Path(self.prefix_path) / "vcom"), "-quiet", "-modelsimini", - join(self.output_path, "modelsim.ini"), + str(Path(self.output_path) / "modelsim.ini"), "-2008", "-work", "lib", @@ -66,13 +66,13 @@ def test_compile_project_vhdl_2002(self, process, check_output): "file.vhd", "lib", file_type="vhdl", vhdl_standard=VHDL.standard("2002") ) simif.compile_project(project) - process_args = [join(self.prefix_path, "vlib"), "-unix", "lib_path"] + process_args = [str(Path(self.prefix_path) / "vlib"), "-unix", "lib_path"] process.assert_called_once_with(process_args, env=simif.get_env()) check_args = [ - join(self.prefix_path, "vcom"), + str(Path(self.prefix_path) / "vcom"), "-quiet", "-modelsimini", - join(self.output_path, "modelsim.ini"), + str(Path(self.output_path) / "modelsim.ini"), "-2002", "-work", "lib", @@ -93,13 +93,13 @@ def test_compile_project_vhdl_93(self, process, check_output): "file.vhd", "lib", file_type="vhdl", vhdl_standard=VHDL.standard("93") ) simif.compile_project(project) - process_args = [join(self.prefix_path, "vlib"), "-unix", "lib_path"] + process_args = [str(Path(self.prefix_path) / "vlib"), "-unix", "lib_path"] process.assert_called_once_with(process_args, env=simif.get_env()) check_args = [ - join(self.prefix_path, "vcom"), + str(Path(self.prefix_path) / "vcom"), "-quiet", "-modelsimini", - join(self.output_path, "modelsim.ini"), + str(Path(self.output_path) / "modelsim.ini"), "-93", "-work", "lib", @@ -119,13 +119,13 @@ def test_compile_project_vhdl_extra_flags(self, process, check_output): source_file = project.add_source_file("file.vhd", "lib", file_type="vhdl") source_file.set_compile_option("modelsim.vcom_flags", ["custom", "flags"]) simif.compile_project(project) - process_args = [join(self.prefix_path, "vlib"), "-unix", "lib_path"] + process_args = [str(Path(self.prefix_path) / "vlib"), "-unix", "lib_path"] process.assert_called_once_with(process_args, env=simif.get_env()) check_args = [ - join(self.prefix_path, "vcom"), + str(Path(self.prefix_path) / "vcom"), "-quiet", "-modelsimini", - join(self.output_path, "modelsim.ini"), + str(Path(self.output_path) / "modelsim.ini"), "custom", "flags", "-2008", @@ -146,13 +146,13 @@ def test_compile_project_verilog(self, process, check_output): write_file("file.v", "") project.add_source_file("file.v", "lib", file_type="verilog") simif.compile_project(project) - process_args = [join(self.prefix_path, "vlib"), "-unix", "lib_path"] + process_args = [str(Path(self.prefix_path) / "vlib"), "-unix", "lib_path"] process.assert_called_once_with(process_args, env=simif.get_env()) check_args = [ - join(self.prefix_path, "vlog"), + str(Path(self.prefix_path) / "vlog"), "-quiet", "-modelsimini", - join(self.output_path, "modelsim.ini"), + str(Path(self.output_path) / "modelsim.ini"), "-work", "lib", "file.v", @@ -172,13 +172,13 @@ def test_compile_project_system_verilog(self, process, check_output): write_file("file.sv", "") project.add_source_file("file.sv", "lib", file_type="systemverilog") simif.compile_project(project) - process_args = [join(self.prefix_path, "vlib"), "-unix", "lib_path"] + process_args = [str(Path(self.prefix_path) / "vlib"), "-unix", "lib_path"] process.assert_called_once_with(process_args, env=simif.get_env()) check_args = [ - join(self.prefix_path, "vlog"), + str(Path(self.prefix_path) / "vlog"), "-quiet", "-modelsimini", - join(self.output_path, "modelsim.ini"), + str(Path(self.output_path) / "modelsim.ini"), "-sv", "-work", "lib", @@ -200,13 +200,13 @@ def test_compile_project_verilog_extra_flags(self, process, check_output): source_file = project.add_source_file("file.v", "lib", file_type="verilog") source_file.set_compile_option("modelsim.vlog_flags", ["custom", "flags"]) simif.compile_project(project) - process_args = [join(self.prefix_path, "vlib"), "-unix", "lib_path"] + process_args = [str(Path(self.prefix_path) / "vlib"), "-unix", "lib_path"] process.assert_called_once_with(process_args, env=simif.get_env()) check_args = [ - join(self.prefix_path, "vlog"), + str(Path(self.prefix_path) / "vlog"), "-quiet", "-modelsimini", - join(self.output_path, "modelsim.ini"), + str(Path(self.output_path) / "modelsim.ini"), "custom", "flags", "-work", @@ -230,13 +230,13 @@ def test_compile_project_verilog_include(self, process, check_output): "file.v", "lib", file_type="verilog", include_dirs=["include"] ) simif.compile_project(project) - process_args = [join(self.prefix_path, "vlib"), "-unix", "lib_path"] + process_args = [str(Path(self.prefix_path) / "vlib"), "-unix", "lib_path"] process.assert_called_once_with(process_args, env=simif.get_env()) check_args = [ - join(self.prefix_path, "vlog"), + str(Path(self.prefix_path) / "vlog"), "-quiet", "-modelsimini", - join(self.output_path, "modelsim.ini"), + str(Path(self.output_path) / "modelsim.ini"), "-work", "lib", "file.v", @@ -259,13 +259,13 @@ def test_compile_project_verilog_define(self, process, check_output): "file.v", "lib", file_type="verilog", defines={"defname": "defval"} ) simif.compile_project(project) - process_args = [join(self.prefix_path, "vlib"), "-unix", "lib_path"] + process_args = [str(Path(self.prefix_path) / "vlib"), "-unix", "lib_path"] process.assert_called_once_with(process_args, env=simif.get_env()) process_args = [ - join(self.prefix_path, "vlog"), + str(Path(self.prefix_path) / "vlog"), "-quiet", "-modelsimini", - join(self.output_path, "modelsim.ini"), + str(Path(self.output_path) / "modelsim.ini"), "-work", "lib", "file.v", @@ -275,10 +275,15 @@ def test_compile_project_verilog_define(self, process, check_output): ] check_output.assert_called_once_with(process_args, env=simif.get_env()) + def _get_inis(self): + return ( + str(Path(self.output_path) / "modelsim.ini"), + str(Path(self.prefix_path) / ".." / "modelsim.ini"), + str(Path(self.test_path) / "my_modelsim.ini"), + ) + def test_copies_modelsim_ini_file_from_install(self): - modelsim_ini = join(self.output_path, "modelsim.ini") - installed_modelsim_ini = join(self.prefix_path, "..", "modelsim.ini") - user_modelsim_ini = join(self.test_path, "my_modelsim.ini") + (modelsim_ini, installed_modelsim_ini, user_modelsim_ini) = self._get_inis() with open(installed_modelsim_ini, "w") as fptr: fptr.write("installed") @@ -293,9 +298,7 @@ def test_copies_modelsim_ini_file_from_install(self): self.assertEqual(fptr.read(), "installed") def test_copies_modelsim_ini_file_from_user(self): - modelsim_ini = join(self.output_path, "modelsim.ini") - installed_modelsim_ini = join(self.prefix_path, "..", "modelsim.ini") - user_modelsim_ini = join(self.test_path, "my_modelsim.ini") + (modelsim_ini, installed_modelsim_ini, user_modelsim_ini) = self._get_inis() with open(installed_modelsim_ini, "w") as fptr: fptr.write("installed") @@ -312,9 +315,7 @@ def test_copies_modelsim_ini_file_from_user(self): self.assertEqual(fptr.read(), "user") def test_overwrites_modelsim_ini_file_from_install(self): - modelsim_ini = join(self.output_path, "modelsim.ini") - installed_modelsim_ini = join(self.prefix_path, "..", "modelsim.ini") - user_modelsim_ini = join(self.test_path, "my_modelsim.ini") + (modelsim_ini, installed_modelsim_ini, user_modelsim_ini) = self._get_inis() with open(modelsim_ini, "w") as fptr: fptr.write("existing") @@ -332,9 +333,7 @@ def test_overwrites_modelsim_ini_file_from_install(self): self.assertEqual(fptr.read(), "installed") def test_overwrites_modelsim_ini_file_from_user(self): - modelsim_ini = join(self.output_path, "modelsim.ini") - installed_modelsim_ini = join(self.prefix_path, "..", "modelsim.ini") - user_modelsim_ini = join(self.test_path, "my_modelsim.ini") + (modelsim_ini, installed_modelsim_ini, user_modelsim_ini) = self._get_inis() with open(modelsim_ini, "w") as fptr: fptr.write("existing") @@ -354,13 +353,14 @@ def test_overwrites_modelsim_ini_file_from_user(self): self.assertEqual(fptr.read(), "user") def setUp(self): - self.test_path = join(dirname(__file__), "test_modelsim_out") - self.output_path = join(self.test_path, "modelsim") - self.prefix_path = join(self.test_path, "prefix", "bin") + self.test_path = str(Path(__file__).parent / "test_modelsim_out") + + self.output_path = str(Path(self.test_path) / "modelsim") + self.prefix_path = str(Path(self.test_path) / "prefix" / "bin") renew_path(self.test_path) renew_path(self.output_path) renew_path(self.prefix_path) - installed_modelsim_ini = join(self.prefix_path, "..", "modelsim.ini") + installed_modelsim_ini = str(Path(self.prefix_path) / ".." / "modelsim.ini") write_file(installed_modelsim_ini, "[Library]") self.project = Project() self.cwd = os.getcwd() @@ -368,5 +368,5 @@ def setUp(self): def tearDown(self): os.chdir(self.cwd) - if exists(self.test_path): + if Path(self.test_path).exists(): rmtree(self.test_path) diff --git a/tests/unit/test_ostools.py b/tests/unit/test_ostools.py index 6b6fb76da..834a4085a 100644 --- a/tests/unit/test_ostools.py +++ b/tests/unit/test_ostools.py @@ -10,8 +10,8 @@ from unittest import TestCase +from pathlib import Path from shutil import rmtree -from os.path import exists, dirname, join, abspath import sys from vunit.ostools import Process, renew_path @@ -22,11 +22,11 @@ class TestOSTools(TestCase): """ def setUp(self): - self.tmp_dir = join(dirname(__file__), "test_ostools_tmp") + self.tmp_dir = str(Path(__file__).parent / "test_ostools_tmp") renew_path(self.tmp_dir) def tearDown(self): - if exists(self.tmp_dir): + if Path(self.tmp_dir).exists(): rmtree(self.tmp_dir) def make_file(self, file_name, contents): @@ -34,7 +34,7 @@ def make_file(self, file_name, contents): Create a file in the temporary directory with contents Returns the absolute path to the file. """ - full_file_name = abspath(join(self.tmp_dir, file_name)) + full_file_name = str((Path(self.tmp_dir) / file_name).resolve()) with open(full_file_name, "w") as outfile: outfile.write(contents) return full_file_name @@ -101,7 +101,7 @@ def test_output_is_parallel(self): self.assertEqual(message, "message") def test_non_utf8_in_output(self): - python_script = join(dirname(__file__), "non_utf8_printer.py") + python_script = str(Path(__file__).parent / "non_utf8_printer.py") output = [] process = Process([sys.executable, python_script]) process.consume_output(output.append) diff --git a/tests/unit/test_project.py b/tests/unit/test_project.py index 7fcfc30c8..3f4691bb8 100644 --- a/tests/unit/test_project.py +++ b/tests/unit/test_project.py @@ -12,9 +12,9 @@ import unittest -from shutil import rmtree -from os.path import join, exists, dirname +from pathlib import Path import os +from shutil import rmtree from time import sleep import itertools from unittest import mock @@ -30,7 +30,7 @@ class TestProject(unittest.TestCase): # pylint: disable=too-many-public-methods """ def setUp(self): - self.output_path = join(dirname(__file__), "test_project_out") + self.output_path = str(Path(__file__).parent / "test_project_out") renew_path(self.output_path) self.project = Project() self.cwd = os.getcwd() @@ -38,7 +38,7 @@ def setUp(self): def tearDown(self): os.chdir(self.cwd) - if exists(self.output_path): + if Path(self.output_path).exists(): rmtree(self.output_path) def test_parses_entity_architecture(self): @@ -196,7 +196,7 @@ def test_multiple_identical_file_names_with_different_path_in_same_library(self) self.project.add_library("lib", "lib_path") a_foo = self.add_source_file( "lib", - join("a", "foo.vhd"), + str(Path("a") / "foo.vhd"), """ entity a_foo is end entity; @@ -205,7 +205,7 @@ def test_multiple_identical_file_names_with_different_path_in_same_library(self) b_foo = self.add_source_file( "lib", - join("b", "foo.vhd"), + str(Path("b") / "foo.vhd"), """ entity b_foo is end entity; @@ -891,7 +891,7 @@ def test_updating_creates_hash_files(self): for source_file in files: self.update(source_file) - self.assertTrue(exists(self.hash_file_name_of(source_file))) + self.assertTrue(Path(self.hash_file_name_of(source_file)).exists()) def test_should_not_recompile_updated_files(self): file1, file2, file3 = self.create_dummy_three_file_project() diff --git a/tests/unit/test_rivierapro_interface.py b/tests/unit/test_rivierapro_interface.py index 2e8cd846d..d0a42eaae 100644 --- a/tests/unit/test_rivierapro_interface.py +++ b/tests/unit/test_rivierapro_interface.py @@ -10,7 +10,7 @@ import unittest -from os.path import join, dirname, exists +from pathlib import Path import os from shutil import rmtree from unittest import mock @@ -37,18 +37,18 @@ def test_compile_project_vhdl_2019(self, process, check_output): ) simif.compile_project(project) process.assert_any_call( - [join("prefix", "vlib"), "lib", "lib_path"], + [str(Path("prefix") / "vlib"), "lib", "lib_path"], cwd=self.output_path, env=simif.get_env(), ) process.assert_called_with( - [join("prefix", "vmap"), "lib", "lib_path"], + [str(Path("prefix") / "vmap"), "lib", "lib_path"], cwd=self.output_path, env=simif.get_env(), ) check_output.assert_called_once_with( [ - join("prefix", "vcom"), + str(Path("prefix") / "vcom"), "-quiet", "-j", self.output_path, @@ -72,18 +72,18 @@ def test_compile_project_vhdl_2008(self, process, check_output): ) simif.compile_project(project) process.assert_any_call( - [join("prefix", "vlib"), "lib", "lib_path"], + [str(Path("prefix") / "vlib"), "lib", "lib_path"], cwd=self.output_path, env=simif.get_env(), ) process.assert_called_with( - [join("prefix", "vmap"), "lib", "lib_path"], + [str(Path("prefix") / "vmap"), "lib", "lib_path"], cwd=self.output_path, env=simif.get_env(), ) check_output.assert_called_once_with( [ - join("prefix", "vcom"), + str(Path("prefix") / "vcom"), "-quiet", "-j", self.output_path, @@ -107,18 +107,18 @@ def test_compile_project_vhdl_2002(self, process, check_output): ) simif.compile_project(project) process.assert_any_call( - [join("prefix", "vlib"), "lib", "lib_path"], + [str(Path("prefix") / "vlib"), "lib", "lib_path"], cwd=self.output_path, env=simif.get_env(), ) process.assert_called_with( - [join("prefix", "vmap"), "lib", "lib_path"], + [str(Path("prefix") / "vmap"), "lib", "lib_path"], cwd=self.output_path, env=simif.get_env(), ) check_output.assert_called_once_with( [ - join("prefix", "vcom"), + str(Path("prefix") / "vcom"), "-quiet", "-j", self.output_path, @@ -142,18 +142,18 @@ def test_compile_project_vhdl_93(self, process, check_output): ) simif.compile_project(project) process.assert_any_call( - [join("prefix", "vlib"), "lib", "lib_path"], + [str(Path("prefix") / "vlib"), "lib", "lib_path"], cwd=self.output_path, env=simif.get_env(), ) process.assert_called_with( - [join("prefix", "vmap"), "lib", "lib_path"], + [str(Path("prefix") / "vmap"), "lib", "lib_path"], cwd=self.output_path, env=simif.get_env(), ) check_output.assert_called_once_with( [ - join("prefix", "vcom"), + str(Path("prefix") / "vcom"), "-quiet", "-j", self.output_path, @@ -176,18 +176,18 @@ def test_compile_project_vhdl_extra_flags(self, process, check_output): source_file.set_compile_option("rivierapro.vcom_flags", ["custom", "flags"]) simif.compile_project(project) process.assert_any_call( - [join("prefix", "vlib"), "lib", "lib_path"], + [str(Path("prefix") / "vlib"), "lib", "lib_path"], cwd=self.output_path, env=simif.get_env(), ) process.assert_called_with( - [join("prefix", "vmap"), "lib", "lib_path"], + [str(Path("prefix") / "vmap"), "lib", "lib_path"], cwd=self.output_path, env=simif.get_env(), ) check_output.assert_called_once_with( [ - join("prefix", "vcom"), + str(Path("prefix") / "vcom"), "-quiet", "-j", self.output_path, @@ -204,7 +204,7 @@ def test_compile_project_vhdl_extra_flags(self, process, check_output): @mock.patch("vunit.sim_if.check_output", autospec=True, return_value="") @mock.patch("vunit.sim_if.rivierapro.Process", autospec=True) def test_compile_project_verilog(self, process, check_output): - library_cfg = join(self.output_path, "library.cfg") + library_cfg = str(Path(self.output_path) / "library.cfg") simif = RivieraProInterface(prefix="prefix", output_path=self.output_path) project = Project() project.add_library("lib", "lib_path") @@ -212,18 +212,18 @@ def test_compile_project_verilog(self, process, check_output): project.add_source_file("file.v", "lib", file_type="verilog") simif.compile_project(project) process.assert_any_call( - [join("prefix", "vlib"), "lib", "lib_path"], + [str(Path("prefix") / "vlib"), "lib", "lib_path"], cwd=self.output_path, env=simif.get_env(), ) process.assert_called_with( - [join("prefix", "vmap"), "lib", "lib_path"], + [str(Path("prefix") / "vmap"), "lib", "lib_path"], cwd=self.output_path, env=simif.get_env(), ) check_output.assert_called_once_with( [ - join("prefix", "vlog"), + str(Path("prefix") / "vlog"), "-quiet", "-lc", library_cfg, @@ -239,7 +239,7 @@ def test_compile_project_verilog(self, process, check_output): @mock.patch("vunit.sim_if.check_output", autospec=True, return_value="") @mock.patch("vunit.sim_if.rivierapro.Process", autospec=True) def test_compile_project_system_verilog(self, process, check_output): - library_cfg = join(self.output_path, "library.cfg") + library_cfg = str(Path(self.output_path) / "library.cfg") simif = RivieraProInterface(prefix="prefix", output_path=self.output_path) project = Project() project.add_library("lib", "lib_path") @@ -247,18 +247,18 @@ def test_compile_project_system_verilog(self, process, check_output): project.add_source_file("file.sv", "lib", file_type="systemverilog") simif.compile_project(project) process.assert_any_call( - [join("prefix", "vlib"), "lib", "lib_path"], + [str(Path("prefix") / "vlib"), "lib", "lib_path"], cwd=self.output_path, env=simif.get_env(), ) process.assert_called_with( - [join("prefix", "vmap"), "lib", "lib_path"], + [str(Path("prefix") / "vmap"), "lib", "lib_path"], cwd=self.output_path, env=simif.get_env(), ) check_output.assert_called_once_with( [ - join("prefix", "vlog"), + str(Path("prefix") / "vlog"), "-quiet", "-lc", library_cfg, @@ -275,7 +275,7 @@ def test_compile_project_system_verilog(self, process, check_output): @mock.patch("vunit.sim_if.check_output", autospec=True, return_value="") @mock.patch("vunit.sim_if.rivierapro.Process", autospec=True) def test_compile_project_verilog_extra_flags(self, process, check_output): - library_cfg = join(self.output_path, "library.cfg") + library_cfg = str(Path(self.output_path) / "library.cfg") simif = RivieraProInterface(prefix="prefix", output_path=self.output_path) project = Project() project.add_library("lib", "lib_path") @@ -284,18 +284,18 @@ def test_compile_project_verilog_extra_flags(self, process, check_output): source_file.set_compile_option("rivierapro.vlog_flags", ["custom", "flags"]) simif.compile_project(project) process.assert_any_call( - [join("prefix", "vlib"), "lib", "lib_path"], + [str(Path("prefix") / "vlib"), "lib", "lib_path"], cwd=self.output_path, env=simif.get_env(), ) process.assert_called_with( - [join("prefix", "vmap"), "lib", "lib_path"], + [str(Path("prefix") / "vmap"), "lib", "lib_path"], cwd=self.output_path, env=simif.get_env(), ) check_output.assert_called_once_with( [ - join("prefix", "vlog"), + str(Path("prefix") / "vlog"), "-quiet", "-lc", library_cfg, @@ -313,7 +313,7 @@ def test_compile_project_verilog_extra_flags(self, process, check_output): @mock.patch("vunit.sim_if.check_output", autospec=True, return_value="") @mock.patch("vunit.sim_if.rivierapro.Process", autospec=True) def test_compile_project_verilog_include(self, process, check_output): - library_cfg = join(self.output_path, "library.cfg") + library_cfg = str(Path(self.output_path) / "library.cfg") simif = RivieraProInterface(prefix="prefix", output_path=self.output_path) project = Project() project.add_library("lib", "lib_path") @@ -323,16 +323,18 @@ def test_compile_project_verilog_include(self, process, check_output): ) simif.compile_project(project) process.assert_any_call( - [join("prefix", "vlib"), "lib", "lib_path"], cwd=self.output_path, env=None + [str(Path("prefix") / "vlib"), "lib", "lib_path"], + cwd=self.output_path, + env=None, ) process.assert_called_with( - [join("prefix", "vmap"), "lib", "lib_path"], + [str(Path("prefix") / "vmap"), "lib", "lib_path"], cwd=self.output_path, env=simif.get_env(), ) check_output.assert_called_once_with( [ - join("prefix", "vlog"), + str(Path("prefix") / "vlog"), "-quiet", "-lc", library_cfg, @@ -349,7 +351,7 @@ def test_compile_project_verilog_include(self, process, check_output): @mock.patch("vunit.sim_if.check_output", autospec=True, return_value="") @mock.patch("vunit.sim_if.rivierapro.Process", autospec=True) def test_compile_project_verilog_define(self, process, check_output): - library_cfg = join(self.output_path, "library.cfg") + library_cfg = str(Path(self.output_path) / "library.cfg") simif = RivieraProInterface(prefix="prefix", output_path=self.output_path) project = Project() project.add_library("lib", "lib_path") @@ -359,18 +361,18 @@ def test_compile_project_verilog_define(self, process, check_output): ) simif.compile_project(project) process.assert_any_call( - [join("prefix", "vlib"), "lib", "lib_path"], + [str(Path("prefix") / "vlib"), "lib", "lib_path"], cwd=self.output_path, env=simif.get_env(), ) process.assert_called_with( - [join("prefix", "vmap"), "lib", "lib_path"], + [str(Path("prefix") / "vmap"), "lib", "lib_path"], cwd=self.output_path, env=simif.get_env(), ) check_output.assert_called_once_with( [ - join("prefix", "vlog"), + str(Path("prefix") / "vlog"), "-quiet", "-lc", library_cfg, @@ -385,7 +387,7 @@ def test_compile_project_verilog_define(self, process, check_output): ) def setUp(self): - self.output_path = join(dirname(__file__), "test_rivierapro_out") + self.output_path = str(Path(__file__).parent / "test_rivierapro_out") renew_path(self.output_path) self.project = Project() self.cwd = os.getcwd() @@ -393,5 +395,5 @@ def setUp(self): def tearDown(self): os.chdir(self.cwd) - if exists(self.output_path): + if Path(self.output_path).exists(): rmtree(self.output_path) diff --git a/tests/unit/test_simulator_interface.py b/tests/unit/test_simulator_interface.py index 936f7a1b6..7e6e76b66 100644 --- a/tests/unit/test_simulator_interface.py +++ b/tests/unit/test_simulator_interface.py @@ -9,8 +9,8 @@ """ import unittest -from os.path import join, dirname, exists -import os +from pathlib import Path +from os import chdir, getcwd import subprocess from shutil import rmtree from unittest import mock @@ -248,15 +248,15 @@ def find_prefix_from_path(cls): environ.get.assert_called_once_with("VUNIT_SIMNAME_PATH", None) def setUp(self): - self.output_path = join(dirname(__file__), "test_simulator_interface__out") + self.output_path = str(Path(__file__).parent / "test_simulator_interface__out") renew_path(self.output_path) self.project = Project() - self.cwd = os.getcwd() - os.chdir(self.output_path) + self.cwd = getcwd() + chdir(self.output_path) def tearDown(self): - os.chdir(self.cwd) - if exists(self.output_path): + chdir(self.cwd) + if Path(self.output_path).exists(): rmtree(self.output_path) diff --git a/tests/unit/test_test_bench.py b/tests/unit/test_test_bench.py index 8ca79360e..a6cfa6112 100644 --- a/tests/unit/test_test_bench.py +++ b/tests/unit/test_test_bench.py @@ -12,8 +12,7 @@ import unittest -from os.path import join - +from pathlib import Path from unittest import mock from tests.common import with_tempdir, get_vhdl_test_bench from vunit.test.bench import ( @@ -40,7 +39,7 @@ class TestTestBench(unittest.TestCase): @with_tempdir def test_that_single_vhdl_test_is_created(self, tempdir): - design_unit = Entity("tb_entity", file_name=join(tempdir, "file.vhd")) + design_unit = Entity("tb_entity", file_name=str(Path(tempdir) / "file.vhd")) test_bench = TestBench(design_unit) tests = self.create_tests(test_bench) self.assert_has_tests(tests, ["lib.tb_entity.all"]) @@ -49,14 +48,14 @@ def test_that_single_vhdl_test_is_created(self, tempdir): @with_tempdir def test_no_architecture_at_creation(tempdir): design_unit = Entity( - "tb_entity", file_name=join(tempdir, "file.vhd"), no_arch=True + "tb_entity", file_name=str(Path(tempdir) / "file.vhd"), no_arch=True ) TestBench(design_unit) @with_tempdir def test_no_architecture_gives_runtime_error(self, tempdir): design_unit = Entity( - "tb_entity", file_name=join(tempdir, "file.vhd"), no_arch=True + "tb_entity", file_name=str(Path(tempdir) / "file.vhd"), no_arch=True ) test_bench = TestBench(design_unit) try: @@ -68,14 +67,14 @@ def test_no_architecture_gives_runtime_error(self, tempdir): @with_tempdir def test_that_single_verilog_test_is_created(self, tempdir): - design_unit = Module("tb_module", file_name=join(tempdir, "file.v")) + design_unit = Module("tb_module", file_name=str(Path(tempdir) / "file.v")) test_bench = TestBench(design_unit) tests = self.create_tests(test_bench) self.assert_has_tests(tests, ["lib.tb_module.all"]) @with_tempdir def test_create_default_test(self, tempdir): - design_unit = Entity("tb_entity", file_name=join(tempdir, "file.vhd")) + design_unit = Entity("tb_entity", file_name=str(Path(tempdir) / "file.vhd")) design_unit.generic_names = ["runner_cfg"] test_bench = TestBench(design_unit) tests = self.create_tests(test_bench) @@ -83,9 +82,11 @@ def test_create_default_test(self, tempdir): @with_tempdir def test_multiple_architectures_are_not_allowed_for_test_bench(self, tempdir): - design_unit = Entity("tb_entity", file_name=join(tempdir, "file.vhd")) + design_unit = Entity("tb_entity", file_name=str(Path(tempdir) / "file.vhd")) design_unit.generic_names = ["runner_cfg"] - design_unit.add_architecture("arch2", file_name=join(tempdir, "arch2.vhd")) + design_unit.add_architecture( + "arch2", file_name=str(Path(tempdir) / "arch2.vhd") + ) try: TestBench(design_unit) except RuntimeError as exc: @@ -101,7 +102,7 @@ def test_multiple_architectures_are_not_allowed_for_test_bench(self, tempdir): def test_creates_tests_vhdl(self, tempdir): design_unit = Entity( "tb_entity", - file_name=join(tempdir, "file.vhd"), + file_name=str(Path(tempdir) / "file.vhd"), contents="""\ if run("Test 1") --if run("Test 2") @@ -135,7 +136,7 @@ def test_creates_tests_vhdl(self, tempdir): def test_creates_tests_verilog(self, tempdir): design_unit = Module( "tb_module", - file_name=join(tempdir, "file.v"), + file_name=str(Path(tempdir) / "file.v"), contents="""\ `TEST_CASE("Test 1") `TEST_CASE ("Test 2") @@ -168,7 +169,9 @@ def test_creates_tests_verilog(self, tempdir): @with_tempdir def test_keyerror_on_non_existent_test(self, tempdir): design_unit = Entity( - "tb_entity", file_name=join(tempdir, "file.vhd"), contents='if run("Test")' + "tb_entity", + file_name=str(Path(tempdir) / "file.vhd"), + contents='if run("Test")', ) design_unit.generic_names = ["runner_cfg", "name"] test_bench = TestBench(design_unit) @@ -177,14 +180,14 @@ def test_keyerror_on_non_existent_test(self, tempdir): @with_tempdir def test_creates_tests_when_adding_architecture_late(self, tempdir): design_unit = Entity( - "tb_entity", file_name=join(tempdir, "file.vhd"), no_arch=True + "tb_entity", file_name=str(Path(tempdir) / "file.vhd"), no_arch=True ) design_unit.generic_names = ["runner_cfg"] test_bench = TestBench(design_unit) design_unit.add_architecture( "arch", - file_name=join(tempdir, "arch.vhd"), + file_name=str(Path(tempdir) / "file.vhd"), contents="""\ if run("Test_1") --if run("Test_2") @@ -196,11 +199,11 @@ def test_creates_tests_when_adding_architecture_late(self, tempdir): @with_tempdir def test_scan_tests_from_file(self, tempdir): - design_unit = Entity("tb_entity", file_name=join(tempdir, "file.vhd")) + design_unit = Entity("tb_entity", file_name=str(Path(tempdir) / "file.vhd")) design_unit.generic_names = ["runner_cfg"] test_bench = TestBench(design_unit) - file_name = join(tempdir, "file.vhd") + file_name = str(Path(tempdir) / "file.vhd") write_file( file_name, """\ @@ -212,16 +215,15 @@ def test_scan_tests_from_file(self, tempdir): tests = self.create_tests(test_bench) self.assert_has_tests(tests, ["lib.tb_entity.Test_1", "lib.tb_entity.Test_2"]) - @with_tempdir - def test_scan_tests_from_file_location_unix(self, tempdir): - design_unit = Entity("tb_entity", file_name=join(tempdir, "file.vhd")) + def _test_scan_tests_from_file_location(self, tempdir, code): + fstr = str(Path(tempdir) / "file.vhd") + + design_unit = Entity("tb_entity", file_name=fstr) design_unit.generic_names = ["runner_cfg"] test_bench = TestBench(design_unit) - file_name = join(tempdir, "file.vhd") - code = 'foo \n bar \n if run("Test_1")' - write_file(file_name, code) - test_bench.scan_tests_from_file(file_name) + write_file(fstr, code) + test_bench.scan_tests_from_file(fstr) tests = self.create_tests(test_bench) test_info = tests[0].test_information location = test_info["lib.tb_entity.Test_1"].location @@ -229,24 +231,20 @@ def test_scan_tests_from_file_location_unix(self, tempdir): assert location.length == len("Test_1") @with_tempdir - def test_scan_tests_from_file_location_dos(self, tempdir): - design_unit = Entity("tb_entity", file_name=join(tempdir, "file.vhd")) - design_unit.generic_names = ["runner_cfg"] - test_bench = TestBench(design_unit) + def test_scan_tests_from_file_location_unix(self, tempdir): + self._test_scan_tests_from_file_location( + tempdir, 'foo \n bar \n if run("Test_1")' + ) - file_name = join(tempdir, "file.vhd") - code = 'foo \r\n bar \r\n if run("Test_1")' - write_file(file_name, code) - test_bench.scan_tests_from_file(file_name) - tests = self.create_tests(test_bench) - test_info = tests[0].test_information - location = test_info["lib.tb_entity.Test_1"].location - assert location.offset == code.find("Test_1") - assert location.length == len("Test_1") + @with_tempdir + def test_scan_tests_from_file_location_dos(self, tempdir): + self._test_scan_tests_from_file_location( + tempdir, 'foo \r\n bar \r\n if run("Test_1")' + ) @with_tempdir def test_scan_tests_from_missing_file(self, tempdir): - design_unit = Entity("tb_entity", file_name=join(tempdir, "file.vhd")) + design_unit = Entity("tb_entity", file_name=str(Path(tempdir) / "file.vhd")) design_unit.generic_names = ["runner_cfg"] test_bench = TestBench(design_unit) @@ -259,7 +257,7 @@ def test_scan_tests_from_missing_file(self, tempdir): @with_tempdir def test_does_not_add_all_suffix_with_named_configurations(self, tempdir): - design_unit = Entity("tb_entity", file_name=join(tempdir, "file.vhd")) + design_unit = Entity("tb_entity", file_name=str(Path(tempdir) / "file.vhd")) design_unit.generic_names = ["runner_cfg"] test_bench = TestBench(design_unit) @@ -274,7 +272,7 @@ def test_does_not_add_all_suffix_with_named_configurations(self, tempdir): def test_that_run_in_same_simulation_attribute_works(self, tempdir): design_unit = Entity( "tb_entity", - file_name=join(tempdir, "file.vhd"), + file_name=str(Path(tempdir) / "file.vhd"), contents="""\ -- vunit: run_all_in_same_sim if run("Test_1") @@ -291,7 +289,7 @@ def test_that_run_in_same_simulation_attribute_works(self, tempdir): @with_tempdir def test_add_config(self, tempdir): - design_unit = Entity("tb_entity", file_name=join(tempdir, "file.vhd")) + design_unit = Entity("tb_entity", file_name=str(Path(tempdir) / "file.vhd")) design_unit.generic_names = ["runner_cfg", "value", "global_value"] test_bench = TestBench(design_unit) @@ -331,7 +329,7 @@ def test_add_config(self, tempdir): def test_test_case_add_config(self, tempdir): design_unit = Entity( "tb_entity", - file_name=join(tempdir, "file.vhd"), + file_name=str(Path(tempdir) / "file.vhd"), contents=""" if run("test 1") if run("test 2") @@ -389,7 +387,7 @@ def test_runtime_error_on_configuration_of_individual_test_with_same_sim( ): design_unit = Entity( "tb_entity", - file_name=join(tempdir, "file.vhd"), + file_name=str(Path(tempdir) / "file.vhd"), contents="""\ -- vunit: run_all_in_same_sim if run("Test 1") @@ -407,7 +405,7 @@ def test_runtime_error_on_configuration_of_individual_test_with_same_sim( def test_run_all_in_same_sim_can_be_configured(self, tempdir): design_unit = Entity( "tb_entity", - file_name=join(tempdir, "file.vhd"), + file_name=str(Path(tempdir) / "file.vhd"), contents="""\ -- vunit: run_all_in_same_sim if run("Test 1") @@ -436,7 +434,7 @@ def test_run_all_in_same_sim_can_be_configured(self, tempdir): def test_global_user_attributes_not_supported_yet(self, tempdir): design_unit = Entity( "tb_entity", - file_name=join(tempdir, "file.vhd"), + file_name=str(Path(tempdir) / "file.vhd"), contents="""\ -- vunit: .attr0 if run("Test 1") @@ -451,7 +449,7 @@ def test_global_user_attributes_not_supported_yet(self, tempdir): self.assertEqual( str(exc), "File global attributes are not yet supported: .attr0 in %s line 1" - % join(tempdir, "file.vhd"), + % str(Path(tempdir) / "file.vhd"), ) else: assert False, "RuntimeError not raised" @@ -460,7 +458,7 @@ def test_global_user_attributes_not_supported_yet(self, tempdir): def test_error_on_global_attributes_on_tests(self, tempdir): design_unit = Entity( "tb_entity", - file_name=join(tempdir, "file.vhd"), + file_name=str(Path(tempdir) / "file.vhd"), contents="""\ if run("Test 1") -- vunit: run_all_in_same_sim @@ -475,14 +473,14 @@ def test_error_on_global_attributes_on_tests(self, tempdir): self.assertEqual( str(exc), "Attribute run_all_in_same_sim is global and cannot be associated with test Test 1: %s line 2" - % join(tempdir, "file.vhd"), + % str(Path(tempdir) / "file.vhd"), ) else: assert False, "RuntimeError not raised" @with_tempdir def test_test_information(self, tempdir): - file_name = join(tempdir, "file.vhd") + file_name = str(Path(tempdir) / "file.vhd") for same_sim in [True, False]: contents = get_vhdl_test_bench( @@ -521,7 +519,7 @@ def test_test_information(self, tempdir): @with_tempdir def test_fail_on_unknown_sim_option(self, tempdir): - design_unit = Entity("tb_entity", file_name=join(tempdir, "file.vhd")) + design_unit = Entity("tb_entity", file_name=str(Path(tempdir) / "file.vhd")) design_unit.generic_names = ["runner_cfg"] test_bench = TestBench(design_unit) self.assertRaises(ValueError, test_bench.set_sim_option, "unknown", "value") diff --git a/tests/unit/test_test_bench_list.py b/tests/unit/test_test_bench_list.py index d926ab36e..7cb920eae 100644 --- a/tests/unit/test_test_bench_list.py +++ b/tests/unit/test_test_bench_list.py @@ -11,7 +11,7 @@ """ import unittest -from os.path import join +from pathlib import Path from unittest import mock from tests.unit.test_test_bench import Entity, Module from tests.common import with_tempdir @@ -29,19 +29,21 @@ def test_get_test_benches_in_empty_library(self): @with_tempdir def test_tb_filter_requires_runner_cfg(self, tempdir): - design_unit = Entity("tb_entity", file_name=join(tempdir, "file.vhd")) + fname = str(Path(tempdir) / "file.vhd") + + design_unit = Entity("tb_entity", file_name=fname) design_unit.generic_names = ["runner_cfg"] self.assertTrue(tb_filter(design_unit)) - design_unit = Entity("tb_entity", file_name=join(tempdir, "file.vhd")) + design_unit = Entity("tb_entity", file_name=fname) design_unit.generic_names = [] self.assertFalse(tb_filter(design_unit)) - design_unit = Module("tb_module", file_name=join(tempdir, "file.vhd")) + design_unit = Module("tb_module", file_name=fname) design_unit.generic_names = ["runner_cfg"] self.assertTrue(tb_filter(design_unit)) - design_unit = Module("tb_module", file_name=join(tempdir, "file.vhd")) + design_unit = Module("tb_module", file_name=fname) design_unit.generic_names = [] self.assertFalse(tb_filter(design_unit)) @@ -51,7 +53,9 @@ def test_tb_filter_match_prefix_and_suffix_only(self, tempdir): Issue #263 """ with mock.patch("vunit.test.bench_list.LOGGER", autospec=True) as logger: - design_unit = Entity("mul_tbl_scale", file_name=join(tempdir, "file.vhd")) + design_unit = Entity( + "mul_tbl_scale", file_name=str(Path(tempdir) / "file.vhd") + ) self.assertFalse(tb_filter(design_unit)) self.assertFalse(logger.warning.called) @@ -59,7 +63,9 @@ def test_tb_filter_match_prefix_and_suffix_only(self, tempdir): def test_tb_filter_warning_on_missing_runner_cfg_when_matching_tb_pattern( self, tempdir ): - design_unit = Module("tb_module_not_ok", file_name=join(tempdir, "file.vhd")) + design_unit = Module( + "tb_module_not_ok", file_name=str(Path(tempdir) / "file.vhd") + ) design_unit.generic_names = [] with mock.patch("vunit.test.bench_list.LOGGER", autospec=True) as logger: @@ -82,7 +88,7 @@ def test_tb_filter_warning_on_missing_runner_cfg_when_matching_tb_pattern( @with_tempdir def test_tb_filter_warning_on_runner_cfg_but_not_matching_tb_pattern(self, tempdir): design_unit = Entity( - "entity_ok_but_warning", file_name=join(tempdir, "file.vhd") + "entity_ok_but_warning", file_name=str(Path(tempdir) / "file.vhd") ) design_unit.generic_names = ["runner_cfg"] diff --git a/tests/unit/test_test_report.py b/tests/unit/test_test_report.py index 71225e6e6..1e51f2f9b 100644 --- a/tests/unit/test_test_report.py +++ b/tests/unit/test_test_report.py @@ -10,7 +10,7 @@ from unittest import TestCase import os -from os.path import basename, dirname, join +from pathlib import Path from xml.etree import ElementTree from vunit.test.report import TestReport, PASSED, SKIPPED, FAILED from vunit.ui.common import TEST_OUTPUT_PATH @@ -26,7 +26,7 @@ def setUp(self): self.printer = StubPrinter() self.output_file_contents = 'Output file contents\n&13!--"<\\xml>' - self.output_file_name = join(dirname(__file__), "test_report_output.txt") + self.output_file_name = str(Path(__file__).parent / "test_report_output.txt") with open(self.output_file_name, "w") as fwrite: fwrite.write(self.output_file_contents) @@ -277,15 +277,15 @@ def test_junit_report_with_testcase_classname(self): ) def test_dict_report_with_all_passed_tests(self): - opath = dirname(dirname(self.output_file_name)) - test_path = join(opath, TEST_OUTPUT_PATH, "unit") - output_file_name = join(test_path, basename(self.output_file_name)) + opath = Path(self.output_file_name).parent.parent + test_path = opath / TEST_OUTPUT_PATH / "unit" + output_file_name = test_path / Path(self.output_file_name).name results = Results( opath, None, self._report_with_all_passed_tests(output_file_name) ) report = results.get_report() for _, test in report.tests.items(): - self.assertEqual(basename(test.path), test.relpath) + self.assertEqual(test.path.name, test.relpath) test0 = report.tests["passed_test0"] test1 = report.tests["passed_test1"] self.assertEqual( diff --git a/tests/unit/test_test_runner.py b/tests/unit/test_test_runner.py index 3f498d818..0b4c84a28 100644 --- a/tests/unit/test_test_runner.py +++ b/tests/unit/test_test_runner.py @@ -8,7 +8,7 @@ Test the test runner """ -from os.path import join, abspath +from pathlib import Path import unittest from unittest import mock from tests.common import with_tempdir @@ -143,8 +143,9 @@ def test_create_output_path_on_linux(self): test_output = create_output_path(output_path, test_name) self.assertEqual( test_output, - join( - abspath(output_path), test_name + "_" + hash_string(test_name) + str( + Path(output_path).resolve() + / (test_name + "_" + hash_string(test_name)) ), ) @@ -153,8 +154,9 @@ def test_create_output_path_on_linux(self): test_output = create_output_path(output_path, test_name) self.assertEqual( test_output, - join( - abspath(output_path), test_name + "_" + hash_string(test_name) + str( + Path(output_path).resolve() + / (test_name + "_" + hash_string(test_name)) ), ) @@ -164,8 +166,9 @@ def test_create_output_path_on_linux(self): test_output = create_output_path(output_path, test_name) self.assertEqual( test_output, - join( - abspath(output_path), safe_name + "_" + hash_string(test_name) + str( + Path(output_path).resolve() + / (safe_name + "_" + hash_string(test_name)) ), ) @@ -185,8 +188,9 @@ def test_create_output_path_on_windows(self): test_output = create_output_path(output_path, test_name) self.assertEqual( test_output, - join( - abspath(output_path), test_name + "_" + hash_string(test_name) + str( + Path(output_path).resolve() + / (test_name + "_" + hash_string(test_name)) ), ) @@ -195,7 +199,8 @@ def test_create_output_path_on_windows(self): test_name = "_" * 400 test_output = create_output_path(output_path, test_name) self.assertEqual( - test_output, join(abspath(output_path), hash_string(test_name)) + test_output, + str(Path(output_path).resolve() / hash_string(test_name)), ) @staticmethod diff --git a/tests/unit/test_test_suites.py b/tests/unit/test_test_suites.py index 40d4b386c..abee45e8e 100644 --- a/tests/unit/test_test_suites.py +++ b/tests/unit/test_test_suites.py @@ -8,7 +8,7 @@ Test the test suites """ -from os.path import join +from pathlib import Path from unittest import TestCase from tests.common import create_tempdir from vunit.test.suites import TestRun @@ -94,9 +94,9 @@ def _read_test_results(self, expected, contents): Helper method to test the read_test_results function """ with create_tempdir() as path: - file_name = join(path, "vunit_results") + file_name = Path(path) / "vunit_results" if contents is not None: - with open(file_name, "w") as fptr: + with file_name.open("w") as fptr: fptr.write(contents) run = TestRun( @@ -162,9 +162,9 @@ def _test_exit_code( Helper method to test the check_results function """ with create_tempdir() as path: - file_name = join(path, "vunit_results") + file_name = Path(path) / "vunit_results" if contents is not None: - with open(file_name, "w") as fptr: + with file_name.open("w") as fptr: fptr.write(contents) sim_if = SimulatorInterface diff --git a/tests/unit/test_ui.py b/tests/unit/test_ui.py index 1338a5868..56c657e21 100644 --- a/tests/unit/test_ui.py +++ b/tests/unit/test_ui.py @@ -13,8 +13,7 @@ import unittest from string import Template from pathlib import Path -import os -from os.path import join, dirname, basename, exists, abspath +from os import chdir, getcwd import json import re from re import MULTILINE @@ -35,17 +34,17 @@ class TestUi(unittest.TestCase): """ def setUp(self): - self.tmp_path = join(dirname(__file__), "test_ui_tmp") + self.tmp_path = str(Path(__file__).parent / "test_ui_tmp") renew_path(self.tmp_path) - self.cwd = os.getcwd() - os.chdir(self.tmp_path) + self.cwd = getcwd() + chdir(self.tmp_path) - self._output_path = join(self.tmp_path, "output") - self._preprocessed_path = join(self._output_path, "preprocessed") + self._output_path = str(Path(self.tmp_path) / "output") + self._preprocessed_path = str(Path(self._output_path) / "preprocessed") def tearDown(self): - os.chdir(self.cwd) - if exists(self.tmp_path): + chdir(self.cwd) + if Path(self.tmp_path).exists(): rmtree(self.tmp_path) def test_global_custom_preprocessors_should_be_applied_in_the_order_they_are_added( @@ -75,10 +74,10 @@ def test_global_custom_preprocessors_should_be_applied_in_the_order_they_are_add end architecture; """ ) - with open(join(self._preprocessed_path, "lib", basename(file_name))) as fread: + fname = Path(file_name).name + with (Path(self._preprocessed_path) / "lib" / fname).open() as fread: self.assertEqual( - fread.read(), - pp_source.substitute(entity="ent0", file=basename(file_name)), + fread.read(), pp_source.substitute(entity="ent0", file=fname), ) def test_global_check_and_location_preprocessors_should_be_applied_after_global_custom_preprocessors( @@ -90,8 +89,8 @@ def test_global_check_and_location_preprocessors_should_be_applied_after_global_ ui.enable_check_preprocessing() ui.add_preprocessor(TestPreprocessor()) - file_name = self.create_entity_file() - ui.add_source_files(file_name, "lib") + entity_file = Path(self.create_entity_file()) + ui.add_source_files(str(entity_file), "lib") pp_source = Template( """\ @@ -113,10 +112,10 @@ def test_global_check_and_location_preprocessors_should_be_applied_after_global_ end architecture; """ ) - with open(join(self._preprocessed_path, "lib", basename(file_name))) as fread: + with (Path(self._preprocessed_path) / "lib" / entity_file.name).open() as fread: self.assertEqual( fread.read(), - pp_source.substitute(entity="ent0", file=basename(file_name)), + pp_source.substitute(entity="ent0", file=entity_file.name), ) def test_locally_specified_preprocessors_should_be_used_instead_of_any_globally_defined_preprocessors( @@ -151,9 +150,11 @@ def test_locally_specified_preprocessors_should_be_used_instead_of_any_globally_ """ ) self.assertFalse( - exists(join(self._preprocessed_path, "lib", basename(file_name1))) + (Path(self._preprocessed_path) / "lib" / Path(file_name1).name).exists() ) - with open(join(self._preprocessed_path, "lib", basename(file_name2))) as fread: + with ( + Path(self._preprocessed_path) / "lib" / Path(file_name2).name + ).open() as fread: expectd = pp_source.substitute( entity="ent2", report='log("Here I am!"); -- VUnitfier preprocessor: Report turned off, keeping original code.', @@ -183,16 +184,17 @@ def test_recovers_from_preprocessing_error(self, logger): end architecture; """ ) - file_name = join(self.tmp_path, "ent1.vhd") + file_name = Path(self.tmp_path) / "ent1.vhd" contents = source_with_error.substitute(entity="ent1") - self.create_file(file_name, contents) + self.create_file(str(file_name), contents) ui.add_source_file(file_name, "lib") logger.assert_called_once_with( - "Failed to preprocess %s", Path(file_name).resolve() + "Failed to preprocess %s", str(Path(file_name).resolve()) + ) + self.assertFalse( + (Path(self._preprocessed_path) / "lib" / file_name.name).exists() ) - pp_file = join(self._preprocessed_path, "lib", basename(file_name)) - self.assertFalse(exists(pp_file)) def test_supported_source_file_suffixes(self): """Test adding a supported filetype, of any case, is accepted.""" @@ -221,23 +223,26 @@ def test_unsupported_source_file_suffixes(self): def test_exception_on_adding_zero_files(self): ui = self._create_ui() lib = ui.add_library("lib") + dname = Path(__file__).parent self.assertRaisesRegex( ValueError, "Pattern.*missing1.vhd.*", lib.add_source_files, - join(dirname(__file__), "missing1.vhd"), + str(dname / "missing1.vhd"), ) self.assertRaisesRegex( ValueError, "File.*missing2.vhd.*", lib.add_source_file, - join(dirname(__file__), "missing2.vhd"), + str(dname / "missing2.vhd"), ) def test_no_exception_on_adding_zero_files_when_allowed(self): ui = self._create_ui() lib = ui.add_library("lib") - lib.add_source_files(join(dirname(__file__), "missing.vhd"), allow_empty=True) + lib.add_source_files( + str(Path(__file__).parent / "missing.vhd"), allow_empty=True + ) def test_get_test_benchs_and_test(self): ui = self._create_ui() @@ -475,7 +480,7 @@ def test_filtering_tests(self, tempdir): def setup(ui): " Setup the project " lib = ui.add_library("lib") - file_name = join(tempdir, "tb_filter.vhd") + file_name = str(Path(tempdir) / "tb_filter.vhd") create_vhdl_test_bench_file( "tb_filter", file_name, @@ -554,17 +559,18 @@ def check_stdout(ui, expected): @with_tempdir def test_export_json(self, tempdir): - json_file = join(tempdir, "export.json") + tdir = Path(tempdir) + json_file = str(tdir / "export.json") ui = self._create_ui("--export-json", json_file) lib1 = ui.add_library("lib1") lib2 = ui.add_library("lib2") - file_name1 = join(tempdir, "tb_foo.vhd") + file_name1 = str(tdir / "tb_foo.vhd") create_vhdl_test_bench_file("tb_foo", file_name1) lib1.add_source_file(file_name1) - file_name2 = join(tempdir, "tb_bar.vhd") + file_name2 = str(tdir / "tb_bar.vhd") create_vhdl_test_bench_file( "tb_bar", file_name2, @@ -595,7 +601,12 @@ def test_export_json(self, tempdir): # Check the contents of the files section self.assertEqual( set((item["library_name"], item["file_name"]) for item in data["files"]), - set([("lib1", abspath(file_name1)), ("lib2", abspath(file_name2))]), + set( + [ + ("lib1", str(Path(file_name1).resolve())), + ("lib2", str(Path(file_name2).resolve())), + ] + ), ) # Check the contents of the tests section @@ -752,7 +763,7 @@ def check(action): lib = ui.add_library("lib") action(ui, lib) add_source_file.assert_called_once_with( - Path("verilog.v").resolve(), + str(Path("verilog.v").resolve()), "lib", file_type="verilog", include_dirs=all_include_dirs, @@ -788,7 +799,7 @@ def check(action): lib = ui.add_library("lib") action(ui, lib) add_source_file.assert_called_once_with( - Path("verilog.v").resolve(), + str(Path("verilog.v").resolve()), "lib", file_type="verilog", include_dirs=all_include_dirs, @@ -825,7 +836,7 @@ def test_add_source_files_has_no_parse(self): lib.add_source_file(file_name, no_parse=no_parse) add_source_file.assert_called_once_with( - Path("verilog.v").resolve(), + str(Path("verilog.v").resolve()), "lib", file_type="verilog", include_dirs=all_include_dirs, diff --git a/tests/unit/test_verilog_parser.py b/tests/unit/test_verilog_parser.py index c963bb6aa..de368c9da 100644 --- a/tests/unit/test_verilog_parser.py +++ b/tests/unit/test_verilog_parser.py @@ -10,7 +10,7 @@ from unittest import TestCase, mock import os -from os.path import join, dirname, exists +from pathlib import Path import time import shutil from vunit.ostools import renew_path @@ -23,7 +23,7 @@ class TestVerilogParser(TestCase): # pylint: disable=too-many-public-methods """ def setUp(self): - self.output_path = join(dirname(__file__), "test_verilog_parser_out") + self.output_path = str(Path(__file__).parent / "test_verilog_parser_out") renew_path(self.output_path) self.cwd = os.getcwd() os.chdir(self.output_path) @@ -327,10 +327,10 @@ def test_cached_parsing_updated_by_includes(self): def test_cached_parsing_updated_by_higher_priority_file(self): cache = {} - include_paths = [self.output_path, join(self.output_path, "lower_prio")] + include_paths = [self.output_path, str(Path(self.output_path) / "lower_prio")] self.write_file( - join("lower_prio", "include.svh"), + str(Path("lower_prio") / "include.svh"), """ module mod_lower_prio; endmodule; @@ -381,11 +381,11 @@ def write_file(self, file_name, contents): """ Write file with contents into output path """ - full_name = join(self.output_path, file_name) - full_path = dirname(full_name) - if not exists(full_path): - os.makedirs(full_path) - with open(full_name, "w") as fptr: + full_name = Path(self.output_path) / file_name + full_path = full_name.parent + if not full_path.exists(): + os.makedirs(str(full_path)) + with full_name.open("w") as fptr: fptr.write(contents) def parse(self, code, include_paths=None, cache=None, defines=None): diff --git a/tests/unit/test_verilog_preprocessor.py b/tests/unit/test_verilog_preprocessor.py index 81ee6cad4..0ba3caa16 100644 --- a/tests/unit/test_verilog_preprocessor.py +++ b/tests/unit/test_verilog_preprocessor.py @@ -12,7 +12,7 @@ Test of the Verilog preprocessor """ -from os.path import join, dirname, exists +from pathlib import Path import os from unittest import TestCase, mock import shutil @@ -28,7 +28,7 @@ class TestVerilogPreprocessor(TestCase): """ def setUp(self): - self.output_path = join(dirname(__file__), "test_verilog_preprocessor_out") + self.output_path = str(Path(__file__).parent / "test_verilog_preprocessor_out") renew_path(self.output_path) self.cwd = os.getcwd() os.chdir(self.output_path) @@ -150,7 +150,7 @@ def test_preprocess_include_directive(self): '`include "include.svh"', include_paths=[self.output_path] ) result.assert_has_tokens("hello hey") - result.assert_included_files([join(self.output_path, "include.svh")]) + result.assert_included_files([str(Path(self.output_path) / "include.svh")]) def test_detects_circular_includes(self): self.write_file("include1.svh", '`include "include2.svh"') @@ -267,7 +267,7 @@ def test_preprocess_include_directive_from_define(self): include_paths=[self.output_path], ) result.assert_has_tokens("hello hey") - result.assert_included_files([join(self.output_path, "include.svh")]) + result.assert_included_files([str(Path(self.output_path) / "include.svh")]) def test_preprocess_include_directive_from_define_with_args(self): self.write_file("include.svh", "hello hey") @@ -278,7 +278,7 @@ def test_preprocess_include_directive_from_define_with_args(self): include_paths=[self.output_path], ) result.assert_has_tokens("hello hey") - result.assert_included_files([join(self.output_path, "include.svh")]) + result.assert_included_files([str(Path(self.output_path) / "include.svh")]) def test_preprocess_macros_are_recursively_expanded(self): result = self.preprocess( @@ -674,7 +674,7 @@ def test_preprocess_error_in_include_file(self): '\n\n`include "include.svh"', include_paths=[self.output_path] ) result.assert_has_tokens("\n\n") - result.assert_included_files([join(self.output_path, "include.svh")]) + result.assert_included_files([str(Path(self.output_path) / "include.svh")]) result.logger.warning.assert_called_once_with( "Verilog `include bad argument\n%s", "from fn.v line 3:\n" @@ -863,11 +863,11 @@ def write_file(self, file_name, contents): """ Write file with contents into output path """ - full_name = join(self.output_path, file_name) - full_path = dirname(full_name) - if not exists(full_path): - os.makedirs(full_path) - with open(full_name, "w") as fptr: + full_name = Path(self.output_path) / file_name + full_path = full_name.parent + if not full_path.exists(): + os.makedirs(str(full_path)) + with full_name.open("w") as fptr: fptr.write(contents) diff --git a/tools/build_docs.py b/tools/build_docs.py index d0c5c87d2..1211b76ae 100644 --- a/tools/build_docs.py +++ b/tools/build_docs.py @@ -9,7 +9,7 @@ """ from subprocess import check_call -from os.path import join, dirname +from pathlib import Path import sys from sys import argv from create_release_notes import create_release_notes @@ -30,7 +30,7 @@ def main(): ] + ([] if len(argv) < 2 else argv[2:]) + [ "-TEWanb", "html", - join(dirname(__file__), "..", "docs"), + Path(__file__).parent.parent / "docs", argv[1], ] ) diff --git a/tools/create_release_notes.py b/tools/create_release_notes.py index 6404d0899..e4f35d8ab 100644 --- a/tools/create_release_notes.py +++ b/tools/create_release_notes.py @@ -8,21 +8,22 @@ Create monolithic release notes file from several input files """ -from os.path import join, dirname, basename, splitext, relpath +from pathlib import Path +from os.path import relpath from glob import glob from subprocess import check_output, CalledProcessError from shutil import which import datetime -def get_releases(source_path): +def get_releases(source_path: Path): """ Get all releases defined by release note files """ - release_notes = join(source_path, "release_notes") + release_notes = source_path / "release_notes" releases = [] for idx, file_name in enumerate( - sorted(glob(join(release_notes, "*.rst")), reverse=True) + sorted(glob(str(release_notes / "*.rst")), reverse=True) ): releases.append(Release(file_name, is_latest=idx == 0)) return releases @@ -32,7 +33,7 @@ def create_release_notes(): """ Create monolithic release notes file from several input files """ - source_path = join(dirname(__file__), "..", "docs") + source_path = Path(__file__).parent.parent / "docs" releases = get_releases(source_path) latest_release = releases[0] @@ -40,7 +41,7 @@ def create_release_notes(): def banner(fptr): fptr.write("\n" + ("-" * 80) + "\n\n") - with open(join(source_path, "release_notes.rst"), "w") as fptr: + with (source_path / "release_notes.rst").open("w") as fptr: fptr.write( """ .. _release_notes: @@ -96,7 +97,7 @@ class Release(object): def __init__(self, file_name, is_latest): self.file_name = file_name - self.name = splitext(basename(file_name))[0] + self.name = str(Path(file_name).with_suffix("").name) self.tag = "v" + self.name self.is_latest = is_latest diff --git a/tools/docs_utils.py b/tools/docs_utils.py index 621719d42..aa394fa87 100644 --- a/tools/docs_utils.py +++ b/tools/docs_utils.py @@ -10,25 +10,25 @@ import sys import inspect -from os.path import basename, dirname, isdir, isfile, join -from os import listdir, remove +from pathlib import Path +from os import listdir, remove -ROOT = join(dirname(__file__), "..", "docs") +ROOT = Path(__file__).parent.parent / "docs" def examples(): """ Traverses the examples directory and generates examples.rst with the docstrings """ - eg_path = join(ROOT, "..", "examples") - egs_fptr = open(join(ROOT, "examples.rst"), "w+") + eg_path = ROOT.parent / "examples" + egs_fptr = (ROOT / "examples.rst").open("w+") egs_fptr.write("\n".join([".. _examples:\n", "Examples", "========", "\n"])) for language, subdir in {"VHDL": "vhdl", "SystemVerilog": "verilog"}.items(): egs_fptr.write("\n".join([language, "~~~~~~~~~~~~~~~~~~~~~~~", "\n"])) - for item in listdir(join(eg_path, subdir)): - loc = join(eg_path, subdir, item) - if isdir(loc): + for item in listdir(str(eg_path / subdir)): + loc = eg_path / subdir / item + if loc.is_dir(): _data = _get_eg_doc( loc, "https://github.com/VUnit/vunit/tree/master/examples/%s/%s" @@ -38,37 +38,39 @@ def examples(): egs_fptr.write(_data) -def _get_eg_doc(location, ref): +def _get_eg_doc(location: Path, ref): """ Reads the docstring from a run.py file and rewrites the title to make it a ref """ - if not isfile(join(location, "run.py")): + nstr = str(location.name) + + if not (location / "run.py").is_file(): print( "WARNING: Example subdir '" - + basename(location) + + nstr + "' does not contain a 'run.py' file. Skipping..." ) return None - print("Generating '_main.py' from 'run.py' in '" + basename(location) + "'...") - with open(join(location, "run.py"), "r") as ifile: - with open(join(location, "_main.py"), "w") as ofile: + print("Generating '_main.py' from 'run.py' in '" + nstr + "'...") + with (location / "run.py").open("r") as ifile: + with (location / "_main.py").open("w") as ofile: ofile.writelines(["def _main():\n"]) ofile.writelines(["".join([" ", x]) for x in ifile]) - print("Extracting docs from '" + basename(location) + "'...") - sys.path.append(location) + print("Extracting docs from '" + nstr + "'...") + sys.path.append(str(location)) from _main import _main # pylint: disable=import-error,import-outside-toplevel eg_doc = inspect.getdoc(_main) del sys.modules["_main"] - sys.path.remove(location) - remove(join(location, "_main.py")) + sys.path.remove(str(location)) + remove(str(location / "_main.py")) if not eg_doc: print( "WARNING: 'run.py' file in example subdir '" - + basename(location) + + nstr + "' does not contain a docstring. Skipping..." ) return "" diff --git a/tools/release.py b/tools/release.py index cdf4d389a..c3cbc8f48 100644 --- a/tools/release.py +++ b/tools/release.py @@ -15,7 +15,7 @@ import json from urllib.request import urlopen # pylint: disable=no-name-in-module, import-error import sys -from os.path import dirname, join, exists +from pathlib import Path import subprocess from shutil import which @@ -67,8 +67,8 @@ def make_release_commit(version): """ Add release notes and make the release commit """ - run(["git", "add", release_note_file_name(version)]) - run(["git", "add", ABOUT_PY]) + run(["git", "add", str(release_note_file_name(version))]) + run(["git", "add", str(ABOUT_PY)]) run(["git", "commit", "-m", "Release %s" % version]) run(["git", "tag", "v%s" % version, "-a", "-m", "release %s" % version]) @@ -77,7 +77,7 @@ def make_next_pre_release_commit(version): """ Add release notes and make the release commit """ - run(["git", "add", ABOUT_PY]) + run(["git", "add", str(ABOUT_PY)]) run(["git", "commit", "-m", "Start of next release candidate %s" % version]) @@ -87,18 +87,18 @@ def validate_new_release(version, pre_tag): """ release_note = release_note_file_name(version) - if not exists(release_note): + if not release_note.exists(): print( "Not releasing version %s since release note %s does not exist" - % (version, release_note) + % (version, str(release_note)) ) sys.exit(1) - with open(release_note, "r") as fptr: + with release_note.open("r") as fptr: if not fptr.read(): print( "Not releasing version %s since release note %s is empty" - % (version, release_note) + % (version, str(release_note)) ) sys.exit(1) @@ -135,7 +135,7 @@ def set_version(version): Update vunit/about.py with correct version """ - with open(ABOUT_PY, "r") as fptr: + with ABOUT_PY.open("r") as fptr: content = fptr.read() print("Set local version to %s" % version) @@ -143,14 +143,14 @@ def set_version(version): 'VERSION = "%s"' % get_local_version(), 'VERSION = "%s"' % version ) - with open(ABOUT_PY, "w") as fptr: + with ABOUT_PY.open("w") as fptr: fptr.write(content) assert get_local_version() == version -def release_note_file_name(version): - return join(REPO_ROOT, "docs", "release_notes", version + ".rst") +def release_note_file_name(version) -> Path: + return REPO_ROOT / "docs" / "release_notes" / (version + ".rst") def get_local_version(): @@ -160,7 +160,7 @@ def get_local_version(): """ version = ( subprocess.check_output( - [sys.executable, join(REPO_ROOT, "setup.py"), "--version"] + [sys.executable, str(REPO_ROOT / "setup.py"), "--version"] ) .decode() .strip() @@ -180,8 +180,8 @@ def run(cmd): subprocess.check_call(cmd) -REPO_ROOT = join(dirname(__file__), "..") -ABOUT_PY = join(REPO_ROOT, "vunit", "about.py") +REPO_ROOT = Path(__file__).parent.parent +ABOUT_PY = REPO_ROOT / "vunit" / "about.py" if __name__ == "__main__": diff --git a/vunit/__init__.py b/vunit/__init__.py index 218c7688c..77d52478a 100644 --- a/vunit/__init__.py +++ b/vunit/__init__.py @@ -8,14 +8,14 @@ Public VUnit interface """ -from os.path import dirname, join, abspath +from pathlib import Path import vunit.version_check from vunit.ui import VUnit from vunit.vunit_cli import VUnitCLI from vunit.about import version, doc # Repository root -ROOT = abspath(join(dirname(__file__), "..")) +ROOT = str(Path(__file__).parent.parent.resolve()) __version__ = version() __doc__ = doc() # pylint: disable=redefined-builtin diff --git a/vunit/configuration.py b/vunit/configuration.py index d45a3474e..1d38cd240 100644 --- a/vunit/configuration.py +++ b/vunit/configuration.py @@ -10,7 +10,7 @@ import logging import inspect -from os.path import dirname +from pathlib import Path from copy import copy from vunit.sim_if.factory import SIMULATOR_FACTORY @@ -46,7 +46,7 @@ def __init__( # pylint: disable=too-many-arguments self.sim_options = {} if sim_options is None else sim_options self.attributes = {} if attributes is None else attributes - self.tb_path = dirname(design_unit.original_file_name) + self.tb_path = str(Path(design_unit.original_file_name).parent) # Fill in tb_path generic with location of test bench if "tb_path" in design_unit.generic_names: diff --git a/vunit/csv_logs.py b/vunit/csv_logs.py index 7e2ce3550..a22e14574 100644 --- a/vunit/csv_logs.py +++ b/vunit/csv_logs.py @@ -10,7 +10,7 @@ from csv import Sniffer, DictReader, DictWriter from glob import glob -from os.path import abspath +from pathlib import Path class CsvLogs(object): @@ -35,7 +35,7 @@ def __iter__(self): def add(self, pattern): # pylint: disable=missing-docstring - for csv_file in [abspath(p) for p in glob(pattern)]: + for csv_file in [str(Path(p).resolve()) for p in glob(pattern)]: with open(csv_file, "r") as fread: sample = fread.readline() fread.seek(0) diff --git a/vunit/database.py b/vunit/database.py index 2381ea28a..7e35cc7a5 100644 --- a/vunit/database.py +++ b/vunit/database.py @@ -8,7 +8,7 @@ A simple file based database """ -from os.path import join, exists +from pathlib import Path import os import pickle import io @@ -39,7 +39,7 @@ def __init__(self, path, new=False): if new: renew_path(path) - elif not exists(path): + elif not Path(path).exists(): os.makedirs(path) # Map keys to nodes indexes @@ -55,7 +55,7 @@ def _discover_nodes(self): """ keys_to_nodes = {} for file_base_name in os.listdir(self._path): - key = self._read_key(join(self._path, file_base_name)) + key = self._read_key(str(Path(self._path) / file_base_name)) assert key not in keys_to_nodes # Two nodes contains the same key keys_to_nodes[key] = int(file_base_name) return keys_to_nodes @@ -100,7 +100,7 @@ def _to_file_name(self, key): """ Convert key to file name """ - return join(self._path, str(self._keys_to_nodes[key])) + return str(Path(self._path) / str(self._keys_to_nodes[key])) def _allocate_node_for_key(self, key): """ diff --git a/vunit/ostools.py b/vunit/ostools.py index 04f3e70e7..dbc284ddb 100644 --- a/vunit/ostools.py +++ b/vunit/ostools.py @@ -15,8 +15,10 @@ import threading import shutil from queue import Queue, Empty -from os.path import exists, getmtime, dirname, relpath, splitdrive +from pathlib import Path +from os.path import getmtime, relpath, splitdrive import os +from os import getcwd, makedirs import io import logging @@ -296,12 +298,12 @@ def read_file(file_name, encoding="utf-8", newline=None): def write_file(file_name, contents, encoding="utf-8"): """ To stub during testing """ - path = dirname(file_name) + path = str(Path(file_name).parent) if path == "": path = "." if not file_exists(path): - os.makedirs(path) + makedirs(path) with io.open(file_name, "wb") as file_to_write: file_to_write.write(contents.encode(encoding=encoding)) @@ -309,7 +311,7 @@ def write_file(file_name, contents, encoding="utf-8"): def file_exists(file_name): """ To stub during testing """ - return exists(file_name) + return Path(file_name).exists() def get_modification_time(file_name): @@ -334,14 +336,14 @@ def renew_path(path): """ if IS_WINDOWS_SYSTEM: retries = 10 - while retries > 0 and exists(path): + while retries > 0 and Path(path).exists(): shutil.rmtree(path, ignore_errors=retries > 1) time.sleep(0.01) retries -= 1 else: - if exists(path): + if Path(path).exists(): shutil.rmtree(path) - os.makedirs(path) + makedirs(path) def simplify_path(path): @@ -349,7 +351,7 @@ def simplify_path(path): Return relative path towards current working directory unless it is a separate Windows drive """ - cwd = os.getcwd() + cwd = getcwd() drive_cwd = splitdrive(cwd)[0] drive_path = splitdrive(path)[0] if drive_path == drive_cwd: diff --git a/vunit/parsing/verilog/parser.py b/vunit/parsing/verilog/parser.py index 3e152dc05..a2ec6629a 100644 --- a/vunit/parsing/verilog/parser.py +++ b/vunit/parsing/verilog/parser.py @@ -12,7 +12,7 @@ """ import logging -from os.path import dirname, exists, abspath +from pathlib import Path from vunit.ostools import read_file from vunit.parsing.encodings import HDL_FILE_ENCODING from vunit.parsing.tokenizer import TokenStream, EOFException, LocationException @@ -63,7 +63,7 @@ def parse(self, file_name, include_paths=None, defines=None): defines = {} if defines is None else defines include_paths = [] if include_paths is None else include_paths - include_paths = [dirname(file_name)] + include_paths + include_paths = [str(Path(file_name).parent)] + include_paths cached = self._lookup_parse_cache(file_name, include_paths, defines) if cached is not None: @@ -99,7 +99,7 @@ def _key(file_name): """ Returns the database key for parse results of file_name """ - return ("CachedVerilogParser.parse(%s)" % abspath(file_name)).encode() + return ("CachedVerilogParser.parse(%s)" % str(Path(file_name).resolve)).encode() def _store_result(self, file_name, result, included_files, defines): """ @@ -124,7 +124,7 @@ def _content_hash(self, file_name): """ Hash the contents of the file """ - if file_name is None or not exists(file_name): + if file_name is None or not Path(file_name).exists(): return None if file_name not in self._content_cache: self._content_cache[file_name] = file_content_hash( diff --git a/vunit/parsing/verilog/preprocess.py b/vunit/parsing/verilog/preprocess.py index 4a0116e95..c93713c9a 100644 --- a/vunit/parsing/verilog/preprocess.py +++ b/vunit/parsing/verilog/preprocess.py @@ -10,7 +10,7 @@ """ Verilog parsing functionality """ -from os.path import join, exists, abspath +from pathlib import Path import logging from vunit.parsing.tokenizer import ( TokenStream, @@ -350,8 +350,8 @@ def find_included_file(include_paths, file_name): Find the file to include given include_paths """ for include_path in include_paths: - full_name = abspath(join(include_path, file_name)) - if exists(full_name): + full_name = str((Path(include_path) / file_name).resolve()) + if Path(full_name).exists(): return full_name return None diff --git a/vunit/project.py b/vunit/project.py index b66c32744..ea7ac3f9b 100644 --- a/vunit/project.py +++ b/vunit/project.py @@ -9,10 +9,9 @@ """ Functionality to represent and operate on a HDL code project """ -from os.path import join, basename, dirname, isdir, exists +from typing import Optional, Union from pathlib import Path import logging -from typing import Optional from collections import OrderedDict from vunit.hashing import hash_string from vunit.dependency_graph import DependencyGraph, CircularDependencyException @@ -84,7 +83,7 @@ def add_builtin_library(self, logical_name): def add_library( self, logical_name, - directory, + directory: Union[str, Path], vhdl_standard: VHDLStandard = VHDL.STD_2008, is_external=False, ): @@ -94,19 +93,18 @@ def add_library( """ self._validate_new_library_name(logical_name) + dpath = Path(directory) + dstr = str(directory) + if is_external: - if not exists(directory): - raise ValueError("External library %r does not exist" % directory) + if not dpath.exists(): + raise ValueError("External library %r does not exist" % dstr) - if not isdir(directory): - raise ValueError( - "External library must be a directory. Got %r" % directory - ) + if not dpath.is_dir(): + raise ValueError("External library must be a directory. Got %r" % dstr) - library = Library( - logical_name, directory, vhdl_standard, is_external=is_external - ) - LOGGER.debug("Adding library %s with path %s", logical_name, directory) + library = Library(logical_name, dstr, vhdl_standard, is_external=is_external) + LOGGER.debug("Adding library %s with path %s", logical_name, dstr) self._libraries[logical_name] = library self._lower_library_names_dict[logical_name.lower()] = library.name @@ -610,9 +608,12 @@ def _hash_file_name_of(self, source_file): Returns the name of the hash file associated with the source_file """ library = self.get_library(source_file.library.name) - prefix = hash_string(dirname(source_file.name)) - return join( - library.directory, prefix, basename(source_file.name) + ".vunit_hash" + prefix = hash_string(str(Path(source_file.name).parent)) + return str( + Path(library.directory) + / prefix + / Path(source_file.name).name + / ".vunit_hash" ) def update(self, source_file): diff --git a/vunit/sim_if/__init__.py b/vunit/sim_if/__init__.py index 3077962c4..6709b758f 100644 --- a/vunit/sim_if/__init__.py +++ b/vunit/sim_if/__init__.py @@ -10,7 +10,9 @@ import sys import os +from os import environ, listdir, pathsep import subprocess +from pathlib import Path from typing import List from ..ostools import Process, simplify_path from ..exceptions import CompileError @@ -77,12 +79,12 @@ def find_executable(executable): """ Return a list of all executables found in PATH """ - path = os.environ.get("PATH", None) + path = environ.get("PATH", None) if path is None: return [] - paths = path.split(os.pathsep) - _, ext = os.path.splitext(executable) + paths = path.split(pathsep) + ext = Path(executable).suffix if (sys.platform == "win32" or os.name == "os2") and (ext != ".exe"): executable = executable + ".exe" @@ -92,7 +94,7 @@ def find_executable(executable): result.append(executable) for prefix in paths: - file_name = os.path.join(prefix, executable) + file_name = str(Path(prefix) / executable) if isfile(file_name): # the file exists, we have a shot at spawn working result.append(file_name) @@ -133,7 +135,7 @@ def find_toolchain(cls, executables, constraints=None): all_paths = [ [ - os.path.abspath(os.path.dirname(executables)) + str(Path(executables).parent.resolve()) for executables in cls.find_executable(name) ] for name in executables @@ -329,12 +331,13 @@ def get_env(): def isfile(file_name): """ - Case insensitive os.path.isfile + Case insensitive Path.is_file() """ - if not os.path.isfile(file_name): + fpath = Path(file_name) + if not fpath.is_file(): return False - return os.path.basename(file_name) in os.listdir(os.path.dirname(file_name)) + return str(fpath.name) in listdir(str(fpath.parent)) def run_command(command, cwd=None, env=None): diff --git a/vunit/sim_if/activehdl.py b/vunit/sim_if/activehdl.py index e3dc0d2c6..d5af99616 100644 --- a/vunit/sim_if/activehdl.py +++ b/vunit/sim_if/activehdl.py @@ -9,7 +9,7 @@ """ from functools import total_ordering -from os.path import join, dirname, abspath +from pathlib import Path import os import re import logging @@ -58,7 +58,9 @@ def supports_vhdl_package_generics(cls): """ Returns True when this simulator supports VHDL package generics """ - proc = Process([join(cls.find_prefix(), "vcom"), "-version"], env=cls.get_env()) + proc = Process( + [str(Path(cls.find_prefix()) / "vcom"), "-version"], env=cls.get_env() + ) consumer = VersionConsumer() proc.consume_output(consumer) if consumer.version is not None: @@ -68,7 +70,7 @@ def supports_vhdl_package_generics(cls): def __init__(self, prefix, output_path, gui=False): SimulatorInterface.__init__(self, output_path, gui) - self._library_cfg = join(output_path, "library.cfg") + self._library_cfg = str(Path(output_path) / "library.cfg") self._prefix = prefix self._create_library_cfg() self._libraries = [] @@ -112,7 +114,12 @@ def compile_vhdl_file_command(self, source_file): Returns the command to compile a VHDL file """ return ( - [join(self._prefix, "vcom"), "-quiet", "-j", dirname(self._library_cfg)] + [ + str(Path(self._prefix) / "vcom"), + "-quiet", + "-j", + str(Path(self._library_cfg).parent), + ] + source_file.compile_options.get("activehdl.vcom_flags", []) + [ self._std_str(source_file.get_vhdl_standard()), @@ -126,7 +133,7 @@ def compile_verilog_file_command(self, source_file): """ Returns the command to compile a Verilog file """ - args = [join(self._prefix, "vlog"), "-quiet", "-lc", self._library_cfg] + args = [str(Path(self._prefix) / "vlog"), "-quiet", "-lc", self._library_cfg] args += source_file.compile_options.get("activehdl.vlog_flags", []) args += ["-work", source_file.library.name, source_file.name] for library in self._libraries: @@ -143,13 +150,15 @@ def create_library(self, library_name, path, mapped_libraries=None): """ mapped_libraries = mapped_libraries if mapped_libraries is not None else {} - if not file_exists(dirname(abspath(path))): - os.makedirs(dirname(abspath(path))) + apath = str(Path(path).parent.resolve()) + + if not file_exists(apath): + os.makedirs(apath) if not file_exists(path): proc = Process( - [join(self._prefix, "vlib"), library_name, path], - cwd=dirname(self._library_cfg), + [str(Path(self._prefix) / "vlib"), library_name, path], + cwd=str(Path(self._library_cfg).parent), env=self.get_env(), ) proc.consume_output(callback=None) @@ -158,8 +167,8 @@ def create_library(self, library_name, path, mapped_libraries=None): return proc = Process( - [join(self._prefix, "vmap"), library_name, path], - cwd=dirname(self._library_cfg), + [str(Path(self._prefix) / "vmap"), library_name, path], + cwd=str(Path(self._library_cfg).parent), env=self.get_env(), ) proc.consume_output(callback=None) @@ -173,7 +182,8 @@ def _create_library_cfg(self): with open(self._library_cfg, "w") as ofile: ofile.write( - '$INCLUDE = "%s"\n' % join(self._prefix, "..", "vlib", "library.cfg") + '$INCLUDE = "%s"\n' + % str(Path(self._prefix).parent / "vlib" / "library.cfg") ) _library_re = re.compile(r'([a-zA-Z_]+)\s=\s"(.*)"') @@ -192,7 +202,9 @@ def _get_mapped_libraries(self): continue key = match.group(1) value = match.group(2) - libraries[key] = abspath(join(dirname(self._library_cfg), dirname(value))) + libraries[key] = str( + (Path(self._library_cfg).parent / Path(value).parent).resolve() + ) return libraries def _vsim_extra_args(self, config): @@ -243,7 +255,7 @@ def _create_load_function(self, config, output_path): vsim_flags.append(config.architecture_name) if config.sim_options.get("enable_coverage", False): - coverage_file_path = join(output_path, "coverage.acdb") + coverage_file_path = str(Path(output_path) / "coverage.acdb") self._coverage_files.add(coverage_file_path) vsim_flags += ["-acdb_file {%s}" % fix_path(coverage_file_path)] @@ -323,12 +335,12 @@ def merge_coverage(self, file_name, args=None): merge_command += " -o {%s}" % fix_path(file_name) + "\n" - merge_script_name = join(self._output_path, "acdb_merge.tcl") + merge_script_name = str(Path(self._output_path) / "acdb_merge.tcl") with open(merge_script_name, "w") as fptr: fptr.write(merge_command + "\n") vcover_cmd = [ - join(self._prefix, "vsimsa"), + str(Path(self._prefix) / "vsimsa"), "-tcl", "%s" % fix_path(merge_script_name), ] @@ -380,7 +392,7 @@ def _create_gui_script(self, common_file_name, config): init_file = config.sim_options.get(self.name + ".init_file.gui", None) if init_file is not None: - tcl += 'source "%s"\n' % fix_path(abspath(init_file)) + tcl += 'source "%s"\n' % fix_path(str(Path(init_file).resolve())) tcl += ( 'puts "VUnit help: Design already loaded. Use run -all to run the test."\n' @@ -399,10 +411,10 @@ def _run_batch_file(self, batch_file_name, gui, cwd): try: args = [ - join(self._prefix, "vsim"), + str(Path(self._prefix) / "vsim"), "-gui" if gui else "-c", "-l", - join(dirname(batch_file_name), "transcript"), + str(Path(batch_file_name).parent / "transcript"), "-do", todo, ] @@ -417,24 +429,27 @@ def simulate(self, output_path, test_suite_name, config, elaborate_only): """ Run a test bench """ - script_path = join(output_path, self.name) - common_file_name = join(script_path, "common.tcl") - batch_file_name = join(script_path, "batch.tcl") - gui_file_name = join(script_path, "gui.tcl") + script_path = Path(output_path) / self.name + common_file_name = script_path / "common.tcl" + batch_file_name = script_path / "batch.tcl" + gui_file_name = script_path / "gui.tcl" write_file(common_file_name, self._create_common_script(config, output_path)) - write_file(gui_file_name, self._create_gui_script(common_file_name, config)) write_file( - batch_file_name, self._create_batch_script(common_file_name, elaborate_only) + gui_file_name, self._create_gui_script(str(common_file_name), config) + ) + write_file( + str(batch_file_name), + self._create_batch_script(str(common_file_name), elaborate_only), ) if self._gui: - gui_path = join(script_path, "gui") + gui_path = str(script_path / "gui") renew_path(gui_path) - return self._run_batch_file(gui_file_name, gui=True, cwd=gui_path) + return self._run_batch_file(str(gui_file_name), gui=True, cwd=gui_path) return self._run_batch_file( - batch_file_name, gui=False, cwd=dirname(self._library_cfg) + str(batch_file_name), gui=False, cwd=str(Path(self._library_cfg).parent) ) diff --git a/vunit/sim_if/ghdl.py b/vunit/sim_if/ghdl.py index 0e70e9f88..ae0a49fd3 100644 --- a/vunit/sim_if/ghdl.py +++ b/vunit/sim_if/ghdl.py @@ -9,8 +9,7 @@ """ from pathlib import Path -from os.path import exists, join, abspath -import os +from os import environ, makedirs, remove import logging import subprocess import shlex @@ -32,7 +31,7 @@ class GHDLInterface(SimulatorInterface): """ name = "ghdl" - executable = os.environ.get("GHDL", "ghdl") + executable = environ.get("GHDL", "ghdl") supports_gui_flag = True supports_colors_in_gui = True @@ -122,7 +121,7 @@ def _get_version_output(cls, prefix): Get the output of 'ghdl --version' """ return subprocess.check_output( - [join(prefix, cls.executable), "--version"] + [str(Path(prefix) / cls.executable), "--version"] ).decode() @classmethod @@ -183,8 +182,8 @@ def setup_library_mapping(self, project): """ self._project = project for library in project.get_libraries(): - if not exists(library.directory): - os.makedirs(library.directory) + if not Path(library.directory).exists(): + makedirs(library.directory) vhdl_standards = set( source_file.get_vhdl_standard() @@ -233,7 +232,7 @@ def compile_vhdl_file_command(self, source_file): Returns the command to compile a vhdl file """ cmd = [ - join(self._prefix, self.executable), + str(Path(self._prefix) / self.executable), "-a", "--workdir=%s" % source_file.library.directory, "--work=%s" % source_file.library.name, @@ -262,7 +261,7 @@ def _get_command(self, config, output_path, elaborate_only, ghdl_e, wave_file): """ Return GHDL simulation command """ - cmd = [join(self._prefix, self.executable)] + cmd = [str(Path(self._prefix) / self.executable)] if ghdl_e: cmd += ["-e"] @@ -276,8 +275,9 @@ def _get_command(self, config, output_path, elaborate_only, ghdl_e, wave_file): ] cmd += ["-P%s" % lib.directory for lib in self._project.get_libraries()] - bin_path = join( - output_path, "%s-%s" % (config.entity_name, config.architecture_name) + bin_path = str( + Path(output_path) + / ("%s-%s" % (config.entity_name, config.architecture_name)) ) if self._has_output_flag(): cmd += ["-o", bin_path] @@ -303,10 +303,10 @@ def _get_command(self, config, output_path, elaborate_only, ghdl_e, wave_file): cmd += ["--no-run"] else: try: - os.makedirs(output_path, mode=0o777) + makedirs(output_path, mode=0o777) except OSError: pass - with open(join(output_path, "args.json"), "w") as fname: + with (Path(output_path) / "args.json").open("w") as fname: dump( { "bin": str( @@ -328,17 +328,17 @@ def simulate( # pylint: disable=too-many-locals Simulate with entity as top level using generics """ - script_path = join(output_path, self.name) + script_path = str(Path(output_path) / self.name) - if not exists(script_path): - os.makedirs(script_path) + if not Path(script_path).exists(): + makedirs(script_path) ghdl_e = elaborate_only and config.sim_options.get("ghdl.elab_e", False) if self._gtkwave_fmt is not None: - data_file_name = join(script_path, "wave.%s" % self._gtkwave_fmt) - if exists(data_file_name): - os.remove(data_file_name) + data_file_name = str(Path(script_path) / ("wave.%s" % self._gtkwave_fmt)) + if Path(data_file_name).exists(): + remove(data_file_name) else: data_file_name = None @@ -358,7 +358,7 @@ def simulate( # pylint: disable=too-many-locals init_file = config.sim_options.get(self.name + ".gtkwave_script.gui", None) if init_file is not None: - cmd += ["--script", "{}".format(abspath(init_file))] + cmd += ["--script", "{}".format(str(Path(init_file).resolve()))] stdout.write("%s\n" % " ".join(cmd)) subprocess.call(cmd) diff --git a/vunit/sim_if/incisive.py b/vunit/sim_if/incisive.py index c0ec4bad4..5dc683b00 100644 --- a/vunit/sim_if/incisive.py +++ b/vunit/sim_if/incisive.py @@ -8,7 +8,8 @@ Interface for the Cadence Incisive simulator """ -from os.path import join, dirname, abspath, relpath +from pathlib import Path +from os.path import relpath import os import subprocess import logging @@ -94,9 +95,9 @@ def __init__( # pylint: disable=too-many-arguments self._libraries = [] self._log_level = log_level if cdslib is None: - self._cdslib = abspath(join(output_path, "cds.lib")) + self._cdslib = str((Path(output_path) / "cds.lib").resolve()) else: - self._cdslib = abspath(cdslib) + self._cdslib = str(Path(cdslib).resolve()) self._hdlvar = hdlvar self._cds_root_irun = self.find_cds_root_irun() self._create_cdslib() @@ -106,7 +107,7 @@ def find_cds_root_irun(self): Finds irun cds root """ return subprocess.check_output( - [join(self._prefix, "cds_root"), "irun"] + [str(Path(self._prefix) / "cds_root"), "irun"] ).splitlines()[0] def find_cds_root_virtuoso(self): @@ -115,7 +116,7 @@ def find_cds_root_virtuoso(self): """ try: return subprocess.check_output( - [join(self._prefix, "cds_root"), "virtuoso"] + [str(Path(self._prefix) / "cds_root"), "virtuoso"] ).splitlines()[0] except subprocess.CalledProcessError: return None @@ -192,7 +193,7 @@ def compile_vhdl_file_command(self, source_file): """ Returns command to compile a VHDL file """ - cmd = join(self._prefix, "irun") + cmd = str(Path(self._prefix) / "irun") args = [] args += ["-compile"] args += ["-nocopyright"] @@ -205,9 +206,9 @@ def compile_vhdl_file_command(self, source_file): args += self._hdlvar_args() args += [ '-log "%s"' - % join( - self._output_path, - "irun_compile_vhdl_file_%s.log" % source_file.library.name, + % str( + Path(self._output_path) + / ("irun_compile_vhdl_file_%s.log" % source_file.library.name) ) ] if not self._log_level == "debug": @@ -216,13 +217,13 @@ def compile_vhdl_file_command(self, source_file): args += ["-messages"] args += ["-libverbose"] args += source_file.compile_options.get("incisive.irun_vhdl_flags", []) - args += ['-nclibdirname "%s"' % dirname(source_file.library.directory)] + args += ['-nclibdirname "%s"' % str(Path(source_file.library.directory).parent)] args += ["-makelib %s" % source_file.library.directory] args += ['"%s"' % source_file.name] args += ["-endlib"] - argsfile = join( - self._output_path, - "irun_compile_vhdl_file_%s.args" % source_file.library.name, + argsfile = str( + Path(self._output_path) + / ("irun_compile_vhdl_file_%s.args" % source_file.library.name) ) write_file(argsfile, "\n".join(args)) return [cmd, "-f", argsfile] @@ -231,7 +232,7 @@ def compile_verilog_file_command(self, source_file): """ Returns commands to compile a Verilog file """ - cmd = join(self._prefix, "irun") + cmd = str(Path(self._prefix) / "irun") args = [] args += ["-compile"] args += ["-nocopyright"] @@ -248,9 +249,9 @@ def compile_verilog_file_command(self, source_file): args += self._hdlvar_args() args += [ '-log "%s"' - % join( - self._output_path, - "irun_compile_verilog_file_%s.log" % source_file.library.name, + % str( + Path(self._output_path) + / ("irun_compile_verilog_file_%s.log" % source_file.library.name) ) ] if not self._log_level == "debug": @@ -266,13 +267,13 @@ def compile_verilog_file_command(self, source_file): for key, value in source_file.defines.items(): args += ["-define %s=%s" % (key, value.replace('"', '\\"'))] - args += ['-nclibdirname "%s"' % dirname(source_file.library.directory)] + args += ['-nclibdirname "%s"' % str(Path(source_file.library.directory).parent)] args += ["-makelib %s" % source_file.library.name] args += ['"%s"' % source_file.name] args += ["-endlib"] - argsfile = join( - self._output_path, - "irun_compile_verilog_file_%s.args" % source_file.library.name, + argsfile = str( + Path(self._output_path) + / ("irun_compile_verilog_file_%s.args" % source_file.library.name) ) write_file(argsfile, "\n".join(args)) return [cmd, "-f", argsfile] @@ -283,8 +284,10 @@ def create_library(self, library_name, library_path, mapped_libraries=None): """ mapped_libraries = mapped_libraries if mapped_libraries is not None else {} - if not file_exists(dirname(abspath(library_path))): - os.makedirs(dirname(abspath(library_path))) + lpath = str(Path(library_path).resolve().parent) + + if not file_exists(lpath): + os.makedirs(lpath) if ( library_name in mapped_libraries @@ -310,7 +313,7 @@ def simulate( # pylint: disable=too-many-locals Elaborates and Simulates with entity as top level using generics """ - script_path = join(output_path, self.name) + script_path = str(Path(output_path) / self.name) launch_gui = self._gui is not False and not elaborate_only if elaborate_only: @@ -319,7 +322,7 @@ def simulate( # pylint: disable=too-many-locals steps = ["elaborate", "simulate"] for step in steps: - cmd = join(self._prefix, "irun") + cmd = str(Path(self._prefix) / "irun") args = [] if step == "elaborate": args += ["-elaborate"] @@ -345,12 +348,12 @@ def simulate( # pylint: disable=too-many-locals ] # promote to error: "bad natural literal in generic association" args += ["-work work"] args += [ - '-nclibdirname "%s"' % (join(self._output_path, "libraries")) + '-nclibdirname "%s"' % (str(Path(self._output_path) / "libraries")) ] # @TODO: ugly args += config.sim_options.get("incisive.irun_sim_flags", []) args += ['-cdslib "%s"' % self._cdslib] args += self._hdlvar_args() - args += ['-log "%s"' % join(script_path, "irun_%s.log" % step)] + args += ['-log "%s"' % str(Path(script_path) / ("irun_%s.log" % step))] if not self._log_level == "debug": args += ["-quiet"] else: @@ -369,21 +372,15 @@ def simulate( # pylint: disable=too-many-locals if config.architecture_name is None: # we have a SystemVerilog toplevel: - args += [ - "-top %s" - % join("%s.%s:sv" % (config.library_name, config.entity_name)) - ] + args += ["-top %s.%s:sv" % (config.library_name, config.entity_name)] else: # we have a VHDL toplevel: args += [ - "-top %s" - % join( - "%s.%s:%s" - % ( - config.library_name, - config.entity_name, - config.architecture_name, - ) + "-top %s.%s:%s" + % ( + config.library_name, + config.entity_name, + config.architecture_name, ) ] argsfile = "%s/irun_%s.args" % (script_path, step) diff --git a/vunit/sim_if/modelsim.py b/vunit/sim_if/modelsim.py index 1a5af9352..e14e22f37 100644 --- a/vunit/sim_if/modelsim.py +++ b/vunit/sim_if/modelsim.py @@ -8,7 +8,7 @@ Interface towards Mentor Graphics ModelSim """ -from os.path import join, dirname, abspath +from pathlib import Path import os import logging import io @@ -70,7 +70,7 @@ def find_prefix_from_path(cls): """ def has_modelsim_ini(path): - return os.path.isfile(join(path, "..", "modelsim.ini")) + return os.path.isfile(str(Path(path) / "modelsim.ini")) return cls.find_toolchain(["vsim"], constraints=[has_modelsim_ini]) @@ -87,7 +87,7 @@ def __init__(self, prefix, output_path, persistent=False, gui=False): self, prefix, persistent, - sim_cfg_file_name=join(output_path, "modelsim.ini"), + sim_cfg_file_name=str(Path(output_path) / "modelsim.ini"), ) self._libraries = [] self._coverage_files = set() @@ -98,12 +98,12 @@ def _create_modelsim_ini(self): """ Create the modelsim.ini file """ - parent = dirname(self._sim_cfg_file_name) + parent = str(Path(self._sim_cfg_file_name).parent) if not file_exists(parent): os.makedirs(parent) original_modelsim_ini = os.environ.get( - "VUNIT_MODELSIM_INI", join(self._prefix, "..", "modelsim.ini") + "VUNIT_MODELSIM_INI", str(Path(self._prefix).parent / "modelsim.ini") ) with open(original_modelsim_ini, "rb") as fread: with open(self._sim_cfg_file_name, "wb") as fwrite: @@ -157,7 +157,7 @@ def compile_vhdl_file_command(self, source_file): """ return ( [ - join(self._prefix, "vcom"), + str(Path(self._prefix) / "vcom"), "-quiet", "-modelsimini", self._sim_cfg_file_name, @@ -176,7 +176,7 @@ def compile_verilog_file_command(self, source_file): Returns the command to compile a verilog file """ args = [ - join(self._prefix, "vlog"), + str(Path(self._prefix) / "vlog"), "-quiet", "-modelsimini", self._sim_cfg_file_name, @@ -200,12 +200,14 @@ def create_library(self, library_name, path, mapped_libraries=None): """ mapped_libraries = mapped_libraries if mapped_libraries is not None else {} - if not file_exists(dirname(abspath(path))): - os.makedirs(dirname(abspath(path))) + apath = str(Path(path).parent.resolve()) + + if not file_exists(apath): + os.makedirs(apath) if not file_exists(path): proc = Process( - [join(self._prefix, "vlib"), "-unix", path], env=self.get_env() + [str(Path(self._prefix) / "vlib"), "-unix", path], env=self.get_env() ) proc.consume_output(callback=None) @@ -247,7 +249,7 @@ def _create_load_function(self, test_suite_name, config, output_path): architecture_suffix = "(%s)" % config.architecture_name if config.sim_options.get("enable_coverage", False): - coverage_file = join(output_path, "coverage.ucdb") + coverage_file = str(Path(output_path) / "coverage.ucdb") self._coverage_files.add(coverage_file) coverage_save_cmd = ( "coverage save -onexit -testname {%s} -assert -directive -cvg -codeAll {%s}" @@ -259,7 +261,7 @@ def _create_load_function(self, test_suite_name, config, output_path): coverage_args = "" vsim_flags = [ - "-wlf {%s}" % fix_path(join(output_path, "vsim.wlf")), + "-wlf {%s}" % fix_path(str(Path(output_path) / "vsim.wlf")), "-quiet", "-t ps", # for correct handling of verilog fatal/finish @@ -383,9 +385,9 @@ def merge_coverage(self, file_name, args=None): if args is None: args = [] - coverage_files = join(self._output_path, "coverage_files.txt") + coverage_files = str(Path(self._output_path) / "coverage_files.txt") vcover_cmd = ( - [join(self._prefix, "vcover"), "merge", "-inputs"] + [str(Path(self._prefix) / "vcover"), "merge", "-inputs"] + [coverage_files] + args + [file_name] diff --git a/vunit/sim_if/rivierapro.py b/vunit/sim_if/rivierapro.py index 0cb9b1766..2e66ad7ce 100644 --- a/vunit/sim_if/rivierapro.py +++ b/vunit/sim_if/rivierapro.py @@ -8,7 +8,7 @@ Interface towards Aldec Riviera Pro """ -from os.path import join, dirname, abspath +from pathlib import Path import os import re import logging @@ -66,7 +66,7 @@ def find_prefix_from_path(cls): """ def no_avhdl(path): - return not file_exists(join(path, "avhdl.exe")) + return not file_exists(str(Path(path) / "avhdl.exe")) return cls.find_toolchain(["vsim", "vsimsa"], constraints=[no_avhdl]) @@ -75,7 +75,9 @@ def get_osvvm_coverage_api(cls): """ Returns simulator name when OSVVM coverage API is supported, None otherwise. """ - proc = Process([join(cls.find_prefix(), "vcom"), "-version"], env=cls.get_env()) + proc = Process( + [str(Path(cls.find_prefix()) / "vcom"), "-version"], env=cls.get_env() + ) consumer = VersionConsumer() proc.consume_output(consumer) if consumer.year is not None: @@ -96,7 +98,10 @@ def supports_vhdl_package_generics(cls): def __init__(self, prefix, output_path, persistent=False, gui=False): SimulatorInterface.__init__(self, output_path, gui) VsimSimulatorMixin.__init__( - self, prefix, persistent, sim_cfg_file_name=join(output_path, "library.cfg") + self, + prefix, + persistent, + sim_cfg_file_name=str(Path(output_path) / "library.cfg"), ) self._create_library_cfg() self._libraries = [] @@ -151,10 +156,10 @@ def compile_vhdl_file_command(self, source_file): return ( [ - join(self._prefix, "vcom"), + str(Path(self._prefix) / "vcom"), "-quiet", "-j", - dirname(self._sim_cfg_file_name), + str(Path(self._sim_cfg_file_name).parent), ] + source_file.compile_options.get("rivierapro.vcom_flags", []) + [ @@ -169,7 +174,12 @@ def compile_verilog_file_command(self, source_file): """ Returns the command to compile a Verilog file """ - args = [join(self._prefix, "vlog"), "-quiet", "-lc", self._sim_cfg_file_name] + args = [ + str(Path(self._prefix) / "vlog"), + "-quiet", + "-lc", + self._sim_cfg_file_name, + ] if source_file.is_system_verilog: args += ["-sv2k12"] args += source_file.compile_options.get("rivierapro.vlog_flags", []) @@ -188,13 +198,15 @@ def create_library(self, library_name, path, mapped_libraries=None): """ mapped_libraries = mapped_libraries if mapped_libraries is not None else {} - if not file_exists(dirname(abspath(path))): - os.makedirs(dirname(abspath(path))) + apath = str(Path(path).parent.resolve()) + + if not file_exists(apath): + os.makedirs(apath) if not file_exists(path): proc = Process( - [join(self._prefix, "vlib"), library_name, path], - cwd=dirname(self._sim_cfg_file_name), + [str(Path(self._prefix) / "vlib"), library_name, path], + cwd=str(Path(self._sim_cfg_file_name).parent), env=self.get_env(), ) proc.consume_output(callback=None) @@ -203,8 +215,8 @@ def create_library(self, library_name, path, mapped_libraries=None): return proc = Process( - [join(self._prefix, "vmap"), library_name, path], - cwd=dirname(self._sim_cfg_file_name), + [str(Path(self._prefix) / "vmap"), library_name, path], + cwd=str(Path(self._sim_cfg_file_name).parent), env=self.get_env(), ) proc.consume_output(callback=None) @@ -221,7 +233,7 @@ def _create_library_cfg(self): @property def _builtin_library_cfg(self): - return join(self._prefix, "..", "vlib", "library.cfg") + return str(Path(self._prefix).parent / "vlib" / "library.cfg") _library_re = re.compile(r"([a-zA-Z_0-9]+)\s=\s(.*)") @@ -230,7 +242,9 @@ def _get_mapped_libraries(self, library_cfg_file): Get mapped libraries by running vlist on the working directory """ lines = [] - proc = Process([join(self._prefix, "vlist")], cwd=dirname(library_cfg_file)) + proc = Process( + [str(Path(self._prefix) / "vlist")], cwd=str(Path(library_cfg_file).parent) + ) proc.consume_output(callback=lines.append) libraries = {} @@ -240,7 +254,9 @@ def _get_mapped_libraries(self, library_cfg_file): continue key = match.group(1) value = match.group(2) - libraries[key] = abspath(join(dirname(library_cfg_file), dirname(value))) + libraries[key] = str( + (Path(library_cfg_file).parent / (Path(value).parent)).resolve() + ) return libraries def _create_load_function( @@ -260,13 +276,13 @@ def _create_load_function( ) vsim_flags = [ - "-dataset {%s}" % fix_path(join(output_path, "dataset.asdb")), + "-dataset {%s}" % fix_path(str(Path(output_path) / "dataset.asdb")), pli_str, set_generic_str, ] if config.sim_options.get("enable_coverage", False): - coverage_file_path = join(output_path, "coverage.acdb") + coverage_file_path = str(Path(output_path) / "coverage.acdb") self._coverage_files.add(coverage_file_path) vsim_flags += ["-acdb_file {%s}" % coverage_file_path] @@ -384,12 +400,12 @@ def merge_coverage(self, file_name, args=None): merge_command += " -o {%s}" % file_name.replace("\\", "/") - merge_script_name = join(self._output_path, "acdb_merge.tcl") + merge_script_name = str(Path(self._output_path) / "acdb_merge.tcl") with open(merge_script_name, "w") as fptr: fptr.write(merge_command + "\n") vcover_cmd = [ - join(self._prefix, "vsim"), + str(Path(self._prefix) / "vsim"), "-c", "-do", "source %s; quit;" % merge_script_name.replace("\\", "/"), diff --git a/vunit/sim_if/vsim_simulator_mixin.py b/vunit/sim_if/vsim_simulator_mixin.py index f5eee9a07..81d0cad3a 100644 --- a/vunit/sim_if/vsim_simulator_mixin.py +++ b/vunit/sim_if/vsim_simulator_mixin.py @@ -11,7 +11,7 @@ import sys import os -from os.path import join, dirname, abspath +from pathlib import Path from ..ostools import write_file, Process from ..test.suites import get_result_file_name from ..persistent_tcl_shell import PersistentTclShell @@ -25,7 +25,7 @@ class VsimSimulatorMixin(object): def __init__(self, prefix, persistent, sim_cfg_file_name): self._prefix = prefix - sim_cfg_file_name = abspath(sim_cfg_file_name) + sim_cfg_file_name = str(Path(sim_cfg_file_name).resolve()) self._sim_cfg_file_name = sim_cfg_file_name prefix = ( @@ -36,14 +36,14 @@ def __init__(self, prefix, persistent, sim_cfg_file_name): def create_process(ident): return Process( [ - join(prefix, "vsim"), + str(Path(prefix) / "vsim"), "-c", "-l", - join(dirname(sim_cfg_file_name), "transcript%i" % ident), + str(Path(sim_cfg_file_name).parent / ("transcript%i" % ident)), "-do", - abspath(join(dirname(__file__), "tcl_read_eval_loop.tcl")), + str((Path(__file__).parent / "tcl_read_eval_loop.tcl").resolve()), ], - cwd=dirname(sim_cfg_file_name), + cwd=str(Path(sim_cfg_file_name).parent), env=env, ) @@ -91,7 +91,7 @@ def _create_restart_function(): "stdout=sys.stdout, " "stderr=sys.stdout))" ) - % (recompile_command, abspath(os.getcwd())), + % (recompile_command, str(Path(os.getcwd()).resolve())), ] recompile_command_eval_tcl = " ".join( ["{%s}" % part for part in recompile_command_eval] @@ -254,8 +254,8 @@ def _source_tcl_file(file_name, config, message): } """ tcl = template % ( - fix_path(abspath(config.tb_path)), - fix_path(abspath(file_name)), + fix_path(str(Path(config.tb_path).resolve())), + fix_path(str(Path(file_name).resolve())), message, ) return tcl @@ -279,15 +279,15 @@ def _run_batch_file(self, batch_file_name, gui=False): try: args = [ - join(self._prefix, "vsim"), + str(Path(self._prefix) / "vsim"), "-gui" if gui else "-c", "-l", - join(dirname(batch_file_name), "transcript"), + str(Path(batch_file_name).parent / "transcript"), "-do", 'source "%s"' % fix_path(batch_file_name), ] - proc = Process(args, cwd=dirname(self._sim_cfg_file_name)) + proc = Process(args, cwd=str(Path(self._sim_cfg_file_name).parent)) proc.consume_output() except Process.NonZeroExitCode: return False @@ -316,30 +316,33 @@ def simulate(self, output_path, test_suite_name, config, elaborate_only): """ Run a test bench """ - script_path = join(output_path, self.name) + script_path = Path(output_path) / self.name - common_file_name = join(script_path, "common.do") - gui_file_name = join(script_path, "gui.do") - batch_file_name = join(script_path, "batch.do") + common_file_name = script_path / "common.do" + gui_file_name = script_path / "gui.do" + batch_file_name = script_path / "batch.do" write_file( - common_file_name, + str(common_file_name), self._create_common_script( test_suite_name, config, script_path, output_path ), ) - write_file(gui_file_name, self._create_gui_script(common_file_name, config)) write_file( - batch_file_name, self._create_batch_script(common_file_name, elaborate_only) + str(gui_file_name), self._create_gui_script(str(common_file_name), config) + ) + write_file( + str(batch_file_name), + self._create_batch_script(str(common_file_name), elaborate_only), ) if self._gui: - return self._run_batch_file(gui_file_name, gui=True) + return self._run_batch_file(str(gui_file_name), gui=True) if self._persistent_shell is not None: - return self._run_persistent(common_file_name, load_only=elaborate_only) + return self._run_persistent(str(common_file_name), load_only=elaborate_only) - return self._run_batch_file(batch_file_name) + return self._run_batch_file(str(batch_file_name)) def fix_path(path): diff --git a/vunit/source_file.py b/vunit/source_file.py index 4dc763ba8..81731bba2 100644 --- a/vunit/source_file.py +++ b/vunit/source_file.py @@ -9,7 +9,6 @@ """ from pathlib import Path from typing import Union -from os.path import splitext import logging from copy import copy import traceback @@ -369,7 +368,7 @@ def file_type_of(file_name): """ Return the file type of file_name based on the file ending """ - _, ext = splitext(file_name) + ext = str(Path(file_name).suffix) if ext.lower() in VHDL_EXTENSIONS: return "vhdl" diff --git a/vunit/test/bench.py b/vunit/test/bench.py index f3035ef92..d411c60ea 100644 --- a/vunit/test/bench.py +++ b/vunit/test/bench.py @@ -9,7 +9,7 @@ """ import logging -from os.path import basename +from pathlib import Path import re import bisect import collections @@ -98,7 +98,7 @@ def _check_architectures(design_unit): % ( design_unit.name, ", ".join( - "%s:%s" % (name, basename(fname)) + "%s:%s" % (name, str(Path(fname).name)) for name, fname in sorted( design_unit.architecture_names.items() ) diff --git a/vunit/test/report.py b/vunit/test/report.py index 9efb026e0..19900965e 100644 --- a/vunit/test/report.py +++ b/vunit/test/report.py @@ -13,7 +13,7 @@ import os import socket import re -from os.path import dirname +from pathlib import Path from vunit.color_printer import COLOR_PRINTER from vunit.ostools import read_file @@ -325,5 +325,5 @@ def to_dict(self): return { "status": self._status.name, "time": self.time, - "path": dirname(self._output_file_name), + "path": str(Path(self._output_file_name).parent), } diff --git a/vunit/test/runner.py b/vunit/test/runner.py index 5ab718e0a..bc514ff47 100644 --- a/vunit/test/runner.py +++ b/vunit/test/runner.py @@ -9,7 +9,8 @@ """ import os -from os.path import join, exists, abspath, basename, relpath +from os.path import relpath +from pathlib import Path import traceback import threading import sys @@ -77,7 +78,7 @@ def run(self, test_suites): Run a list of test suites """ - if not exists(self._output_path): + if not Path(self._output_path).exists(): os.makedirs(self._output_path) self._create_test_mapping_file(test_suites) @@ -145,7 +146,7 @@ def _run_thread(self, write_stdout, scheduler, num_tests, is_main): test_suite = scheduler.next() output_path = create_output_path(self._output_path, test_suite.name) - output_file_name = join(output_path, "output.txt") + output_file_name = str(Path(output_path) / "output.txt") with self._stdout_lock(): for test_name in test_suite.test_names: @@ -187,7 +188,7 @@ def _run_test_suite( """ Run the actual test suite """ - color_output_file_name = join(output_path, "output_with_color.txt") + color_output_file_name = str(Path(output_path) / "output_with_color.txt") output_file = None color_output_file = None @@ -263,11 +264,13 @@ def _create_test_mapping_file(self, test_suites): Create a file mapping test name to test output folder. This is to allow the user to find the test output folder when it is hashed """ - mapping_file_name = join(self._output_path, "test_name_to_path_mapping.txt") + mapping_file_name = str( + Path(self._output_path) / "test_name_to_path_mapping.txt" + ) # Load old mapping to remember non-deleted test folders as well # even when re-running only a single test case - if exists(mapping_file_name): + if Path(mapping_file_name).exists(): with open(mapping_file_name, "r") as fptr: mapping = set(fptr.read().splitlines()) else: @@ -275,7 +278,7 @@ def _create_test_mapping_file(self, test_suites): for test_suite in test_suites: test_output = create_output_path(self._output_path, test_suite.name) - mapping.add("%s %s" % (basename(test_output), test_suite.name)) + mapping.add("%s %s" % (Path(test_output).name, test_suite.name)) # Sort by everything except hash mapping = sorted(mapping, key=lambda value: value[value.index(" ") :]) @@ -288,7 +291,7 @@ def _print_output(self, output_file_name): """ Print contents of output file if it exists """ - with open(output_file_name, "r") as fread: + with Path(output_file_name).open("r") as fread: for line in fread.readlines(): self._stdout_ansi.write(line) @@ -433,7 +436,7 @@ def create_output_path(output_path, test_suite_name): Create the full output path of a test case. Ensure no bad characters and no long path names. """ - output_path = abspath(output_path) + output_path = str(Path(output_path).resolve()) safe_name = ( "".join(char if _is_legal(char) else "_" for char in test_suite_name) + "_" ) @@ -454,7 +457,7 @@ def create_output_path(output_path, test_suite_name): else: full_name = safe_name + hash_name - return join(output_path, full_name) + return str(Path(output_path) / full_name) def wrap(file_obj, use_color=True): diff --git a/vunit/test/suites.py b/vunit/test/suites.py index 846ff06af..e7d069937 100644 --- a/vunit/test/suites.py +++ b/vunit/test/suites.py @@ -8,7 +8,7 @@ Contains different kinds of test suites """ -from os.path import join +from pathlib import Path from .. import ostools from .report import PASSED, SKIPPED, FAILED @@ -345,4 +345,4 @@ def _full_name(test_suite_name, test_case_name): def get_result_file_name(output_path): - return join(output_path, "vunit_results") + return str(Path(output_path) / "vunit_results") diff --git a/vunit/ui/__init__.py b/vunit/ui/__init__.py index d6dca10ed..33fc882c0 100644 --- a/vunit/ui/__init__.py +++ b/vunit/ui/__init__.py @@ -16,8 +16,8 @@ import logging import json import os -from typing import Optional, Set -from os.path import exists, abspath, join, basename, normpath, dirname +from typing import Optional, Set, Union +from pathlib import Path from fnmatch import fnmatch from ..database import PickledDataBase, DataBase from .. import ostools @@ -58,7 +58,10 @@ class VUnit( # pylint: disable=too-many-instance-attributes, too-many-public-me @classmethod def from_argv( - cls, argv=None, compile_builtins=True, vhdl_standard: Optional[str] = None + cls, + argv=None, + compile_builtins: Optional[bool] = True, + vhdl_standard: Optional[str] = None, ): """ Create VUnit instance from command line arguments. @@ -84,7 +87,10 @@ def from_argv( @classmethod def from_args( - cls, args, compile_builtins=True, vhdl_standard: Optional[str] = None + cls, + args, + compile_builtins: Optional[bool] = True, + vhdl_standard: Optional[str] = None, ): """ Create VUnit instance from args namespace. @@ -102,11 +108,14 @@ def from_args( return cls(args, compile_builtins=compile_builtins, vhdl_standard=vhdl_standard) def __init__( - self, args, compile_builtins=True, vhdl_standard: Optional[str] = None + self, + args, + compile_builtins: Optional[bool] = True, + vhdl_standard: Optional[str] = None, ): self._args = args self._configure_logging(args.log_level) - self._output_path = abspath(args.output_path) + self._output_path = str(Path(args.output_path).resolve()) if args.no_color: self._printer = NO_COLOR_PRINTER @@ -135,10 +144,12 @@ def test_filter(name, attribute_names): # Use default simulator options if no simulator was present if self._simulator_class is None: simulator_class = SimulatorInterface - self._simulator_output_path = join(self._output_path, "none") + self._simulator_output_path = str(Path(self._output_path) / "none") else: simulator_class = self._simulator_class - self._simulator_output_path = join(self._output_path, simulator_class.name) + self._simulator_output_path = str( + Path(self._output_path) / simulator_class.name + ) self._create_output_path(args.clean) @@ -161,7 +172,7 @@ def _create_database(self): Check for Python version used to create the database is the same as the running python instance or re-create """ - project_database_file_name = join(self._output_path, "project_database") + project_database_file_name = str(Path(self._output_path) / "project_database") create_new = False key = b"version" version = str((9, sys.version)).encode() @@ -202,7 +213,7 @@ def _which_vhdl_standard(self, vhdl_standard: Optional[str]) -> VHDLStandard: return VHDL.standard(vhdl_standard) def add_external_library( - self, library_name, path, vhdl_standard: Optional[str] = None + self, library_name, path: Union[str, Path], vhdl_standard: Optional[str] = None ): """ Add an externally compiled library as a black-box @@ -223,14 +234,14 @@ def add_external_library( self._project.add_library( library_name, - abspath(path), + Path(path).resolve(), self._which_vhdl_standard(vhdl_standard), is_external=True, ) return self.library(library_name) def add_source_files_from_csv( - self, project_csv_path, vhdl_standard: Optional[str] = None + self, project_csv_path: Union[str, Path], vhdl_standard: Optional[str] = None ): """ Add a project configuration, mapping all the libraries and files @@ -247,14 +258,14 @@ def add_source_files_from_csv( libs: Set[str] = set() files = SourceFileList(list()) - with open(project_csv_path) as csv_path_file: + ppath = Path(project_csv_path) + + with ppath.open() as csv_path_file: for row in csv.reader(csv_path_file): if len(row) == 2: lib_name = row[0].strip() no_normalized_file = row[1].strip() - file_name_ = normpath( - join(dirname(project_csv_path), no_normalized_file) - ) + file_name_ = str((ppath.parent / no_normalized_file).resolve()) lib = ( self.library(lib_name) if lib_name in libs @@ -270,7 +281,10 @@ def add_source_files_from_csv( return files def add_library( - self, library_name, vhdl_standard: Optional[str] = None, allow_duplicate=False + self, + library_name: str, + vhdl_standard: Optional[str] = None, + allow_duplicate: Optional[bool] = False, ): """ Add a library managed by VUnit. @@ -291,10 +305,9 @@ def add_library( """ standard = self._which_vhdl_standard(vhdl_standard) - - path = join(self._simulator_output_path, "libraries", library_name) + path = Path(self._simulator_output_path) / "libraries" / library_name if not self._project.has_library(library_name): - self._project.add_library(library_name, abspath(path), standard) + self._project.add_library(library_name, str(path.resolve()), standard) elif not allow_duplicate: raise ValueError( "Library %s already added. Use allow_duplicate to ignore this error." @@ -302,7 +315,7 @@ def add_library( ) return self.library(library_name) - def library(self, library_name): + def library(self, library_name: str): """ Get a library @@ -313,7 +326,7 @@ def library(self, library_name): raise KeyError(library_name) return Library(library_name, self, self._project, self._test_bench_list) - def set_attribute(self, name, value, allow_empty=False): + def set_attribute(self, name: str, value: str, allow_empty: Optional[bool] = False): """ Set a value of attribute in all |configurations| @@ -336,7 +349,7 @@ def set_attribute(self, name, value, allow_empty=False): ): test_bench.set_attribute(name, value) - def set_generic(self, name, value, allow_empty=False): + def set_generic(self, name: str, value: str, allow_empty: Optional[bool] = False): """ Set a value of generic in all |configurations| @@ -359,7 +372,7 @@ def set_generic(self, name, value, allow_empty=False): ): test_bench.set_generic(name.lower(), value) - def set_parameter(self, name, value, allow_empty=False): + def set_parameter(self, name: str, value: str, allow_empty: Optional[bool] = False): """ Set value of parameter in all |configurations| @@ -382,7 +395,13 @@ def set_parameter(self, name, value, allow_empty=False): ): test_bench.set_generic(name, value) - def set_sim_option(self, name, value, allow_empty=False, overwrite=True): + def set_sim_option( + self, + name: str, + value: str, + allow_empty: Optional[bool] = False, + overwrite: Optional[bool] = True, + ): """ Set simulation option in all |configurations| @@ -406,7 +425,9 @@ def set_sim_option(self, name, value, allow_empty=False, overwrite=True): ): test_bench.set_sim_option(name, value, overwrite) - def set_compile_option(self, name, value, allow_empty=False): + def set_compile_option( + self, name: str, value: str, allow_empty: Optional[bool] = False + ): """ Set compile option of all files @@ -430,7 +451,9 @@ def set_compile_option(self, name, value, allow_empty=False): ): source_file.set_compile_option(name, value) - def add_compile_option(self, name, value, allow_empty=False): + def add_compile_option( + self, name: str, value: str, allow_empty: Optional[bool] = False + ): """ Add compile option to all files @@ -447,7 +470,9 @@ def add_compile_option(self, name, value, allow_empty=False): ): source_file.add_compile_option(name, value) - def get_source_file(self, file_name, library_name=None): + def get_source_file( + self, file_name: Union[str, Path], library_name: Optional[str] = None + ): """ Get a source file @@ -456,22 +481,29 @@ def get_source_file(self, file_name, library_name=None): :returns: A :class:`.SourceFile` object """ - files = self.get_source_files(file_name, library_name, allow_empty=True) + fstr = str(file_name) + + files = self.get_source_files(fstr, library_name, allow_empty=True) if len(files) > 1: raise ValueError( "Found file named '%s' in multiple-libraries, " - "add explicit library_name." % file_name + "add explicit library_name." % fstr ) if not files: if library_name is None: - raise ValueError("Found no file named '%s'" % file_name) + raise ValueError("Found no file named '%s'" % fstr) raise ValueError( - "Found no file named '%s' in library '%s'" % (file_name, library_name) + "Found no file named '%s' in library '%s'" % (fstr, library_name) ) return files[0] - def get_source_files(self, pattern="*", library_name=None, allow_empty=False): + def get_source_files( + self, + pattern="*", + library_name: Optional[str] = None, + allow_empty: Optional[bool] = False, + ): """ Get a list of source files @@ -487,7 +519,7 @@ def get_source_files(self, pattern="*", library_name=None, allow_empty=False): continue if not ( - fnmatch(abspath(source_file.name), pattern) + fnmatch(str(Path(source_file.name).resolve()), pattern) or fnmatch(ostools.simplify_path(source_file.name), pattern) ): continue @@ -508,13 +540,13 @@ def get_source_files(self, pattern="*", library_name=None, allow_empty=False): def add_source_files( # pylint: disable=too-many-arguments self, pattern, - library_name, + library_name: str, preprocessors=None, include_dirs=None, defines=None, - allow_empty=False, + allow_empty: Optional[bool] = False, vhdl_standard: Optional[str] = None, - no_parse=False, + no_parse: Optional[bool] = False, file_type=None, ): """ @@ -552,13 +584,13 @@ def add_source_files( # pylint: disable=too-many-arguments def add_source_file( # pylint: disable=too-many-arguments self, - file_name, - library_name, + file_name: Union[str, Path], + library_name: str, preprocessors=None, include_dirs=None, defines=None, vhdl_standard: Optional[str] = None, - no_parse=False, + no_parse: Optional[bool] = False, file_type=None, ): """ @@ -583,7 +615,7 @@ def add_source_file( # pylint: disable=too-many-arguments """ return self.library(library_name).add_source_file( - file_name=file_name, + file_name=str(file_name), preprocessors=preprocessors, include_dirs=include_dirs, defines=defines, @@ -592,7 +624,9 @@ def add_source_file( # pylint: disable=too-many-arguments file_type=file_type, ) - def _preprocess(self, library_name, file_name, preprocessors): + def _preprocess( + self, library_name: str, file_name: Union[str, Path], preprocessors + ): """ Preprocess file_name within library_name using explicit preprocessors if preprocessors is None then use implicit globally defined processors @@ -604,33 +638,35 @@ def _preprocess(self, library_name, file_name, preprocessors): preprocessors = [p for p in preprocessors if p is not None] preprocessors = self._external_preprocessors + preprocessors + fstr = str(file_name) + if not preprocessors: - return file_name + return fstr + + fname = str(Path(file_name).name) try: code = ostools.read_file(file_name, encoding=HDL_FILE_ENCODING) for preprocessor in preprocessors: - code = preprocessor.run(code, basename(file_name)) + code = preprocessor.run(code, fname) except KeyboardInterrupt: raise KeyboardInterrupt except: # pylint: disable=bare-except traceback.print_exc() - LOGGER.error("Failed to preprocess %s", file_name) - return file_name + LOGGER.error("Failed to preprocess %s", fstr) + return fstr else: - pp_file_name = join( - self._preprocessed_path, library_name, basename(file_name) - ) + pp_file_name = str(Path(self._preprocessed_path) / library_name / fname) idx = 1 while ostools.file_exists(pp_file_name): LOGGER.debug( "Preprocessed file exists '%s', adding prefix", pp_file_name ) - pp_file_name = join( - self._preprocessed_path, - library_name, - "%i_%s" % (idx, basename(file_name)), + pp_file_name = str( + Path(self._preprocessed_path) + / library_name + / ("%i_%s" % (idx, fname)), ) idx += 1 @@ -705,7 +741,7 @@ def main(self, post_run=None): sys.exit(0) - def _create_tests(self, simulator_if): + def _create_tests(self, simulator_if: Union[None, SimulatorInterface]): """ Create the test cases """ @@ -749,7 +785,7 @@ def _create_simulator_if(self): ) sys.exit(1) - if not exists(self._simulator_output_path): + if not Path(self._simulator_output_path).exists(): os.makedirs(self._simulator_output_path) return self._simulator_class.from_args( @@ -800,7 +836,9 @@ def _main_list_only(self): print("Listed %i tests" % test_list.num_tests) return True - def _main_export_json(self, json_file_name): # pylint: disable=too-many-locals + def _main_export_json( + self, json_file_name: Union[str, Path] + ): # pylint: disable=too-many-locals """ Main function when exporting to JSON """ @@ -810,7 +848,7 @@ def _main_export_json(self, json_file_name): # pylint: disable=too-many-locals for source_file in file_objects: files.append( dict( - file_name=abspath(source_file.name), + file_name=str(Path(source_file.name).resolve()), library_name=source_file.library.name, ) ) @@ -850,7 +888,7 @@ def _main_export_json(self, json_file_name): # pylint: disable=too-many-locals tests=tests, ) - with open(json_file_name, "w") as fptr: + with Path(json_file_name).open("w") as fptr: json.dump(json_data, fptr, sort_keys=True, indent=4, separators=(",", ": ")) return True @@ -873,13 +911,13 @@ def _main_compile_only(self): self._compile(simulator_if) return True - def _create_output_path(self, clean): + def _create_output_path(self, clean: bool): """ Create or re-create the output path if necessary """ if clean: ostools.renew_path(self._output_path) - elif not exists(self._output_path): + elif not Path(self._output_path).exists(): os.makedirs(self._output_path) ostools.renew_path(self._preprocessed_path) @@ -890,13 +928,13 @@ def vhdl_standard(self) -> str: @property def _preprocessed_path(self): - return join(self._output_path, "preprocessed") + return str(Path(self._output_path) / "preprocessed") @property def codecs_path(self): - return join(self._output_path, "codecs") + return str(Path(self._output_path) / "codecs") - def _compile(self, simulator_if): + def _compile(self, simulator_if: SimulatorInterface): """ Compile entire project """ @@ -913,7 +951,7 @@ def _compile(self, simulator_if): target_files=target_files, ) - def _get_testbench_files(self, simulator_if): + def _get_testbench_files(self, simulator_if: Union[None, SimulatorInterface]): """ Return the list of all test bench files for the currently selected tests to run """ @@ -940,7 +978,7 @@ def _run_test(self, test_cases, report): runner = TestRunner( report, - join(self._output_path, TEST_OUTPUT_PATH), + str(Path(self._output_path) / TEST_OUTPUT_PATH), verbosity=verbosity, num_threads=self._args.num_threads, fail_fast=self._args.fail_fast, diff --git a/vunit/ui/packagefacade.py b/vunit/ui/packagefacade.py index 379e777b1..9637beb65 100644 --- a/vunit/ui/packagefacade.py +++ b/vunit/ui/packagefacade.py @@ -8,7 +8,7 @@ UI class PackageFacade """ -from os.path import join, splitext +from pathlib import Path from ..com import codec_generator @@ -33,9 +33,9 @@ def generate_codecs( codec_package_name = self._package_name + "_codecs" if output_file_name is None: - codecs_path = join(self._parent.codecs_path, self._library_name) - file_extension = splitext(self._design_unit.source_file.name)[1] - output_file_name = join(codecs_path, codec_package_name + file_extension) + codecs_path = Path(self._parent.codecs_path) / self._library_name + file_extension = Path(self._design_unit.source_file.name).suffix + output_file_name = codecs_path / (codec_package_name + file_extension) codec_generator.generate_codecs( self._design_unit, codec_package_name, used_packages, output_file_name diff --git a/vunit/ui/results.py b/vunit/ui/results.py index eb3057ca4..9e63322ce 100644 --- a/vunit/ui/results.py +++ b/vunit/ui/results.py @@ -8,7 +8,8 @@ UI class Results """ -from os.path import join, basename, normpath +from pathlib import Path +from typing import Dict, Union from .common import TEST_OUTPUT_PATH @@ -45,7 +46,7 @@ def get_report(self): report.tests.update( { test.name: TestResult( - join(self._output_path, TEST_OUTPUT_PATH), + Path(self._output_path) / TEST_OUTPUT_PATH, obj["status"], obj["time"], obj["path"], @@ -63,9 +64,9 @@ class Report(object): :data tests: Dictionary of :class:`TestResult` objects """ - def __init__(self, output_path): - self.output_path = output_path - self.tests = {} + def __init__(self, output_path: Union[str, Path]): + self.output_path = Path(output_path) + self.tests: Dict[str, TestResult] = {} class TestResult(object): @@ -93,20 +94,22 @@ def post_func(results): vu.main(post_run=post_func) """ - def __init__(self, test_output_path, status, time, path): - self._test_output_path = test_output_path + def __init__( + self, test_output_path: Union[str, Path], status, time, path: Union[str, Path] + ): + self._test_output_path = Path(test_output_path) self.status = status self.time = time - self.path = path + self.path = Path(path) @property - def relpath(self): + def relpath(self) -> str: """ If the path is a subdir to the default TEST_OUTPUT_PATH, return the subdir only """ - base = basename(self.path) - return ( + base = self.path.name + return str( base - if normpath(join(self._test_output_path, base)) == normpath(self.path) + if (self._test_output_path / base).resolve() == self.path.resolve() else self.path ) diff --git a/vunit/vhdl/check/tools/generate_check_equal.py b/vunit/vhdl/check/tools/generate_check_equal.py index aeb244305..e8957e385 100644 --- a/vunit/vhdl/check/tools/generate_check_equal.py +++ b/vunit/vhdl/check/tools/generate_check_equal.py @@ -4,7 +4,7 @@ # # Copyright (c) 2014-2020, Lars Asplund lars.anders.asplund@gmail.com -from os.path import join, dirname +from pathlib import Path from string import Template api_template = """ procedure check_equal( @@ -767,14 +767,14 @@ def replace_region(region_name, file_name, new_contents): def main(): - check_api_file_name = join(dirname(__file__), "..", "src", "check_api.vhd") + check_api_file_name = str(Path(__file__).parent.parent / "src" / "check_api.vhd") replace_region("check_equal", check_api_file_name, generate_api()) - check_file_name = join(dirname(__file__), "..", "src", "check.vhd") + check_file_name = str(Path(__file__).parent.parent / "src" / "check.vhd") replace_region("check_equal", check_file_name, generate_impl()) - with open( - join(dirname(__file__), "..", "test", "tb_check_equal.vhd"), "wb" + with (Path(__file__).parent.parent / "test" / "tb_check_equal.vhd").open( + "wb" ) as fptr: fptr.write(generate_test().encode()) diff --git a/vunit/vhdl/check/tools/generate_check_match.py b/vunit/vhdl/check/tools/generate_check_match.py index 4229da772..129755b50 100644 --- a/vunit/vhdl/check/tools/generate_check_match.py +++ b/vunit/vhdl/check/tools/generate_check_match.py @@ -4,7 +4,7 @@ # # Copyright (c) 2014-2020, Lars Asplund lars.anders.asplund@gmail.com -from os.path import join, dirname +from pathlib import Path from string import Template from generate_check_equal import replace_region @@ -448,14 +448,14 @@ def generate_test(): def main(): - check_api_file_name = join(dirname(__file__), "..", "src", "check_api.vhd") + check_api_file_name = str(Path(__file__).parent.parent / "src" / "check_api.vhd") replace_region("check_match", check_api_file_name, generate_api()) - check_file_name = join(dirname(__file__), "..", "src", "check.vhd") + check_file_name = str(Path(__file__).parent.parent / "src" / "check.vhd") replace_region("check_match", check_file_name, generate_impl()) - with open( - join(dirname(__file__), "..", "test", "tb_check_match.vhd"), "wb" + with (Path(__file__).parent.parent / "test" / "tb_check_match.vhd").open( + "wb" ) as fptr: fptr.write(generate_test().encode()) diff --git a/vunit/vhdl/com/run.py b/vunit/vhdl/com/run.py index c1e83b7ec..f55e7ab28 100644 --- a/vunit/vhdl/com/run.py +++ b/vunit/vhdl/com/run.py @@ -4,17 +4,16 @@ # # Copyright (c) 2014-2020, Lars Asplund lars.anders.asplund@gmail.com -from os.path import join, dirname +from pathlib import Path from vunit import VUnit -root = dirname(__file__) +ROOT = Path(__file__).parent -prj = VUnit.from_argv() -prj.add_com() -tb_com_lib = prj.add_library("tb_com_lib") -tb_com_lib.add_source_files(join(root, "test", "*.vhd")) -pkg = tb_com_lib.package("custom_types_pkg") -pkg.generate_codecs( +UI = VUnit.from_argv() +UI.add_com() +TB_COM_LIB = UI.add_library("tb_com_lib") +TB_COM_LIB.add_source_files(ROOT / "test" / "*.vhd") +TB_COM_LIB.package("custom_types_pkg").generate_codecs( codec_package_name="custom_codec_pkg", used_packages=[ "ieee.std_logic_1164", @@ -22,4 +21,5 @@ "tb_com_lib.more_constants_pkg", ], ) -prj.main() + +UI.main() diff --git a/vunit/vhdl/dictionary/run.py b/vunit/vhdl/dictionary/run.py index 8fbb6da42..a90fc1571 100644 --- a/vunit/vhdl/dictionary/run.py +++ b/vunit/vhdl/dictionary/run.py @@ -4,12 +4,12 @@ # # Copyright (c) 2014-2020, Lars Asplund lars.anders.asplund@gmail.com -from os.path import join, dirname +from pathlib import Path from vunit import VUnit -root = dirname(__file__) +ROOT = Path(__file__).parent -ui = VUnit.from_argv() -lib = ui.add_library("lib") -lib.add_source_files(join(root, "test", "*.vhd")) -ui.main() +UI = VUnit.from_argv() +UI.add_library("lib").add_source_files(ROOT / "test" / "*.vhd") + +UI.main() diff --git a/vunit/vhdl/logging/run.py b/vunit/vhdl/logging/run.py index 5378e3cdd..caaeb8be3 100644 --- a/vunit/vhdl/logging/run.py +++ b/vunit/vhdl/logging/run.py @@ -4,11 +4,12 @@ # # Copyright (c) 2014-2020, Lars Asplund lars.anders.asplund@gmail.com -from os.path import join, dirname +from pathlib import Path from vunit import VUnit -root = dirname(__file__) -ui = VUnit.from_argv() -lib = ui.library("vunit_lib") -lib.add_source_files(join(root, "test", "*.vhd")) -ui.main() +ROOT = Path(__file__).parent + +UI = VUnit.from_argv() +UI.library("vunit_lib").add_source_files(ROOT / "test" / "*.vhd") + +UI.main() diff --git a/vunit/vhdl/path/run.py b/vunit/vhdl/path/run.py index 913f518c3..a90fc1571 100644 --- a/vunit/vhdl/path/run.py +++ b/vunit/vhdl/path/run.py @@ -4,11 +4,12 @@ # # Copyright (c) 2014-2020, Lars Asplund lars.anders.asplund@gmail.com -from os.path import join, dirname +from pathlib import Path from vunit import VUnit -root = dirname(__file__) -ui = VUnit.from_argv() -lib = ui.add_library("lib") -lib.add_source_files(join(root, "test", "*.vhd")) -ui.main() +ROOT = Path(__file__).parent + +UI = VUnit.from_argv() +UI.add_library("lib").add_source_files(ROOT / "test" / "*.vhd") + +UI.main() diff --git a/vunit/vhdl/random/run.py b/vunit/vhdl/random/run.py index 041600ff1..74c1b3f47 100644 --- a/vunit/vhdl/random/run.py +++ b/vunit/vhdl/random/run.py @@ -4,13 +4,13 @@ # # Copyright (c) 2014-2020, Lars Asplund lars.anders.asplund@gmail.com -from os.path import join, dirname +from pathlib import Path from vunit import VUnit -root = dirname(__file__) +ROOT = Path(__file__).parent -ui = VUnit.from_argv() -ui.add_random() -lib = ui.library("vunit_lib") -lib.add_source_files(join(root, "test", "*.vhd")) -ui.main() +UI = VUnit.from_argv() +UI.add_random() +UI.library("vunit_lib").add_source_files(ROOT / "test" / "*.vhd") + +UI.main() diff --git a/vunit/vhdl/run/run.py b/vunit/vhdl/run/run.py index 7135a5b94..e7ee5c0de 100644 --- a/vunit/vhdl/run/run.py +++ b/vunit/vhdl/run/run.py @@ -4,12 +4,12 @@ # # Copyright (c) 2014-2020, Lars Asplund lars.anders.asplund@gmail.com -from os.path import join, dirname +from pathlib import Path from vunit import VUnit -root = dirname(__file__) -ui = VUnit.from_argv() +ROOT = Path(__file__).parent -lib = ui.add_library("tb_run_lib") -lib.add_source_files(join(root, "test", "*.vhd")) -ui.main() +UI = VUnit.from_argv() +UI.add_library("tb_run_lib").add_source_files(ROOT / "test" / "*.vhd") + +UI.main() diff --git a/vunit/vhdl/string_ops/run.py b/vunit/vhdl/string_ops/run.py index cb9bb49c1..a90fc1571 100644 --- a/vunit/vhdl/string_ops/run.py +++ b/vunit/vhdl/string_ops/run.py @@ -4,14 +4,12 @@ # # Copyright (c) 2014-2020, Lars Asplund lars.anders.asplund@gmail.com -from os.path import join, dirname +from pathlib import Path from vunit import VUnit -root = dirname(__file__) -common_path = join(root, "..", "common", "test") +ROOT = Path(__file__).parent -ui = VUnit.from_argv() -lib = ui.add_library("lib") -lib.add_source_files(join(root, "test", "*.vhd")) +UI = VUnit.from_argv() +UI.add_library("lib").add_source_files(ROOT / "test" / "*.vhd") -ui.main() +UI.main() diff --git a/vunit/vhdl/verification_components/run.py b/vunit/vhdl/verification_components/run.py index db7e52409..cc8005c0e 100644 --- a/vunit/vhdl/verification_components/run.py +++ b/vunit/vhdl/verification_components/run.py @@ -4,17 +4,17 @@ # # Copyright (c) 2014-2020, Lars Asplund lars.anders.asplund@gmail.com -from os.path import join, dirname +from pathlib import Path from itertools import product from vunit import VUnit -root = dirname(__file__) +ROOT = Path(__file__).parent -ui = VUnit.from_argv() -ui.add_random() -ui.add_verification_components() -lib = ui.library("vunit_lib") -lib.add_source_files(join(root, "test", "*.vhd")) +UI = VUnit.from_argv() +UI.add_random() +UI.add_verification_components() +LIB = UI.library("vunit_lib") +LIB.add_source_files(ROOT / "test" / "*.vhd") def encode(tb_cfg): @@ -67,12 +67,12 @@ def gen_avalon_master_tests(obj, *args): obj.add_config(name=config_name, generics=dict(encoded_tb_cfg=encode(tb_cfg))) -tb_avalon_slave = lib.test_bench("tb_avalon_slave") +tb_avalon_slave = LIB.test_bench("tb_avalon_slave") for test in tb_avalon_slave.get_tests(): gen_avalon_tests(test, [32], [1, 2, 64], [1.0, 0.3], [0.0, 0.4]) -tb_avalon_master = lib.test_bench("tb_avalon_master") +tb_avalon_master = LIB.test_bench("tb_avalon_master") for test in tb_avalon_master.get_tests(): if test.name == "wr single rd single": @@ -82,19 +82,19 @@ def gen_avalon_master_tests(obj, *args): test, [64], [1.0, 0.3], [0.0, 0.7], [1.0, 0.3], [1.0, 0.3] ) -TB_WISHBONE_SLAVE = lib.test_bench("tb_wishbone_slave") +TB_WISHBONE_SLAVE = LIB.test_bench("tb_wishbone_slave") for test in TB_WISHBONE_SLAVE.get_tests(): # TODO strobe_prob not implemented in slave tb gen_wb_tests(test, [8, 32], [1, 64], [1.0], [0.3, 1.0], [0.4, 0.0]) -TB_WISHBONE_MASTER = lib.test_bench("tb_wishbone_master") +TB_WISHBONE_MASTER = LIB.test_bench("tb_wishbone_master") for test in TB_WISHBONE_MASTER.get_tests(): gen_wb_tests(test, [8, 32], [1, 64], [0.3, 1.0], [0.3, 1.0], [0.4, 0.0]) -TB_AXI_STREAM = lib.test_bench("tb_axi_stream") +TB_AXI_STREAM = LIB.test_bench("tb_axi_stream") for id_length in [0, 8]: for dest_length in [0, 8]: @@ -110,7 +110,7 @@ def gen_avalon_master_tests(obj, *args): ), ) -TB_AXI_STREAM_PROTOCOL_CHECKER = lib.test_bench("tb_axi_stream_protocol_checker") +TB_AXI_STREAM_PROTOCOL_CHECKER = LIB.test_bench("tb_axi_stream_protocol_checker") for data_length in [0, 8]: for test in TB_AXI_STREAM_PROTOCOL_CHECKER.get_tests("*passing*tdata*"): @@ -140,4 +140,4 @@ def gen_avalon_master_tests(obj, *args): name="stall_slave", generics=dict(g_stall_percentage_slave=30) ) -ui.main() +UI.main() diff --git a/vunit/vhdl_parser.py b/vunit/vhdl_parser.py index b4e530cbe..1fb05f994 100644 --- a/vunit/vhdl_parser.py +++ b/vunit/vhdl_parser.py @@ -11,7 +11,7 @@ """ import re -from os.path import abspath +from pathlib import Path import logging from vunit.cached import cached from vunit.parsing.encodings import HDL_FILE_ENCODING @@ -32,7 +32,7 @@ def parse(self, file_name): Parse the VHDL code and return a VHDLDesignFile parse result parse result is re-used if content hash found in database """ - file_name = abspath(file_name) + file_name = str(Path(file_name).resolve()) return cached( "CachedVHDLParser.parse", VHDLDesignFile.parse, diff --git a/vunit/vivado/vivado.py b/vunit/vivado/vivado.py index 530e0b8ee..0978c32b4 100644 --- a/vunit/vivado/vivado.py +++ b/vunit/vivado/vivado.py @@ -10,7 +10,7 @@ from subprocess import check_call from os import makedirs -from os.path import abspath, join, dirname, exists, basename +from pathlib import Path def add_from_compile_order_file( @@ -69,15 +69,16 @@ def create_compile_order_file(project_file, compile_order_file, vivado_path=None """ print( "Generating Vivado project compile order into %s ..." - % abspath(compile_order_file) + % str(Path(compile_order_file).resolve()) ) - if not exists(dirname(compile_order_file)): - makedirs(dirname(compile_order_file)) + fpath = Path(compile_order_file) + if not fpath.parent.exists(): + makedirs(str(fpath.parent)) print("Extracting compile order ...") run_vivado( - join(dirname(__file__), "tcl", "extract_compile_order.tcl"), + str(Path(__file__).parent / "tcl" / "extract_compile_order.tcl"), tcl_args=[project_file, compile_order_file], vivado_path=vivado_path, ) @@ -101,13 +102,13 @@ def _read_compile_order(file_name): # Vivado generates duplicate files for different IP:s # using the same underlying libraries. We remove duplicates here - key = (library_name, basename(file_name)) + key = (library_name, Path(file_name).name) if key in unique: continue unique.add(key) if file_type == "Verilog Header": - include_dirs.add(dirname(file_name)) + include_dirs.add(str(Path(file_name).parent)) else: compile_order.append((library_name, file_name)) @@ -121,10 +122,12 @@ def run_vivado(tcl_file_name, tcl_args=None, cwd=None, vivado_path=None): Note: the shell=True is important in windows where Vivado is just a bat file. """ vivado = ( - "vivado" if vivado_path is None else join(abspath(vivado_path), "bin", "vivado") + "vivado" + if vivado_path is None + else str(Path(vivado_path).resolve() / "bin" / "vivado") ) cmd = "{} -nojournal -nolog -notrace -mode batch -source {}".format( - vivado, abspath(tcl_file_name) + vivado, str(Path(tcl_file_name).resolve()) ) if tcl_args is not None: cmd += " -tclargs " + " ".join([str(val) for val in tcl_args]) diff --git a/vunit/vunit_cli.py b/vunit/vunit_cli.py index 1e9731eb7..1f3003028 100644 --- a/vunit/vunit_cli.py +++ b/vunit/vunit_cli.py @@ -39,7 +39,7 @@ """ import argparse -from os.path import join, abspath +from pathlib import Path import os from vunit.sim_if.factory import SIMULATOR_FACTORY from vunit.about import version @@ -80,7 +80,7 @@ def _create_argument_parser(description=None, for_documentation=False): if for_documentation: default_output_path = "./vunit_out" else: - default_output_path = join(abspath(os.getcwd()), "vunit_out") + default_output_path = str(Path(os.getcwd()).resolve() / "vunit_out") parser = argparse.ArgumentParser(description=description)