From 616af05543a6650dfc0a95bcd81f01b6cf8598d9 Mon Sep 17 00:00:00 2001 From: Piotr Bajorowicz Date: Tue, 22 Sep 2020 15:13:17 +0200 Subject: [PATCH 1/2] Workaround for empty macro issue in Riviera-PRO --- vunit/sim_if/rivierapro.py | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/vunit/sim_if/rivierapro.py b/vunit/sim_if/rivierapro.py index 8561c58bd..95d10807e 100644 --- a/vunit/sim_if/rivierapro.py +++ b/vunit/sim_if/rivierapro.py @@ -210,7 +210,10 @@ def compile_verilog_file_command(self, source_file): for include_dir in source_file.include_dirs: args += ["+incdir+%s" % include_dir] for key, value in source_file.defines.items(): - args += ["+define+%s=%s" % (key, value)] + if value != "": + args += ["+define+%s=%s" % (key, value)] + else: + args += ["+define+%s" % (key)] return args def create_library(self, library_name, path, mapped_libraries=None): From 5266f9087c36031f9d4b8aba951bb024b4f6aafd Mon Sep 17 00:00:00 2001 From: Piotr Bajorowicz Date: Wed, 23 Sep 2020 10:44:13 +0200 Subject: [PATCH 2/2] Update rivierapro.py Workaround for empty macro issue in Riviera-PRO - more elegant solution --- vunit/sim_if/rivierapro.py | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/vunit/sim_if/rivierapro.py b/vunit/sim_if/rivierapro.py index 95d10807e..ce839b9d3 100644 --- a/vunit/sim_if/rivierapro.py +++ b/vunit/sim_if/rivierapro.py @@ -210,10 +210,9 @@ def compile_verilog_file_command(self, source_file): for include_dir in source_file.include_dirs: args += ["+incdir+%s" % include_dir] for key, value in source_file.defines.items(): - if value != "": - args += ["+define+%s=%s" % (key, value)] - else: - args += ["+define+%s" % (key)] + args += ["+define+%s" % key] + if value: + args[-1] += "=%s" % value return args def create_library(self, library_name, path, mapped_libraries=None):