From 129d910560a5f9d6e03ddec6c3d3928b8d4444e3 Mon Sep 17 00:00:00 2001
From: Evan Haas <evan@lagerdata.com>
Date: Fri, 2 Aug 2024 05:49:17 -0700
Subject: [PATCH] Zig update: remove some deprecated targets

---
 src/aro/Compilation.zig        |  2 +-
 src/aro/Driver/GCCDetector.zig |  2 +-
 src/aro/target.zig             | 18 +++---------------
 src/aro/toolchains/Linux.zig   |  1 -
 4 files changed, 5 insertions(+), 18 deletions(-)

diff --git a/src/aro/Compilation.zig b/src/aro/Compilation.zig
index f94e72e2..1a1b5307 100644
--- a/src/aro/Compilation.zig
+++ b/src/aro/Compilation.zig
@@ -368,7 +368,7 @@ fn generateSystemDefines(comp: *Compilation, w: anytype) !void {
             \\#define __sparc_v9__ 1
             \\
         ),
-        .sparc, .sparcel => try w.writeAll(
+        .sparc => try w.writeAll(
             \\#define __sparc__ 1
             \\#define __sparc 1
             \\
diff --git a/src/aro/Driver/GCCDetector.zig b/src/aro/Driver/GCCDetector.zig
index d13a6398..72025431 100644
--- a/src/aro/Driver/GCCDetector.zig
+++ b/src/aro/Driver/GCCDetector.zig
@@ -376,7 +376,7 @@ fn collectLibDirsAndTriples(
             biarch_libdirs.appendSliceAssumeCapacity(&RISCV32LibDirs);
             biarch_triple_aliases.appendSliceAssumeCapacity(&RISCV32Triples);
         },
-        .sparc, .sparcel => {
+        .sparc => {
             lib_dirs.appendSliceAssumeCapacity(&SPARCv8LibDirs);
             triple_aliases.appendSliceAssumeCapacity(&SPARCv8Triples);
             biarch_libdirs.appendSliceAssumeCapacity(&SPARCv9LibDirs);
diff --git a/src/aro/target.zig b/src/aro/target.zig
index 59ad5c2b..844a11d2 100644
--- a/src/aro/target.zig
+++ b/src/aro/target.zig
@@ -50,13 +50,12 @@ pub fn intPtrType(target: std.Target) Type {
         .xcore,
         .hexagon,
         .m68k,
-        .spir,
         .spirv32,
         .arc,
         .avr,
         => return .{ .specifier = .int },
 
-        .sparc, .sparcel => switch (target.os.tag) {
+        .sparc => switch (target.os.tag) {
             .netbsd, .openbsd => {},
             else => return .{ .specifier = .int },
         },
@@ -138,7 +137,7 @@ pub fn defaultFunctionAlignment(target: std.Target) u8 {
     return switch (target.cpu.arch) {
         .arm, .armeb => 4,
         .aarch64, .aarch64_be => 4,
-        .sparc, .sparcel, .sparc64 => 4,
+        .sparc, .sparc64 => 4,
         .riscv64 => 2,
         else => 1,
     };
@@ -432,7 +431,7 @@ pub fn ldEmulationOption(target: std.Target, arm_endianness: ?std.builtin.Endian
         .powerpc64le => "elf64lppc",
         .riscv32 => "elf32lriscv",
         .riscv64 => "elf64lriscv",
-        .sparc, .sparcel => "elf32_sparc",
+        .sparc => "elf32_sparc",
         .sparc64 => "elf64_sparc",
         .loongarch32 => "elf32loongarch",
         .loongarch64 => "elf64loongarch",
@@ -472,13 +471,11 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target {
         .powerpcle,
         .riscv32,
         .sparc,
-        .sparcel,
         .thumb,
         .thumbeb,
         .x86,
         .xcore,
         .nvptx,
-        .spir,
         .kalimba,
         .lanai,
         .wasm32,
@@ -493,7 +490,6 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target {
         .aarch64_be => copy.cpu.arch = .armeb,
         .nvptx64 => copy.cpu.arch = .nvptx,
         .wasm64 => copy.cpu.arch = .wasm32,
-        .spir64 => copy.cpu.arch = .spir,
         .spirv64 => copy.cpu.arch = .spirv32,
         .loongarch64 => copy.cpu.arch = .loongarch32,
         .mips64 => copy.cpu.arch = .mips,
@@ -519,7 +515,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {
         .lanai,
         .m68k,
         .msp430,
-        .sparcel,
         .spu_2,
         .xcore,
         .xtensa,
@@ -532,7 +527,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {
         .bpfel,
         .nvptx64,
         .wasm64,
-        .spir64,
         .spirv64,
         .loongarch64,
         .mips64,
@@ -556,7 +550,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {
         .powerpcle => copy.cpu.arch = .powerpc64le,
         .riscv32 => copy.cpu.arch = .riscv64,
         .sparc => copy.cpu.arch = .sparc64,
-        .spir => copy.cpu.arch = .spir64,
         .spirv => copy.cpu.arch = .spirv64,
         .spirv32 => copy.cpu.arch = .spirv64,
         .thumb => copy.cpu.arch = .aarch64,
@@ -604,7 +597,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 {
         .riscv64 => "riscv64",
         .sparc => "sparc",
         .sparc64 => "sparc64",
-        .sparcel => "sparcel",
         .s390x => "s390x",
         .thumb => "thumb",
         .thumbeb => "thumbeb",
@@ -614,8 +606,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 {
         .xtensa => "xtensa",
         .nvptx => "nvptx",
         .nvptx64 => "nvptx64",
-        .spir => "spir",
-        .spir64 => "spir64",
         .spirv => "spirv",
         .spirv32 => "spirv32",
         .spirv64 => "spirv64",
@@ -632,8 +622,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 {
 
     const llvm_os = switch (target.os.tag) {
         .freestanding => "unknown",
-        .ananas => "ananas",
-        .cloudabi => "cloudabi",
         .dragonfly => "dragonfly",
         .freebsd => "freebsd",
         .fuchsia => "fuchsia",
diff --git a/src/aro/toolchains/Linux.zig b/src/aro/toolchains/Linux.zig
index ee24c223..a7d8c71b 100644
--- a/src/aro/toolchains/Linux.zig
+++ b/src/aro/toolchains/Linux.zig
@@ -357,7 +357,6 @@ fn getOSLibDir(target: std.Target) []const u8 {
         .powerpc,
         .powerpcle,
         .sparc,
-        .sparcel,
         => return "lib32",
         else => {},
     }