[AIE2] Annotate Tile Memory AS

Xilinx · Aug 9, 2024 · c341c2c · c341c2c
1 parent 887f0f1
commit c341c2c
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Showing 10 changed files with 119 additions and 24 deletions.
diff --git a/llvm/lib/Target/AIE/AIE2AddrSpace.h b/llvm/lib/Target/AIE/AIE2AddrSpace.h
@@ -39,6 +39,7 @@ enum class AddressSpaces {
 };
 
 enum class DMBanks { A, B, C, D };
+enum class TileMemory { TileMemory = 4 };
 
 } // end namespace AIE2
 } // end namespace llvm

diff --git a/llvm/lib/Target/AIE/AIE2Subtarget.cpp b/llvm/lib/Target/AIE/AIE2Subtarget.cpp
@@ -119,6 +119,9 @@ AIE2Subtarget::getMemoryBanksFromAddressSpace(unsigned AddrSpace) const {
     MemoryBanks.set(static_cast<unsigned>(DMBanks::C))
         .set(static_cast<unsigned>(DMBanks::D));
     break;
+  case AddressSpaces::TM:
+    MemoryBanks.set(static_cast<unsigned>(TileMemory::TileMemory));
+    break;
   default:
     // For unimplemented cases assume all
     MemoryBanks.set();

diff --git a/llvm/lib/Target/AIE/AIE2TargetMachine.cpp b/llvm/lib/Target/AIE/AIE2TargetMachine.cpp
@@ -271,6 +271,8 @@ AIE2TargetMachine::getAddressSpaceForPseudoSourceKind(unsigned Kind) const {
   case PseudoSourceValue::Stack:
   case PseudoSourceValue::FixedStack:
     return StackAddrSpace;
+  case PseudoSourceValue::TargetCustom:
+    return static_cast<unsigned>(AIE2::AddressSpaces::TM);
   default:
     return static_cast<unsigned>(AIE2::AddressSpaces::none);
   }

diff --git a/llvm/test/CodeGen/AIE/aie2/GlobalISel/inst-select-store_load_TM.mir b/llvm/test/CodeGen/AIE/aie2/GlobalISel/inst-select-store_load_TM.mir
@@ -18,7 +18,7 @@ body:             |
     ; CHECK-LABEL: name: Read_TM
     ; CHECK: liveins: $p0
     ; CHECK-NEXT: {{  $}}
-    ; CHECK-NEXT: [[LDA_TM:%[0-9]+]]:er = LDA_TM %2:ep :: (load (s32) from custom "TileMemory")
+    ; CHECK-NEXT: [[LDA_TM:%[0-9]+]]:er = LDA_TM %2:ep :: (load (s32) from custom "TileMemory", addrspace 15)
     ; CHECK-NEXT: $r0 = COPY [[LDA_TM]]
     ; CHECK-NEXT: PseudoRET implicit $lr, implicit $r0
     %1:ptrregbank(p0) = COPY $p0
@@ -39,7 +39,7 @@ body:             |
     ; CHECK-LABEL: name: Write_TM
     ; CHECK: liveins: $p0
     ; CHECK-NEXT: {{  $}}
-    ; CHECK-NEXT: ST_TM %1:er, %2:ep :: (store (s32) into custom "TileMemory")
+    ; CHECK-NEXT: ST_TM %1:er, %2:ep :: (store (s32) into custom "TileMemory", addrspace 15)
     ; CHECK-NEXT: PseudoRET implicit $lr
     %1:ptrregbank(p0) = COPY $p0
     G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aie2.write.tm), %0:gprregbank(s32), %5:ptrregbank(p0)

diff --git a/llvm/test/CodeGen/AIE/aie2/schedule/load.mir b/llvm/test/CodeGen/AIE/aie2/schedule/load.mir
@@ -39,7 +39,7 @@ body:             |
     ; CHECK-LABEL: name: load_tm
     ; CHECK: liveins: $p1
     ; CHECK-NEXT: {{  $}}
-    ; CHECK-NEXT: $r6 = LDA_TM killed $p1 :: (load (s32) from custom "TileMemory")
+    ; CHECK-NEXT: $r6 = LDA_TM killed $p1 :: (load (s32) from custom "TileMemory", addrspace 15)
     ; CHECK-NEXT: NOP
     ; CHECK-NEXT: NOP
     ; CHECK-NEXT: NOP

diff --git a/llvm/test/CodeGen/AIE/aie2/schedule/memory_access_DM_TM.mir b/llvm/test/CodeGen/AIE/aie2/schedule/memory_access_DM_TM.mir
@@ -0,0 +1,89 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
+# This file is licensed under the Apache License v2.0 with LLVM Exceptions.
+# See https://llvm.org/LICENSE.txt for license information.
+# SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+#
+# (c) Copyright 2024 Advanced Micro Devices, Inc. or its affiliates
+# RUN: llc -march=aie2 -run-pass=postmisched %topdown-multi %s -o - | FileCheck %s
+
+# This test checks scheduling of LDA_TM with VLDB
+
+---
+name:            LDA_TM_VLDB_from_BankA
+alignment:       16
+body:             |
+  bb.0.entry:
+    ; CHECK-LABEL: name: LDA_TM_VLDB_from_BankA
+    ; CHECK: BUNDLE implicit-def $r0, implicit-def $wl2, implicit killed $p0 {
+    ; CHECK-NEXT:   $r0 = LDA_TM $p0 :: (load (s32) from custom "TileMemory", addrspace 15)
+    ; CHECK-NEXT:   $wl2 = VLDB_dmw_ldb_ag_idx_imm killed $p0, 0 :: (load (<8 x s32>), addrspace 5)
+    ; CHECK-NEXT: }
+    ; CHECK-NEXT: NOP
+    ; CHECK-NEXT: NOP
+    ; CHECK-NEXT: NOP
+    ; CHECK-NEXT: NOP
+    ; CHECK-NEXT: NOP
+    ; CHECK-NEXT: NOP
+    $r0 = LDA_TM $p0 :: (load (s32) from custom "TileMemory")
+    $wl2 = VLDB_dmw_ldb_ag_idx_imm $p0, 0 :: (load (<8 x s32>), addrspace 5)
+...
+
+---
+name:            LDA_TM_VLDB_from_BankB
+alignment:       16
+body:             |
+  bb.0.entry:
+    ; CHECK-LABEL: name: LDA_TM_VLDB_from_BankB
+    ; CHECK: BUNDLE implicit-def $r0, implicit-def $wl2, implicit killed $p0 {
+    ; CHECK-NEXT:   $r0 = LDA_TM $p0 :: (load (s32) from custom "TileMemory", addrspace 15)
+    ; CHECK-NEXT:   $wl2 = VLDB_dmw_ldb_ag_idx_imm killed $p0, 0 :: (load (<8 x s32>), addrspace 6)
+    ; CHECK-NEXT: }
+    ; CHECK-NEXT: NOP
+    ; CHECK-NEXT: NOP
+    ; CHECK-NEXT: NOP
+    ; CHECK-NEXT: NOP
+    ; CHECK-NEXT: NOP
+    ; CHECK-NEXT: NOP
+    $r0 = LDA_TM $p0 :: (load (s32) from custom "TileMemory")
+    $wl2 = VLDB_dmw_ldb_ag_idx_imm $p0, 0 :: (load (<8 x s32>), addrspace 6)
+...
+
+---
+name:            LDA_TM_VLDB_from_BankC
+alignment:       16
+body:             |
+  bb.0.entry:
+    ; CHECK-LABEL: name: LDA_TM_VLDB_from_BankC
+    ; CHECK: BUNDLE implicit-def $r0, implicit-def $wl2, implicit killed $p0 {
+    ; CHECK-NEXT:   $r0 = LDA_TM $p0 :: (load (s32) from custom "TileMemory", addrspace 15)
+    ; CHECK-NEXT:   $wl2 = VLDB_dmw_ldb_ag_idx_imm killed $p0, 0 :: (load (<8 x s32>), addrspace 7)
+    ; CHECK-NEXT: }
+    ; CHECK-NEXT: NOP
+    ; CHECK-NEXT: NOP
+    ; CHECK-NEXT: NOP
+    ; CHECK-NEXT: NOP
+    ; CHECK-NEXT: NOP
+    ; CHECK-NEXT: NOP
+    $r0 = LDA_TM $p0 :: (load (s32) from custom "TileMemory")
+    $wl2 = VLDB_dmw_ldb_ag_idx_imm $p0, 0 :: (load (<8 x s32>), addrspace 7)
+...
+
+---
+name:            LDA_TM_VLDB_from_BankD
+alignment:       16
+body:             |
+  bb.0.entry:
+    ; CHECK-LABEL: name: LDA_TM_VLDB_from_BankD
+    ; CHECK: BUNDLE implicit-def $r0, implicit-def $wl2, implicit killed $p0 {
+    ; CHECK-NEXT:   $r0 = LDA_TM $p0 :: (load (s32) from custom "TileMemory", addrspace 15)
+    ; CHECK-NEXT:   $wl2 = VLDB_dmw_ldb_ag_idx_imm killed $p0, 0 :: (load (<8 x s32>), addrspace 8)
+    ; CHECK-NEXT: }
+    ; CHECK-NEXT: NOP
+    ; CHECK-NEXT: NOP
+    ; CHECK-NEXT: NOP
+    ; CHECK-NEXT: NOP
+    ; CHECK-NEXT: NOP
+    ; CHECK-NEXT: NOP
+    $r0 = LDA_TM $p0 :: (load (s32) from custom "TileMemory")
+    $wl2 = VLDB_dmw_ldb_ag_idx_imm $p0, 0 :: (load (<8 x s32>), addrspace 8)
+...
diff --git a/llvm/test/CodeGen/AIE/aie2/schedule/pre_ra/load_storetm.mir b/llvm/test/CodeGen/AIE/aie2/schedule/pre_ra/load_storetm.mir
@@ -30,9 +30,9 @@ body: |
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:ep = COPY [[COPY]]
     ; CHECK-NEXT: [[LDA_dms_lda_idx_imm1:%[0-9]+]]:er = LDA_dms_lda_idx_imm [[COPY1]], 0 :: (load (s32) from %ir.p0)
     ; CHECK-NEXT: [[MOVXM_lng_cg:%[0-9]+]]:ep_as_32bit = MOVXM_lng_cg -524284
-    ; CHECK-NEXT: ST_TM [[LDA_dms_lda_idx_imm]], [[MOVXM_lng_cg]] :: (store (s32) into custom "TileMemory")
+    ; CHECK-NEXT: ST_TM [[LDA_dms_lda_idx_imm]], [[MOVXM_lng_cg]] :: (store (s32) into custom "TileMemory", addrspace 15)
     ; CHECK-NEXT: [[MOVXM_lng_cg1:%[0-9]+]]:ep_as_32bit = MOVXM_lng_cg -524280
-    ; CHECK-NEXT: ST_TM [[LDA_dms_lda_idx_imm1]], [[MOVXM_lng_cg1]] :: (store (s32) into custom "TileMemory")
+    ; CHECK-NEXT: ST_TM [[LDA_dms_lda_idx_imm1]], [[MOVXM_lng_cg1]] :: (store (s32) into custom "TileMemory", addrspace 15)
     %100:ep = COPY $p0
     %200:er = LDA_dms_lda_idx_imm %100, 0 :: (load (s32) from %ir.p0)
     %300:ep_as_32bit = MOVXM_lng_cg -524284

diff --git a/llvm/test/CodeGen/AIE/aie2/schedule/resource/proc_bus.mir b/llvm/test/CodeGen/AIE/aie2/schedule/resource/proc_bus.mir
@@ -23,8 +23,8 @@ body:             |
     ; CHECK-NEXT:   $p0 = MOV_mv_scl killed $r1
     ; CHECK-NEXT: }
     ; CHECK-NEXT: $p1 = MOV_mv_scl killed $r4
-    ; CHECK-NEXT: ST_TM killed $r0, killed $p0 :: (store (s32) into custom "TileMemory")
-    ; CHECK-NEXT: $r0 = LDA_TM killed $p1 :: (load (s32) from custom "TileMemory")
+    ; CHECK-NEXT: ST_TM killed $r0, killed $p0 :: (store (s32) into custom "TileMemory", addrspace 15)
+    ; CHECK-NEXT: $r0 = LDA_TM killed $p1 :: (load (s32) from custom "TileMemory", addrspace 15)
     ; CHECK-NEXT: NOP
     ; CHECK-NEXT: NOP
     ; CHECK-NEXT: NOP

diff --git a/llvm/test/CodeGen/AIE/aie2/schedule/store.mir b/llvm/test/CodeGen/AIE/aie2/schedule/store.mir
@@ -40,7 +40,7 @@ body:             |
     ; CHECK-NEXT: NOP
     ; CHECK-NEXT: NOP
     ; CHECK-NEXT: NOP
-    ; CHECK-NEXT: ST_TM killed $r6, killed $p0 :: (store (s32) into custom "TileMemory")
+    ; CHECK-NEXT: ST_TM killed $r6, killed $p0 :: (store (s32) into custom "TileMemory", addrspace 15)
     ; CHECK-NEXT: NOP
     $r6 = LDA_dms_lda_idx_imm $p1, 4
     ST_TM $r6, $p0 :: (store (s32) into custom "TileMemory")

diff --git a/llvm/test/CodeGen/AIE/aie2/schedule/tmdep.mir b/llvm/test/CodeGen/AIE/aie2/schedule/tmdep.mir
@@ -75,11 +75,11 @@ body:             |
     liveins: $p0
     ; CHECK-LABEL: name: nodep_wtm_rmem
     ; CHECK: LDA_dms_lda_idx_imm killed renamable $p0, 0 :: (load (s32) from %ir.p)
-    ; CHECK: ST_TM killed renamable $r1, killed renamable $p1 :: (store (s32) into custom "TileMemory")
+    ; CHECK: ST_TM killed renamable $r1, killed renamable $p1 :: (store (s32) into custom "TileMemory", addrspace 15)
 
     renamable $r1 = MOVA_lda_cg 42
     renamable $p1 = MOVXM_lng_cg -524284
-    ST_TM killed renamable $r1, killed renamable $p1 :: (store (s32) into custom "TileMemory")
+    ST_TM killed renamable $r1, killed renamable $p1 :: (store (s32) into custom "TileMemory", addrspace 15)
     renamable $r0 = LDA_dms_lda_idx_imm killed renamable $p0, 0 :: (load (s32) from %ir.p)
     PseudoRET implicit $lr, implicit $r0
 
@@ -99,10 +99,10 @@ body:             |
 
     ; CHECK-LABEL: name: nodep_rtm_wmem
     ; CHECK: ST_dms_sts_idx_imm killed renamable $r1, killed renamable $p0, 0 :: (store (s32) into %ir.p)
-    ; CHECK: renamable $r0 = LDA_TM killed renamable $p1 :: (load (s32) from custom "TileMemory")
+    ; CHECK: renamable $r0 = LDA_TM killed renamable $p1 :: (load (s32) from custom "TileMemory", addrspace 15)
     renamable $p1 = MOVXM_lng_cg -524282
     ST_dms_sts_idx_imm killed renamable $r1, killed renamable $p0, 0 :: (store (s32) into %ir.p)
-    renamable $r0 = LDA_TM killed renamable $p1 :: (load (s32) from custom "TileMemory")
+    renamable $r0 = LDA_TM killed renamable $p1 :: (load (s32) from custom "TileMemory", addrspace 15)
 
 ...
 ---
@@ -118,12 +118,12 @@ body:             |
   bb.0.entry:
     liveins: $p1
     ; CHECK-LABEL: name: true_tm
-    ; CHECK: ST_TM killed renamable $r1, killed renamable $p0 :: (store (s32) into custom "TileMemory")
-    ; CHECK: renamable $r0 = LDA_TM killed renamable $p1 :: (load (s32) from custom "TileMemory")
+    ; CHECK: ST_TM killed renamable $r1, killed renamable $p0 :: (store (s32) into custom "TileMemory", addrspace 15)
+    ; CHECK: renamable $r0 = LDA_TM killed renamable $p1 :: (load (s32) from custom "TileMemory", addrspace 15)
     renamable $r1 = MOVA_lda_cg 42
     renamable $p0 = MOVXM_lng_cg -524283
-    ST_TM killed renamable $r1, renamable $p0 :: (store (s32) into custom "TileMemory")
-    renamable $r0 = LDA_TM killed renamable $p1 :: (load (s32) from custom "TileMemory")
+    ST_TM killed renamable $r1, renamable $p0 :: (store (s32) into custom "TileMemory", addrspace 15)
+    renamable $r0 = LDA_TM killed renamable $p1 :: (load (s32) from custom "TileMemory", addrspace 15)
 
 ...
 ---
@@ -139,11 +139,11 @@ body:             |
   bb.0.entry:
     liveins: $p0, $r1
     ; CHECK-LABEL: name: anti_tm
-    ; CHECK: renamable $r0 = LDA_TM renamable $p0 :: (load (s32) from custom "TileMemory")
-    ; CHECK: ST_TM killed renamable $r1, killed renamable $p0 :: (store (s32) into custom "TileMemory")
-    renamable $r0 = LDA_TM renamable $p0 :: (load (s32) from custom "TileMemory")
+    ; CHECK: renamable $r0 = LDA_TM renamable $p0 :: (load (s32) from custom "TileMemory", addrspace 15)
+    ; CHECK: ST_TM killed renamable $r1, killed renamable $p0 :: (store (s32) into custom "TileMemory", addrspace 15)
+    renamable $r0 = LDA_TM renamable $p0 :: (load (s32) from custom "TileMemory", addrspace 15)
     renamable $r1 = MOVA_lda_cg 42
-    ST_TM killed renamable $r1, renamable $p0 :: (store (s32) into custom "TileMemory")
+    ST_TM killed renamable $r1, renamable $p0 :: (store (s32) into custom "TileMemory", addrspace 15)
 
 ...
 ---
@@ -160,14 +160,14 @@ body:             |
     liveins: $r0, $r1
 
     ; CHECK-LABEL: name: out_tm
-    ; CHECK: ST_TM killed renamable $r3, killed renamable $p0 :: (store (s32) into custom "TileMemory")
-    ; CHECK: ST_TM killed renamable $r0, killed renamable $p0 :: (store (s32) into custom "TileMemory")
+    ; CHECK: ST_TM killed renamable $r3, killed renamable $p0 :: (store (s32) into custom "TileMemory", addrspace 15)
+    ; CHECK: ST_TM killed renamable $r0, killed renamable $p0 :: (store (s32) into custom "TileMemory", addrspace 15)
     renamable $p0 = MOVXM_lng_cg -524283
     renamable $r2 = MOVXM_lng_cg 524288
     renamable $r3 = nsw ADD_add_r_ri renamable $r0, 13, implicit-def $srcarry
-    ST_TM killed renamable $r3, killed renamable $p0 :: (store (s32) into custom "TileMemory")
+    ST_TM killed renamable $r3, killed renamable $p0 :: (store (s32) into custom "TileMemory", addrspace 15)
     renamable $r1 = ADD killed renamable $r1, killed renamable $r2, implicit-def $srcarry
     $p0 = MOV_mv_scl killed $r1
-    ST_TM killed renamable $r0, killed renamable $p0 :: (store (s32) into custom "TileMemory")
+    ST_TM killed renamable $r0, killed renamable $p0 :: (store (s32) into custom "TileMemory", addrspace 15)
 
 ...